DMI: Adjusting structures size / Adding cpu core

This patch adds some correction of the dmi structures but also add the
support of the cpu cores/threads.

1 files changed, 16 insertions, 0 deletions

diff --git a/com32/hdt/hdt-menu-processor.c b/com32/hdt/hdt-menu-processor.c
index ad4a8bae..f28833b5 100644
--- a/com32/hdt/hdt-menu-processor.c
+++ b/com32/hdt/hdt-menu-processor.c
@@ -84,6 +84,22 @@ void compute_processor(struct s_my_menu *menu, struct s_hardware *hardware)
     add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
     menu->items_count++;
 
+    if (hardware->dmi.processor.core_enabled != 0) {
+        snprintf(buffer, sizeof buffer, "CPU Enable: %d", hardware->dmi.processor.core_enabled);
+        snprintf(statbuffer, sizeof statbuffer, "Number of CPU Enabled : %d",
+	     hardware->dmi.processor.core_enabled);
+        add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
+        menu->items_count++;
+    }
+
+    if (hardware->dmi.processor.thread_count != 0) {
+        snprintf(buffer, sizeof buffer, "CPU Thread: %d", hardware->dmi.processor.thread_count);
+        snprintf(statbuffer, sizeof statbuffer, "Number of CPU Threads : %d",
+	     hardware->dmi.processor.thread_count);
+        add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
+        menu->items_count++;
+    }
+
     snprintf(buffer, sizeof buffer, "L1 Cache  : %dK + %dK (I+D)",
 	     hardware->cpu.l1_instruction_cache_size,
 	     hardware->cpu.l1_data_cache_size);