diff options
Diffstat (limited to 'com32/gplinclude/cpuid.h')
| -rw-r--r-- | com32/gplinclude/cpuid.h | 236 |
1 files changed, 144 insertions, 92 deletions
diff --git a/com32/gplinclude/cpuid.h b/com32/gplinclude/cpuid.h index 53a08085..6a33e9cb 100644 --- a/com32/gplinclude/cpuid.h +++ b/com32/gplinclude/cpuid.h @@ -18,9 +18,11 @@ #include <stdbool.h> #include <stdint.h> +#include <stdio.h> #include <cpufeature.h> #include <sys/bitops.h> #include <sys/cpu.h> +#include <sys/io.h> #include <klibc/compiler.h> #define PAGE_SIZE 4096 @@ -28,99 +30,112 @@ #define CPU_MODEL_SIZE 48 #define CPU_VENDOR_SIZE 48 +#define CPU_FLAGS(m_) \ +m_(bool, fpu, /* Onboard FPU */) \ +m_(bool, vme, /* Virtual Mode Extensions */) \ +m_(bool, de, /* Debugging Extensions */) \ +m_(bool, pse, /* Page Size Extensions */) \ +m_(bool, tsc, /* Time Stamp Counter */) \ +m_(bool, msr, /* Model-Specific Registers, RDMSR, WRMSR */) \ +m_(bool, pae, /* Physical Address Extensions */) \ +m_(bool, mce, /* Machine Check Architecture */) \ +m_(bool, cx8, /* CMPXCHG8 instruction */) \ +m_(bool, apic, /* Onboard APIC */) \ +m_(bool, sep, /* SYSENTER/SYSEXIT */) \ +m_(bool, mtrr, /* Memory Type Range Registers */) \ +m_(bool, pge, /* Page Global Enable */) \ +m_(bool, mca, /* Machine Check Architecture */) \ +m_(bool, cmov, /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */) \ +m_(bool, pat, /* Page Attribute Table */) \ +m_(bool, pse_36, /* 36-bit PSEs */) \ +m_(bool, psn, /* Processor serial number */) \ +m_(bool, clflsh, /* Supports the CLFLUSH instruction */) \ +m_(bool, dts, /* Debug Trace Store */) \ +m_(bool, acpi, /* ACPI via MSR */) \ +m_(bool, pbe, /* Pending Break Enable */) \ +m_(bool, mmx, /* Multimedia Extensions */) \ +m_(bool, fxsr, /* FXSAVE and FXRSTOR instructions (fast save and restore of FPU context), and CR4.OSFXSR available */) \ +m_(bool, sse, /* Streaming SIMD Extensions */) \ +m_(bool, sse2, /* Streaming SIMD Extensions 2 */) \ +m_(bool, ss, /* CPU self snoop */) \ +m_(bool, htt, /* Hyper-Threading */) \ +m_(bool, acc, /* Automatic clock control */) \ +m_(bool, syscall, /* SYSCALL/SYSRET */) \ +m_(bool, mp, /* MP Capable. */) \ +m_(bool, nx, /* Execute Disable */) \ +m_(bool, mmxext, /* AMD MMX extensions */) \ +m_(bool, fxsr_opt, /* FXSAVE/FXRSTOR optimizations */) \ +m_(bool, gbpages, /* "pdpe1gb" GB pages */) \ +m_(bool, rdtscp, /* RDTSCP */) \ +m_(bool, lm, /* Long Mode (x86-64) */) \ +m_(bool, nowext, /* AMD 3DNow! extensions */) \ +m_(bool, now, /* 3DNow! */) \ +m_(bool, smp, /* A smp configuration has been found */) \ +m_(bool, pni, /* Streaming SIMD Extensions-3 */) \ +m_(bool, pclmulqd, /* PCLMULQDQ instruction */) \ +m_(bool, dtes64, /* 64-bit Debug Store */) \ +m_(bool, vmx, /* Hardware virtualization */) \ +m_(bool, smx, /* Safer Mode */) \ +m_(bool, est, /* Enhanced SpeedStep */) \ +m_(bool, tm2, /* Thermal Monitor 2 */) \ +m_(bool, sse3, /* Supplemental SSE-3 */) \ +m_(bool, cid, /* Context ID */) \ +m_(bool, fma, /* Fused multiply-add */) \ +m_(bool, cx16, /* CMPXCHG16B */) \ +m_(bool, xtpr, /* Send Task Priority Messages */) \ +m_(bool, pdcm, /* Performance Capabilities */) \ +m_(bool, dca, /* Direct Cache Access */) \ +m_(bool, xmm4_1, /* "sse4_1" SSE-4.1 */) \ +m_(bool, xmm4_2, /* "sse4_2" SSE-4.2 */) \ +m_(bool, x2apic, /* x2APIC */) \ +m_(bool, movbe, /* MOVBE instruction */) \ +m_(bool, popcnt, /* POPCNT instruction */) \ +m_(bool, aes, /* AES Instruction */) \ +m_(bool, xsave, /* XSAVE/XRSTOR/XSETBV/XGETBV */) \ +m_(bool, osxsave, /* XSAVE enabled in the OS */) \ +m_(bool, avx, /* Advanced Vector Extensions */) \ +m_(bool, hypervisor, /* Running on a hypervisor */) \ +m_(bool, ace2, /* Advanced Cryptography Engine v2 */) \ +m_(bool, ace2_en, /* ACE v2 enabled */) \ +m_(bool, phe, /* PadLock Hash Engine */) \ +m_(bool, phe_en, /* PadLock Hash Engine Enabled */) \ +m_(bool, pmm, /* PadLock Montgomery Multiplier */) \ +m_(bool, pmm_en, /* PadLock Montgomery Multiplier enabled */) \ +m_(bool, svm, /* Secure virtual machine */) \ +m_(bool, extapic, /* Extended APIC space */) \ +m_(bool, cr8_legacy, /* CR8 in 32-bit mode */) \ +m_(bool, abm, /* Advanced bit manipulation */) \ +m_(bool, sse4a, /* SSE4-A */) \ +m_(bool, misalignsse, /* Misaligned SSE mode */) \ +m_(bool, nowprefetch, /* 3DNow prefetch instructions */) \ +m_(bool, osvw, /* OS Visible Workaround */) \ +m_(bool, ibs, /* Instruction Based Sampling */) \ +m_(bool, sse5, /* SSE5 */) \ +m_(bool, skinit, /* SKINIT/STGI instructions */) \ +m_(bool, wdt, /* Watchdog Timer */) \ +m_(bool, ida, /* Intel Dynamic Acceleration */) \ +m_(bool, arat, /* Always Running APIC Timer */) \ +m_(bool, tpr_shadow, /* Intel TPR Shadow */) \ +m_(bool, vnmi, /* Intel Virtual NMI */) \ +m_(bool, flexpriority, /* Intel FlexPriority */) \ +m_(bool, ept, /* Intel Extended Page Table */) \ +m_(bool, vpid, /* Intel Virtual Processor ID */) + +#define STRUCT_MEMBERS(type_, name_, comment_) type_ name_; + +#define STRUCT_MEMBER_NAMES(type_, name_, comment_) #name_ , + +#define STRUCTURE_MEMBER_OFFSETS(type_, name_, comment_) \ + offsetof(s_cpu_flags, name_), + typedef struct { - bool fpu; /* Onboard FPU */ - bool vme; /* Virtual Mode Extensions */ - bool de; /* Debugging Extensions */ - bool pse; /* Page Size Extensions */ - bool tsc; /* Time Stamp Counter */ - bool msr; /* Model-Specific Registers, RDMSR, WRMSR */ - bool pae; /* Physical Address Extensions */ - bool mce; /* Machine Check Architecture */ - bool cx8; /* CMPXCHG8 instruction */ - bool apic; /* Onboard APIC */ - bool sep; /* SYSENTER/SYSEXIT */ - bool mtrr; /* Memory Type Range Registers */ - bool pge; /* Page Global Enable */ - bool mca; /* Machine Check Architecture */ - bool cmov; /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ - bool pat; /* Page Attribute Table */ - bool pse_36; /* 36-bit PSEs */ - bool psn; /* Processor serial number */ - bool clflsh; /* Supports the CLFLUSH instruction */ - bool dts; /* Debug Trace Store */ - bool acpi; /* ACPI via MSR */ - bool pbe; /* Pending Break Enable */ - bool mmx; /* Multimedia Extensions */ - bool fxsr; /* FXSAVE and FXRSTOR instructions (fast save and restore */ - /* of FPU context), and CR4.OSFXSR available */ - bool sse; /* Streaming SIMD Extensions */ - bool sse2; /* Streaming SIMD Extensions 2 */ - bool ss; /* CPU self snoop */ - bool htt; /* Hyper-Threading */ - bool acc; /* Automatic clock control */ - bool syscall; /* SYSCALL/SYSRET */ - bool mp; /* MP Capable. */ - bool nx; /* Execute Disable */ - bool mmxext; /* AMD MMX extensions */ - bool fxsr_opt; /* FXSAVE/FXRSTOR optimizations */ - bool gbpages; /* "pdpe1gb" GB pages */ - bool rdtscp; /* RDTSCP */ - bool lm; /* Long Mode (x86-64) */ - bool nowext; /* AMD 3DNow! extensions */ - bool now; /* 3DNow! */ - bool smp; /* A smp configuration has been found */ - bool pni; /* Streaming SIMD Extensions-3 */ - bool pclmulqd; /* PCLMULQDQ instruction */ - bool dtes64; /* 64-bit Debug Store */ - bool vmx; /* Hardware virtualization */ - bool smx; /* Safer Mode */ - bool est; /* Enhanced SpeedStep */ - bool tm2; /* Thermal Monitor 2 */ - bool sse3; /* Supplemental SSE-3 */ - bool cid; /* Context ID */ - bool fma; /* Fused multiply-add */ - bool cx16; /* CMPXCHG16B */ - bool xtpr; /* Send Task Priority Messages */ - bool pdcm; /* Performance Capabilities */ - bool dca; /* Direct Cache Access */ - bool xmm4_1; /* "sse4_1" SSE-4.1 */ - bool xmm4_2; /* "sse4_2" SSE-4.2 */ - bool x2apic; /* x2APIC */ - bool movbe; /* MOVBE instruction */ - bool popcnt; /* POPCNT instruction */ - bool aes; /* AES Instruction */ - bool xsave; /* XSAVE/XRSTOR/XSETBV/XGETBV */ - bool osxsave; /* XSAVE enabled in the OS */ - bool avx; /* Advanced Vector Extensions */ - bool hypervisor; /* Running on a hypervisor */ - bool ace2; /* Advanced Cryptography Engine v2 */ - bool ace2_en; /* ACE v2 enabled */ - bool phe; /* PadLock Hash Engine */ - bool phe_en; /* PadLock Hash Engine Enabled */ - bool pmm; /* PadLock Montgomery Multiplier */ - bool pmm_en; /* PadLock Montgomery Multiplier enabled */ - bool svm; /* Secure virtual machine */ - bool extapic; /* Extended APIC space */ - bool cr8_legacy; /* CR8 in 32-bit mode */ - bool abm; /* Advanced bit manipulation */ - bool sse4a; /* SSE4-A */ - bool misalignsse; /* Misaligned SSE mode */ - bool nowprefetch; /* 3DNow prefetch instructions */ - bool osvw; /* OS Visible Workaround */ - bool ibs; /* Instruction Based Sampling */ - bool sse5; /* SSE5 */ - bool skinit; /* SKINIT/STGI instructions */ - bool wdt; /* Watchdog Timer */ - bool ida; /* Intel Dynamic Acceleration */ - bool arat; /* Always Running APIC Timer */ - bool tpr_shadow; /* Intel TPR Shadow */ - bool vnmi; /* Intel Virtual NMI */ - bool flexpriority; /* Intel FlexPriority */ - bool ept; /* Intel Extended Page Table */ - bool vpid; /* Intel Virtual Processor ID */ + CPU_FLAGS(STRUCT_MEMBERS) } s_cpu_flags; +extern size_t cpu_flags_offset[]; +extern const char *cpu_flags_names[]; +extern size_t cpu_flags_count; + typedef struct { char vendor[CPU_VENDOR_SIZE]; uint8_t vendor_id; @@ -135,6 +150,7 @@ typedef struct { s_cpu_flags flags; } s_cpu; +extern bool get_cpu_flag_value_from_name(s_cpu *cpu, const char * flag); /**********************************************************************************/ /**********************************************************************************/ /* From this point this is some internal stuff mainly taken from the linux kernel */ @@ -171,11 +187,37 @@ typedef struct { #define X86_VENDOR_RISE 6 #define X86_VENDOR_TRANSMETA 7 #define X86_VENDOR_NSC 8 -#define X86_VENDOR_NUM 9 -#define X86_VENDOR_UNKNOWN 0xff +#define X86_VENDOR_UNKNOWN 9 +#define X86_VENDOR_NUM 10 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) +// Taken from asm/processor-flags.h +// NSC/Cyrix CPU configuration register indexes +#define CX86_CCR2 0xc2 +#define CX86_CCR3 0xc3 +#define CX86_DIR0 0xfe +#define CX86_DIR1 0xff + +static const char Cx86_model[][9] = { + "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ", + "M II ", "Unknown" +}; + +static const char Cx486_name[][5] = { + "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx", + "SRx2", "DRx2" +}; + +static const char Cx486S_name[][4] = { + "S", "S2", "Se", "S2e" +}; + +static const char Cx486D_name[][4] = { + "DX", "DX2", "?", "?", "?", "DX4" +}; + + /* * CPU type and hardware bug flags. Kept separately for each CPU. * Members of this structure are referenced in head.S, so think twice @@ -260,6 +302,16 @@ struct intel_mp_floating { uint8_t mpf_feature5; /* Unused (0) */ }; +static inline uint8_t getCx86(uint8_t reg) { + outb(reg, 0x22); + return inb(0x23); +} + +static inline void setCx86(uint8_t reg, uint8_t data) { + outb(reg, 0x22); + outb(data, 0x23); +} + extern void get_cpu_vendor(struct cpuinfo_x86 *c); extern void detect_cpu(s_cpu * cpu); #endif |