diff options
Diffstat (limited to 'gpxe/src/drivers/infiniband')
| -rw-r--r-- | gpxe/src/drivers/infiniband/MT25218_PRM.h | 3462 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/MT25408_PRM.h | 3319 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/arbel.c | 2247 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/arbel.h | 544 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/hermon.c | 2752 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/hermon.h | 610 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/linda.c | 2432 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/linda.h | 276 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/linda_fw.c | 1069 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/mlx_bitops.h | 223 | ||||
| -rw-r--r-- | gpxe/src/drivers/infiniband/qib_7220_regs.h | 1762 | ||||
| -rwxr-xr-x | gpxe/src/drivers/infiniband/qib_genbits.pl | 116 |
12 files changed, 0 insertions, 18812 deletions
diff --git a/gpxe/src/drivers/infiniband/MT25218_PRM.h b/gpxe/src/drivers/infiniband/MT25218_PRM.h deleted file mode 100644 index f1b7c1ff..00000000 --- a/gpxe/src/drivers/infiniband/MT25218_PRM.h +++ /dev/null @@ -1,3462 +0,0 @@ -/* - This software is available to you under a choice of one of two - licenses. You may choose to be licensed under the terms of the GNU - General Public License (GPL) Version 2, available at - <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD - license, available in the LICENSE.TXT file accompanying this - software. These details are also available at - <http://openib.org/license.html>. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - SOFTWARE. - - Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. -*/ - -FILE_LICENCE ( GPL2_ONLY ); - -/*** - *** This file was generated at "Tue Nov 22 15:21:23 2005" - *** by: - *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix arbelprm_ -bits -fixnames MT25218_PRM.csp - ***/ - -#ifndef H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H -#define H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H - -/* UD Address Vector */ - -struct arbelprm_ud_address_vector_st { /* Little Endian */ - pseudo_bit_t pd[0x00018]; /* Protection Domain */ - pseudo_bit_t port_number[0x00002]; /* Port number - 1 - Port 1 - 2 - Port 2 - other - reserved */ - pseudo_bit_t reserved0[0x00006]; -/* -------------- */ - pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ - pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ - pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ - pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control. - 0 - 4X injection rate - 1 - 1X injection rate - other - reserved - */ - pseudo_bit_t reserved2[0x00001]; - pseudo_bit_t msg[0x00002]; /* Max Message size, size is 256*2^MSG bytes */ - pseudo_bit_t reserved3[0x00002]; - pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table - mgid_index = (port_number-1) * 2^log_max_gid + gid_index - Where: - 1. log_max_gid is taken from QUERY_DEV_LIM command - 2. gid_index is the index to the GID table */ - pseudo_bit_t reserved4[0x0000a]; -/* -------------- */ - pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ - pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ - pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ -/* -------------- */ - pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ -/* -------------- */ - pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ -/* -------------- */ - pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ -/* -------------- */ - pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */ -/* -------------- */ -}; - -/* Send doorbell */ - -struct arbelprm_send_doorbell_st { /* Little Endian */ - pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */ - pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */ - pseudo_bit_t reserved0[0x00002]; - pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */ - pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */ -/* -------------- */ - pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */ - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ -/* -------------- */ -}; - -/* ACCESS_LAM_inject_errors_input_modifier */ - -struct arbelprm_access_lam_inject_errors_input_modifier_st { /* Little Endian */ - pseudo_bit_t index3[0x00007]; - pseudo_bit_t q3[0x00001]; - pseudo_bit_t index2[0x00007]; - pseudo_bit_t q2[0x00001]; - pseudo_bit_t index1[0x00007]; - pseudo_bit_t q1[0x00001]; - pseudo_bit_t index0[0x00007]; - pseudo_bit_t q0[0x00001]; -/* -------------- */ -}; - -/* ACCESS_LAM_inject_errors_input_parameter */ - -struct arbelprm_access_lam_inject_errors_input_parameter_st { /* Little Endian */ - pseudo_bit_t ba[0x00002]; /* Bank Address */ - pseudo_bit_t da[0x00002]; /* Dimm Address */ - pseudo_bit_t reserved0[0x0001c]; -/* -------------- */ - pseudo_bit_t ra[0x00010]; /* Row Address */ - pseudo_bit_t ca[0x00010]; /* Column Address */ -/* -------------- */ -}; - -/* */ - -struct arbelprm_recv_wqe_segment_next_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00006]; - pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */ -/* -------------- */ - pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes). - Zero value in NDS field signals end of WQEs? chain. - */ - pseudo_bit_t reserved1[0x0001a]; -/* -------------- */ -}; - -/* Send wqe segment data inline */ - -struct arbelprm_wqe_segment_data_inline_st { /* Little Endian */ - pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */ - pseudo_bit_t reserved0[0x00015]; - pseudo_bit_t always1[0x00001]; -/* -------------- */ - pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t reserved2[0x00040]; -/* -------------- */ -}; - -/* Send wqe segment data ptr */ - -struct arbelprm_wqe_segment_data_ptr_st { /* Little Endian */ - pseudo_bit_t byte_count[0x0001f]; - pseudo_bit_t always0[0x00001]; -/* -------------- */ - pseudo_bit_t l_key[0x00020]; -/* -------------- */ - pseudo_bit_t local_address_h[0x00020]; -/* -------------- */ - pseudo_bit_t local_address_l[0x00020]; -/* -------------- */ -}; - -/* Send wqe segment rd */ - -struct arbelprm_local_invalidate_segment_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - pseudo_bit_t mem_key[0x00018]; - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t reserved2[0x000a0]; -/* -------------- */ -}; - -/* Fast_Registration_Segment */ - -struct arbelprm_fast_registration_segment_st { /* Little Endian */ - pseudo_bit_t reserved0[0x0001b]; - pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */ - pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */ - pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */ - pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */ - pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */ -/* -------------- */ - pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list */ -/* -------------- */ - pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. */ -/* -------------- */ - pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. - page_size should be less than 20. */ - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t zb[0x00001]; /* Zero Based Region */ - pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list */ -/* -------------- */ - pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */ -/* -------------- */ - pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */ -/* -------------- */ - pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */ -/* -------------- */ - pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */ -/* -------------- */ -}; - -/* Send wqe segment atomic */ - -struct arbelprm_wqe_segment_atomic_st { /* Little Endian */ - pseudo_bit_t swap_add_h[0x00020]; -/* -------------- */ - pseudo_bit_t swap_add_l[0x00020]; -/* -------------- */ - pseudo_bit_t compare_h[0x00020]; -/* -------------- */ - pseudo_bit_t compare_l[0x00020]; -/* -------------- */ -}; - -/* Send wqe segment remote address */ - -struct arbelprm_wqe_segment_remote_address_st { /* Little Endian */ - pseudo_bit_t remote_virt_addr_h[0x00020]; -/* -------------- */ - pseudo_bit_t remote_virt_addr_l[0x00020]; -/* -------------- */ - pseudo_bit_t rkey[0x00020]; -/* -------------- */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ -}; - -/* end wqe segment bind */ - -struct arbelprm_wqe_segment_bind_st { /* Little Endian */ - pseudo_bit_t reserved0[0x0001d]; - pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */ - pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window. - */ - pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */ -/* -------------- */ - pseudo_bit_t reserved1[0x0001e]; - pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */ - pseudo_bit_t type[0x00001]; /* Window type. - 0 - Type one window - 1 - Type two window - */ -/* -------------- */ - pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */ -/* -------------- */ - pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */ -/* -------------- */ - pseudo_bit_t start_address_h[0x00020]; -/* -------------- */ - pseudo_bit_t start_address_l[0x00020]; -/* -------------- */ - pseudo_bit_t length_h[0x00020]; -/* -------------- */ - pseudo_bit_t length_l[0x00020]; -/* -------------- */ -}; - -/* Send wqe segment ud */ - -struct arbelprm_wqe_segment_ud_st { /* Little Endian */ - struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ -/* -------------- */ - pseudo_bit_t destination_qp[0x00018]; - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t q_key[0x00020]; -/* -------------- */ - pseudo_bit_t reserved1[0x00040]; -/* -------------- */ -}; - -/* Send wqe segment rd */ - -struct arbelprm_wqe_segment_rd_st { /* Little Endian */ - pseudo_bit_t destination_qp[0x00018]; - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t q_key[0x00020]; -/* -------------- */ - pseudo_bit_t reserved1[0x00040]; -/* -------------- */ -}; - -/* Send wqe segment ctrl */ - -struct arbelprm_wqe_segment_ctrl_send_st { /* Little Endian */ - pseudo_bit_t always1[0x00001]; - pseudo_bit_t s[0x00001]; /* Solicited Event bit. If set, SE (Solicited Event) bit is set in the (last packet of) message. */ - pseudo_bit_t e[0x00001]; /* Event bit. If set, event is generated upon WQE?s completion, if QP is allowed to generate an event. Every WQE with E-bit set generates an event. The C bit must be set on unsignalled QPs if the E bit is set. */ - pseudo_bit_t c[0x00001]; /* Completion Queue bit. Valid for unsignalled QPs only. If set, the CQ is updated upon WQE?s completion */ - pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */ - pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */ - pseudo_bit_t reserved0[0x00001]; - pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */ - pseudo_bit_t reserved1[0x00018]; -/* -------------- */ - pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */ -/* -------------- */ -}; - -/* Send wqe segment next */ - -struct arbelprm_wqe_segment_next_st { /* Little Endian */ - pseudo_bit_t nopcode[0x00005]; /* Next Opcode: OpCode to be used in the next WQE. Encodes the type of operation to be executed on the QP: - ?00000? - NOP. WQE with this opcode creates a completion, but does nothing else - ?01000? - RDMA-write - ?01001? - RDMA-Write with Immediate - ?10000? - RDMA-read - ?10001? - Atomic Compare & swap - ?10010? - Atomic Fetch & Add - ?11000? - Bind memory window - - The encoding for the following operations depends on the QP type: - For RC, UC and RD QP: - ?01010? - SEND - ?01011? - SEND with Immediate - - For UD QP: - the encoding depends on the values of bit[31] of the Q_key field in the Datagram Segment (see Table 39, ?Unreliable Datagram Segment Format - Pointers,? on page 101) of - both the current WQE and the next WQE, as follows: - - If the last WQE Q_Key bit[31] is clear and the next WQE Q_key bit[31] is set : - ?01000? - SEND - ?01001? - SEND with Immediate - - otherwise (if the next WQE Q_key bit[31] is cleared, or the last WQE Q_Key bit[31] is set): - ?01010? - SEND - ?01011? - SEND with Immediate - - All other opcode values are RESERVED, and will result in invalid operation execution. */ - pseudo_bit_t reserved0[0x00001]; - pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */ -/* -------------- */ - pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes). - Zero value in NDS field signals end of WQEs? chain. - */ - pseudo_bit_t f[0x00001]; /* Fence bit. If set, next WQE will start execution only after all previous Read/Atomic WQEs complete. */ - pseudo_bit_t always1[0x00001]; - pseudo_bit_t reserved1[0x00018]; -/* -------------- */ -}; - -/* Address Path */ - -struct arbelprm_address_path_st { /* Little Endian */ - pseudo_bit_t pkey_index[0x00007]; /* PKey table index */ - pseudo_bit_t reserved0[0x00011]; - pseudo_bit_t port_number[0x00002]; /* Specific port associated with this QP/EE. - 1 - Port 1 - 2 - Port 2 - other - reserved */ - pseudo_bit_t reserved1[0x00006]; -/* -------------- */ - pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ - pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ - pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ - pseudo_bit_t reserved2[0x00005]; - pseudo_bit_t rnr_retry[0x00003]; /* RNR retry count (see C9-132 in IB spec Vol 1) - 0-6 - number of retries - 7 - infinite */ -/* -------------- */ - pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ - pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control. - 0 - 100% injection rate - 1 - 25% injection rate - 2 - 12.5% injection rate - 3 - 50% injection rate - other - reserved */ - pseudo_bit_t reserved3[0x00005]; - pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table */ - pseudo_bit_t reserved4[0x00005]; - pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details. - The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */ -/* -------------- */ - pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ - pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ - pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ -/* -------------- */ - pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ -/* -------------- */ - pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ -/* -------------- */ - pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ -/* -------------- */ - pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */ -/* -------------- */ -}; - -/* HCA Command Register (HCR) */ - -struct arbelprm_hca_command_register_st { /* Little Endian */ - pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */ -/* -------------- */ - pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */ -/* -------------- */ - pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */ -/* -------------- */ - pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */ -/* -------------- */ - pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */ -/* -------------- */ - pseudo_bit_t reserved0[0x00010]; - pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */ -/* -------------- */ - pseudo_bit_t opcode[0x0000c]; /* Command opcode */ - pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */ - pseudo_bit_t reserved1[0x00006]; - pseudo_bit_t e[0x00001]; /* Event Request - 0 - Don't report event (software will poll the GO bit) - 1 - Report event to EQ when the command completes */ - pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR) - Software can write to the HCR only if Go bit is cleared. - Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */ - pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared) - 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */ -/* -------------- */ -}; - -/* CQ Doorbell */ - -struct arbelprm_cq_cmd_doorbell_st { /* Little Endian */ - pseudo_bit_t cqn[0x00018]; /* CQ number accessed */ - pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ - 0x0 - Reserved - 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter. - 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter. - 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated - Other - Reserved */ - pseudo_bit_t reserved0[0x00001]; - pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ. - This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited - completion or Request notification for multiple completions doorbells after receiving completion notification. - This field is initialized to Zero */ - pseudo_bit_t reserved1[0x00002]; -/* -------------- */ - pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */ -/* -------------- */ -}; - -/* RD-send doorbell */ - -struct arbelprm_rd_send_doorbell_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram) - Must be zero for Nop and Bind operations */ -/* -------------- */ - pseudo_bit_t reserved1[0x00008]; - pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ -/* -------------- */ - struct arbelprm_send_doorbell_st send_doorbell;/* Send Parameters */ -/* -------------- */ -}; - -/* Multicast Group Member QP */ - -struct arbelprm_mgmqp_st { /* Little Endian */ - pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */ - pseudo_bit_t reserved0[0x00007]; - pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */ -/* -------------- */ -}; - -/* vsd */ - -struct arbelprm_vsd_st { /* Little Endian */ - pseudo_bit_t vsd_dw0[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw1[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw2[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw3[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw4[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw5[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw6[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw7[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw8[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw9[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw10[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw11[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw12[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw13[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw14[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw15[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw16[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw17[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw18[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw19[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw20[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw21[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw22[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw23[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw24[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw25[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw26[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw27[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw28[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw29[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw30[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw31[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw32[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw33[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw34[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw35[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw36[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw37[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw38[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw39[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw40[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw41[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw42[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw43[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw44[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw45[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw46[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw47[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw48[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw49[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw50[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw51[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw52[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw53[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw54[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw55[0x00020]; -/* -------------- */ -}; - -/* ACCESS_LAM_inject_errors */ - -struct arbelprm_access_lam_inject_errors_st { /* Little Endian */ - struct arbelprm_access_lam_inject_errors_input_parameter_st access_lam_inject_errors_input_parameter; -/* -------------- */ - struct arbelprm_access_lam_inject_errors_input_modifier_st access_lam_inject_errors_input_modifier; -/* -------------- */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ -}; - -/* Logical DIMM Information */ - -struct arbelprm_dimminfo_st { /* Little Endian */ - pseudo_bit_t dimmsize[0x00010]; /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t dimmstatus[0x00001]; /* DIMM Status - 0 - Enabled - 1 - Disabled - */ - pseudo_bit_t dh[0x00001]; /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */ - pseudo_bit_t wo[0x00001]; /* When set, the DIMM is write only. - If data integrity is configured (other than none), the DIMM must be - only targeted by write transactions where the address and size are multiples of 16 bytes. */ - pseudo_bit_t reserved1[0x00005]; -/* -------------- */ - pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM - 1 - DIMM SPD was read from InfiniHost-III-EX NVMEM */ - pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits. - Valid only if spd bit is 0. */ - pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */ - pseudo_bit_t syn[0x00004]; /* Error syndrome (valid regardless of status value) - 0 - DIMM has no error - 1 - SPD error (e.g. checksum error, no response, error while reading) - 2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2) - 3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict) - 5 - DIMM size trimmed due to configuration (size exceeds) - other - Error, reserved - */ - pseudo_bit_t reserved2[0x00016]; -/* -------------- */ - pseudo_bit_t reserved3[0x00040]; -/* -------------- */ - pseudo_bit_t dimm_start_adr_h[0x00020];/* DIMM memory start address [63:32]. This value is valid only when DIMMStatus is 0. */ -/* -------------- */ - pseudo_bit_t dimm_start_adr_l[0x00020];/* DIMM memory start address [31:0]. This value is valid only when DIMMStatus is 0. */ -/* -------------- */ - pseudo_bit_t reserved4[0x00040]; -/* -------------- */ -}; - -/* UAR Parameters */ - -struct arbelprm_uar_params_st { /* Little Endian */ - pseudo_bit_t uar_base_addr_h[0x00020];/* UAR Base (pyhsical) Address [63:32] (QUERY_HCA only) */ -/* -------------- */ - pseudo_bit_t reserved0[0x00014]; - pseudo_bit_t uar_base_addr_l[0x0000c];/* UAR Base (pyhsical) Address [31:20] (QUERY_HCA only) */ -/* -------------- */ - pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page. - Size of UAR Page is 4KB*2^UAR_Page_Size */ - pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */ - pseudo_bit_t reserved1[0x00004]; - pseudo_bit_t log_uar_entry_sz[0x00006];/* Size of UAR Context entry is 2^log_uar_sz in 4KByte pages */ - pseudo_bit_t reserved2[0x0000a]; -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32]. - Number of entries in table is 2^log_max_uars. - Table must be aligned to its size */ -/* -------------- */ - pseudo_bit_t uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0]. - Number of entries in table is 2^log_max_uars. - Table must be aligned to its size. */ -/* -------------- */ - pseudo_bit_t uar_context_base_addr_h[0x00020];/* Base address of UAR Context [63:32]. - Number of entries in table is 2^log_max_uars. - Table must be aligned to its size. */ -/* -------------- */ - pseudo_bit_t uar_context_base_addr_l[0x00020];/* Base address of UAR Context [31:0]. - Number of entries in table is 2^log_max_uars. - Table must be aligned to its size. */ -/* -------------- */ -}; - -/* Translation and Protection Tables Parameters */ - -struct arbelprm_tptparams_st { /* Little Endian */ - pseudo_bit_t mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32]. - Entry size is 64 bytes. - Table must be aligned to its size. - Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ -/* -------------- */ - pseudo_bit_t mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0]. - Entry size is 64 bytes. - Table must be aligned to its size. - Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ -/* -------------- */ - pseudo_bit_t log_mpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the MPT table. */ - pseudo_bit_t reserved0[0x00002]; - pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout - - The field returned in RNR Naks generated when a page fault is detected. - It has no effect when on-demand-paging is not used. */ - pseudo_bit_t reserved1[0x00013]; -/* -------------- */ - pseudo_bit_t reserved2[0x00020]; -/* -------------- */ - pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32]. - Table must be aligned to its size. - Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ -/* -------------- */ - pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0]. - Table must be aligned to its size. - Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ -/* -------------- */ - pseudo_bit_t reserved3[0x00040]; -/* -------------- */ -}; - -/* Multicast Support Parameters */ - -struct arbelprm_multicastparam_st { /* Little Endian */ - pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32]. - The base address must be aligned to the entry size. - Address may be set to 0xFFFFFFFF if multicast is not supported. */ -/* -------------- */ - pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. - The base address must be aligned to the entry size. - Address may be set to 0xFFFFFFFF if multicast is not supported. */ -/* -------------- */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - pseudo_bit_t log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry. - Must be greater than 5 (to allow CTRL and GID sections). - That implies the number of QPs per MC table entry. */ - pseudo_bit_t reserved1[0x00010]; -/* -------------- */ - pseudo_bit_t mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2) - INIT_HCA - the required number of entries - QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */ - pseudo_bit_t reserved2[0x0000f]; -/* -------------- */ - pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */ - pseudo_bit_t reserved3[0x00013]; - pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function - 0 - Default hash function - other - reserved */ - pseudo_bit_t reserved4[0x00005]; -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ -}; - -/* QPC/EEC/CQC/EQC/RDB Parameters */ - -struct arbelprm_qpcbaseaddr_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32] - Table must be aligned on its size */ -/* -------------- */ - pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */ - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t qpc_base_addr_l[0x00019];/* QPC Base Address [31:7] - Table must be aligned on its size */ -/* -------------- */ - pseudo_bit_t reserved2[0x00040]; -/* -------------- */ - pseudo_bit_t eec_base_addr_h[0x00020];/* EEC Base Address [63:32] - Table must be aligned on its size. - Address may be set to 0xFFFFFFFF if RD is not supported. */ -/* -------------- */ - pseudo_bit_t log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */ - pseudo_bit_t reserved3[0x00002]; - pseudo_bit_t eec_base_addr_l[0x00019];/* EEC Base Address [31:7] - Table must be aligned on its size - Address may be set to 0xFFFFFFFF if RD is not supported. */ -/* -------------- */ - pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32] - Table must be aligned on its size - Address may be set to 0xFFFFFFFF if SRQ is not supported. */ -/* -------------- */ - pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */ - pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5] - Table must be aligned on its size - Address may be set to 0xFFFFFFFF if SRQ is not supported. */ -/* -------------- */ - pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32] - Table must be aligned on its size */ -/* -------------- */ - pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */ - pseudo_bit_t reserved4[0x00001]; - pseudo_bit_t cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6] - Table must be aligned on its size */ -/* -------------- */ - pseudo_bit_t reserved5[0x00040]; -/* -------------- */ - pseudo_bit_t eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32] - Table has same number of entries as QPC table. - Table must be aligned to entry size. */ -/* -------------- */ - pseudo_bit_t eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0] - Table has same number of entries as QPC table. - Table must be aligned to entry size. */ -/* -------------- */ - pseudo_bit_t reserved6[0x00040]; -/* -------------- */ - pseudo_bit_t eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32] - Table has same number of entries as EEC table. - Table must be aligned to entry size. - Address may be set to 0xFFFFFFFF if RD is not supported. */ -/* -------------- */ - pseudo_bit_t eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0] - Table has same number of entries as EEC table. - Table must be aligned to entry size. - Address may be set to 0xFFFFFFFF if RD is not supported. */ -/* -------------- */ - pseudo_bit_t reserved7[0x00040]; -/* -------------- */ - pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32] - Address may be set to 0xFFFFFFFF if EQs are not supported. - Table must be aligned to entry size. */ -/* -------------- */ - pseudo_bit_t log_num_eq[0x00004]; /* Log base 2 of number of supported EQs. - Must be 6 or less in InfiniHost-III-EX. */ - pseudo_bit_t reserved8[0x00002]; - pseudo_bit_t eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6] - Address may be set to 0xFFFFFFFF if EQs are not supported. - Table must be aligned to entry size. */ -/* -------------- */ - pseudo_bit_t reserved9[0x00040]; -/* -------------- */ - pseudo_bit_t rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32]. - Address may be set to 0xFFFFFFFF if remote RDMA reads are not supported. - Please refer to QP and EE chapter for further explanation on RDB allocation. */ -/* -------------- */ - pseudo_bit_t rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0]. - Table must be aligned to RDB entry size (32 bytes). - Address may be set to zero if remote RDMA reads are not supported. - Please refer to QP and EE chapter for further explanation on RDB allocation. */ -/* -------------- */ - pseudo_bit_t reserved10[0x00040]; -/* -------------- */ -}; - -/* Header_Log_Register */ - -struct arbelprm_header_log_register_st { /* Little Endian */ - pseudo_bit_t place_holder[0x00020]; -/* -------------- */ - pseudo_bit_t reserved0[0x00060]; -/* -------------- */ -}; - -/* Performance Monitors */ - -struct arbelprm_performance_monitors_st { /* Little Endian */ - pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */ - pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */ - pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */ - pseudo_bit_t reserved0[0x00001]; - pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ - pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ - pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ - pseudo_bit_t reserved1[0x00001]; - pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ - pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ - pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ - pseudo_bit_t reserved2[0x00001]; - pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ - pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ - pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ - pseudo_bit_t reserved3[0x00001]; - pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */ - pseudo_bit_t reserved4[0x00003]; - pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */ - pseudo_bit_t reserved5[0x00003]; -/* -------------- */ - pseudo_bit_t clock_counter[0x00020]; -/* -------------- */ - pseudo_bit_t event_counter1[0x00020]; -/* -------------- */ - pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */ -/* -------------- */ -}; - -/* Receive segment format */ - -struct arbelprm_wqe_segment_ctrl_recv_st { /* Little Endian */ - struct arbelprm_recv_wqe_segment_next_st wqe_segment_next; -/* -------------- */ - pseudo_bit_t reserved0[0x00002]; - pseudo_bit_t reserved1[0x00001]; - pseudo_bit_t reserved2[0x00001]; - pseudo_bit_t reserved3[0x0001c]; -/* -------------- */ - pseudo_bit_t reserved4[0x00020]; -/* -------------- */ -}; - -/* MLX WQE segment format */ - -struct arbelprm_wqe_segment_ctrl_mlx_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00002]; - pseudo_bit_t e[0x00001]; /* WQE event */ - pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */ - pseudo_bit_t icrc[0x00002]; /* icrc field detemines what to do with the last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. Last dword must be 0x0. 1,2 - reserved. 3 - Leave last dword as is. Last dword must not be 0x0. */ - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t sl[0x00004]; - pseudo_bit_t max_statrate[0x00004]; - pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */ - pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */ - pseudo_bit_t reserved2[0x0000e]; -/* -------------- */ - pseudo_bit_t vcrc[0x00010]; /* Packet's VCRC (if not 0 - otherwise computed by HW) */ - pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */ -/* -------------- */ - pseudo_bit_t reserved3[0x00040]; -/* -------------- */ -}; - -/* Send WQE segment format */ - -struct arbelprm_send_wqe_segment_st { /* Little Endian */ - struct arbelprm_wqe_segment_next_st wqe_segment_next;/* Send wqe segment next */ -/* -------------- */ - struct arbelprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */ -/* -------------- */ - struct arbelprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */ -/* -------------- */ - struct arbelprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */ -/* -------------- */ - struct arbelprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */ -/* -------------- */ - pseudo_bit_t reserved0[0x00180]; -/* -------------- */ - struct arbelprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */ -/* -------------- */ - struct arbelprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */ -/* -------------- */ - struct arbelprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ -/* -------------- */ - struct arbelprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */ -/* -------------- */ - struct arbelprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */ -/* -------------- */ - struct arbelprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */ -/* -------------- */ - pseudo_bit_t reserved1[0x00200]; -/* -------------- */ -}; - -/* QP and EE Context Entry */ - -struct arbelprm_queue_pair_ee_context_entry_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t de[0x00001]; /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */ - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm) - 11-Migrated - 00-Armed - 01-Rearm - 10-Reserved - Should be set to 11 for UD QPs and for QPs which do not support APM */ - pseudo_bit_t reserved2[0x00003]; - pseudo_bit_t st[0x00003]; /* Service type (invalid in EE context): - 000-Reliable Connection - 001-Unreliable Connection - 010-Reliable Datagram - 011-Unreliable Datagram - 111-MLX transport (raw bits injection). Used for management QPs and RAW */ - pseudo_bit_t reserved3[0x00009]; - pseudo_bit_t state[0x00004]; /* QP/EE state: - 0 - RST - 1 - INIT - 2 - RTR - 3 - RTS - 4 - SQEr - 5 - SQD (Send Queue Drained) - 6 - ERR - 7 - Send Queue Draining - 8 - Reserved - 9 - Suspended - A- F - Reserved - (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */ -/* -------------- */ - pseudo_bit_t reserved4[0x00020]; -/* -------------- */ - pseudo_bit_t sched_queue[0x00004]; /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */ - pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */ - pseudo_bit_t reserved5[0x00003]; - pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes. - Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ - pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */ - pseudo_bit_t reserved6[0x00001]; - pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. - Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ - pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */ - pseudo_bit_t reserved7[0x00001]; - pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max. - Must be equal to MTU for UD and MLX QPs. */ - pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative): - 0x1 - 256 bytes - 0x2 - 512 - 0x3 - 1024 - 0x4 - 2048 - other - reserved - - Should be configured to 0x4 for UD and MLX QPs. */ -/* -------------- */ - pseudo_bit_t usr_page[0x00018]; /* QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */ - pseudo_bit_t reserved8[0x00008]; -/* -------------- */ - pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained - This field is valid for QUERY and ERR2RST commands only. */ - pseudo_bit_t reserved9[0x00008]; -/* -------------- */ - pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */ - pseudo_bit_t reserved10[0x00008]; -/* -------------- */ - pseudo_bit_t reserved11[0x00040]; -/* -------------- */ - struct arbelprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */ -/* -------------- */ - struct arbelprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */ -/* -------------- */ - pseudo_bit_t rdd[0x00018]; /* Reliable Datagram Domain */ - pseudo_bit_t reserved12[0x00008]; -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* QP protection domain. Not valid (reserved) in EE context. */ - pseudo_bit_t reserved13[0x00008]; -/* -------------- */ - pseudo_bit_t wqe_base_adr_h[0x00020];/* Bits 63:32 of WQE address for both SQ and RQ. - Reserved for EE context. */ -/* -------------- */ - pseudo_bit_t wqe_lkey[0x00020]; /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */ -/* -------------- */ - pseudo_bit_t reserved14[0x00003]; - pseudo_bit_t ssc[0x00001]; /* Send Signaled Completion - 1 - all send WQEs generate CQEs. - 0 - only send WQEs with C bit set generate completion. - Not valid (reserved) in EE context. */ - pseudo_bit_t sic[0x00001]; /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */ - pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only). - The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */ - pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only). - The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */ - pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */ - pseudo_bit_t reserved15[0x00001]; - pseudo_bit_t sae[0x00001]; /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */ - pseudo_bit_t swe[0x00001]; /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */ - pseudo_bit_t sre[0x00001]; /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */ - pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */ - pseudo_bit_t reserved16[0x00002]; - pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */ - pseudo_bit_t flight_lim[0x00004]; /* Number of outstanding (in-flight) messages on the wire allowed for this send queue. - Number of outstanding messages is 2^Flight_Lim. - Use 0xF for unlimited number of outstanding messages. */ - pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */ -/* -------------- */ - pseudo_bit_t reserved17[0x00020]; -/* -------------- */ - pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */ - pseudo_bit_t reserved18[0x00008]; -/* -------------- */ - pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */ - pseudo_bit_t reserved19[0x00008]; -/* -------------- */ - pseudo_bit_t reserved20[0x00006]; - pseudo_bit_t snd_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */ -/* -------------- */ - pseudo_bit_t snd_db_record_index[0x00020];/* Index in the UAR Context Table Entry. - HW uses this index as an offset from the UAR Context Table Entry in order to read this SQ doorbell record. - The entry is obtained via the usr_page field. - Not valid for EE. */ -/* -------------- */ - pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */ - pseudo_bit_t reserved21[0x00008]; -/* -------------- */ - pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */ - pseudo_bit_t reserved22[0x00008]; -/* -------------- */ - pseudo_bit_t reserved23[0x00003]; - pseudo_bit_t rsc[0x00001]; /* 1 - all receive WQEs generate CQEs. - 0 - only receive WQEs with C bit set generate completion. - Not valid (reserved) in EE context. - */ - pseudo_bit_t ric[0x00001]; /* Invalid Credits. - 1 - place "Invalid Credits" to ACKs sent from this queue. - 0 - ACKs report the actual number of end to end credits on the connection. - Not valid (reserved) in EE context. - Must be set to 1 on QPs which are attached to SRQ. */ - pseudo_bit_t reserved24[0x00008]; - pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */ - pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */ - pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */ - pseudo_bit_t reserved25[0x00005]; - pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. - Must be 0 for EE context. */ - pseudo_bit_t reserved26[0x00008]; -/* -------------- */ - pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */ - pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). - Not valid (reserved) in EE context. */ - pseudo_bit_t reserved27[0x00003]; -/* -------------- */ - pseudo_bit_t reserved28[0x00005]; - pseudo_bit_t ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer. - This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */ -/* -------------- */ - pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */ - pseudo_bit_t reserved29[0x00008]; -/* -------------- */ - pseudo_bit_t reserved30[0x00006]; - pseudo_bit_t rcv_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */ -/* -------------- */ - pseudo_bit_t rcv_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue. - HW uses this index as an offset from the UAR Context Table Entry in order to read this RQ doorbell record. - The entry is obtained via the usr_page field. - Not valid for EE. */ -/* -------------- */ - pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams. - On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message. - Not valid (reserved) in EE context. */ -/* -------------- */ - pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. - SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */ - pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */ - pseudo_bit_t reserved31[0x00007]; -/* -------------- */ - pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */ - pseudo_bit_t reserved32[0x00008]; -/* -------------- */ - pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. - Must be 0x0 in SQ initialization. - (QUERY_QPEE only). */ - pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ. - Must be 0x0 in RQ initialization. - (QUERY_QPEE only). */ -/* -------------- */ - pseudo_bit_t reserved33[0x00040]; -/* -------------- */ -}; - -/* Clear Interrupt [63:0] */ - -struct arbelprm_clr_int_st { /* Little Endian */ - pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32] - Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. - This register is write-only. Reading from this register will cause undefined result - */ -/* -------------- */ - pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0] - Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. - This register is write-only. Reading from this register will cause undefined result */ -/* -------------- */ -}; - -/* EQ_Arm_DB_Region */ - -struct arbelprm_eq_arm_db_region_st { /* Little Endian */ - pseudo_bit_t eq_x_arm_h[0x00020]; /* EQ[63:32] X state. - This register is used to Arm EQs when setting the appropriate bits. */ -/* -------------- */ - pseudo_bit_t eq_x_arm_l[0x00020]; /* EQ[31:0] X state. - This register is used to Arm EQs when setting the appropriate bits. */ -/* -------------- */ -}; - -/* EQ Set CI DBs Table */ - -struct arbelprm_eq_set_ci_table_st { /* Little Endian */ - pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved2[0x00020]; -/* -------------- */ - pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved4[0x00020]; -/* -------------- */ - pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ - pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved6[0x00020]; -/* -------------- */ - pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved7[0x00020]; -/* -------------- */ - pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved8[0x00020]; -/* -------------- */ - pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved9[0x00020]; -/* -------------- */ - pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved10[0x00020]; -/* -------------- */ - pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved11[0x00020]; -/* -------------- */ - pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved12[0x00020]; -/* -------------- */ - pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved13[0x00020]; -/* -------------- */ - pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved14[0x00020]; -/* -------------- */ - pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved15[0x00020]; -/* -------------- */ - pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved16[0x00020]; -/* -------------- */ - pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved17[0x00020]; -/* -------------- */ - pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved18[0x00020]; -/* -------------- */ - pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved19[0x00020]; -/* -------------- */ - pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved20[0x00020]; -/* -------------- */ - pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved21[0x00020]; -/* -------------- */ - pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved22[0x00020]; -/* -------------- */ - pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved23[0x00020]; -/* -------------- */ - pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved24[0x00020]; -/* -------------- */ - pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved25[0x00020]; -/* -------------- */ - pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved26[0x00020]; -/* -------------- */ - pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved27[0x00020]; -/* -------------- */ - pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved28[0x00020]; -/* -------------- */ - pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved29[0x00020]; -/* -------------- */ - pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved30[0x00020]; -/* -------------- */ - pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved31[0x00020]; -/* -------------- */ - pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved32[0x00020]; -/* -------------- */ - pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved33[0x00020]; -/* -------------- */ - pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved34[0x00020]; -/* -------------- */ - pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved35[0x00020]; -/* -------------- */ - pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved36[0x00020]; -/* -------------- */ - pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved37[0x00020]; -/* -------------- */ - pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved38[0x00020]; -/* -------------- */ - pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved39[0x00020]; -/* -------------- */ - pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved40[0x00020]; -/* -------------- */ - pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved41[0x00020]; -/* -------------- */ - pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved42[0x00020]; -/* -------------- */ - pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved43[0x00020]; -/* -------------- */ - pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved44[0x00020]; -/* -------------- */ - pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved45[0x00020]; -/* -------------- */ - pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved46[0x00020]; -/* -------------- */ - pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved47[0x00020]; -/* -------------- */ - pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved48[0x00020]; -/* -------------- */ - pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved49[0x00020]; -/* -------------- */ - pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved50[0x00020]; -/* -------------- */ - pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved51[0x00020]; -/* -------------- */ - pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved52[0x00020]; -/* -------------- */ - pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved53[0x00020]; -/* -------------- */ - pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved54[0x00020]; -/* -------------- */ - pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved55[0x00020]; -/* -------------- */ - pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved56[0x00020]; -/* -------------- */ - pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved57[0x00020]; -/* -------------- */ - pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved58[0x00020]; -/* -------------- */ - pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved59[0x00020]; -/* -------------- */ - pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved60[0x00020]; -/* -------------- */ - pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved61[0x00020]; -/* -------------- */ - pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved62[0x00020]; -/* -------------- */ - pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved63[0x00020]; -/* -------------- */ -}; - -/* InfiniHost-III-EX Configuration Registers */ - -struct arbelprm_configuration_registers_st { /* Little Endian */ - pseudo_bit_t reserved0[0x403400]; -/* -------------- */ - struct arbelprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */ -/* -------------- */ - pseudo_bit_t reserved1[0x3fcb20]; -/* -------------- */ -}; - -/* QP_DB_Record */ - -struct arbelprm_qp_db_record_st { /* Little Endian */ - pseudo_bit_t counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */ - pseudo_bit_t reserved0[0x00010]; -/* -------------- */ - pseudo_bit_t reserved1[0x00005]; - pseudo_bit_t res[0x00003]; /* 0x3 for SQ - 0x4 for RQ - 0x5 for SRQ */ - pseudo_bit_t qp_number[0x00018]; /* QP number */ -/* -------------- */ -}; - -/* CQ_ARM_DB_Record */ - -struct arbelprm_cq_arm_db_record_st { /* Little Endian */ - pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */ -/* -------------- */ - pseudo_bit_t cmd[0x00003]; /* 0x0 - No command - 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter. - 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter. - 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated - Other - Reserved */ - pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */ - pseudo_bit_t res[0x00003]; /* Must be 0x2 */ - pseudo_bit_t cq_number[0x00018]; /* CQ number */ -/* -------------- */ -}; - -/* CQ_CI_DB_Record */ - -struct arbelprm_cq_ci_db_record_st { /* Little Endian */ - pseudo_bit_t counter[0x00020]; /* CQ counter */ -/* -------------- */ - pseudo_bit_t reserved0[0x00005]; - pseudo_bit_t res[0x00003]; /* Must be 0x1 */ - pseudo_bit_t cq_number[0x00018]; /* CQ number */ -/* -------------- */ -}; - -/* Virtual_Physical_Mapping */ - -struct arbelprm_virtual_physical_mapping_st { /* Little Endian */ - pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */ -/* -------------- */ - pseudo_bit_t reserved0[0x0000c]; - pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */ -/* -------------- */ - pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */ -/* -------------- */ - pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */ - pseudo_bit_t reserved1[0x00006]; - pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */ -/* -------------- */ -}; - -/* MOD_STAT_CFG */ - -struct arbelprm_mod_stat_cfg_st { /* Little Endian */ - pseudo_bit_t log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */ - pseudo_bit_t reserved0[0x00001]; - pseudo_bit_t srq[0x00001]; /* When set SRQs are supported */ - pseudo_bit_t srq_m[0x00001]; /* Modify SRQ parameters */ - pseudo_bit_t reserved1[0x00018]; -/* -------------- */ - pseudo_bit_t reserved2[0x007e0]; -/* -------------- */ -}; - -/* SRQ Context */ - -struct arbelprm_srq_context_st { /* Little Endian */ - pseudo_bit_t srqn[0x00018]; /* SRQ number */ - pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. - Maximum value is 0x10, i.e. 16M WQEs. */ - pseudo_bit_t state[0x00004]; /* SRQ State: - 1111 - SW Ownership - 0000 - HW Ownership - 0001 - Error - Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ -/* -------------- */ - pseudo_bit_t l_key[0x00020]; /* memory key (L-Key) to be used to access WQEs. */ -/* -------------- */ - pseudo_bit_t srq_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue. - HW uses this index as an offset from the UAR Context Table Entry in order to read this SRQ doorbell record. - The entry is obtained via the usr_page field. */ -/* -------------- */ - pseudo_bit_t usr_page[0x00018]; /* Index (offset) of user page allocated for this SRQ (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */ - pseudo_bit_t reserved0[0x00005]; - pseudo_bit_t log_rq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */ -/* -------------- */ - pseudo_bit_t wqe_addr_h[0x00020]; /* Bits 63:32 of WQE address (WQE base address) */ -/* -------------- */ - pseudo_bit_t reserved1[0x00006]; - pseudo_bit_t srq_wqe_base_adr_l[0x0001a];/* While opening (creating) the SRQ, this field should contain the address of first descriptor to be posted. */ -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* SRQ protection domain. */ - pseudo_bit_t reserved2[0x00008]; -/* -------------- */ - pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. - Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ - pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */ -/* -------------- */ - pseudo_bit_t srq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. - Must be 0x0 in SRQ initialization. - (QUERY_SRQ only). */ - pseudo_bit_t reserved3[0x00010]; -/* -------------- */ - pseudo_bit_t reserved4[0x00060]; -/* -------------- */ -}; - -/* PBL */ - -struct arbelprm_pbl_st { /* Little Endian */ - pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */ -/* -------------- */ - pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */ -/* -------------- */ - pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */ -/* -------------- */ - pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */ -/* -------------- */ - pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */ -/* -------------- */ - pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */ -/* -------------- */ - pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */ -/* -------------- */ - pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */ -/* -------------- */ -}; - -/* Performance Counters */ - -struct arbelprm_performance_counters_st { /* Little Endian */ - pseudo_bit_t sqpc_access_cnt[0x00020];/* SQPC cache access count */ -/* -------------- */ - pseudo_bit_t sqpc_miss_cnt[0x00020];/* SQPC cache miss count */ -/* -------------- */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - pseudo_bit_t rqpc_access_cnt[0x00020];/* RQPC cache access count */ -/* -------------- */ - pseudo_bit_t rqpc_miss_cnt[0x00020];/* RQPC cache miss count */ -/* -------------- */ - pseudo_bit_t reserved1[0x00040]; -/* -------------- */ - pseudo_bit_t cqc_access_cnt[0x00020];/* CQC cache access count */ -/* -------------- */ - pseudo_bit_t cqc_miss_cnt[0x00020]; /* CQC cache miss count */ -/* -------------- */ - pseudo_bit_t reserved2[0x00040]; -/* -------------- */ - pseudo_bit_t tpt_access_cnt[0x00020];/* TPT cache access count */ -/* -------------- */ - pseudo_bit_t mpt_miss_cnt[0x00020]; /* MPT cache miss count */ -/* -------------- */ - pseudo_bit_t mtt_miss_cnt[0x00020]; /* MTT cache miss count */ -/* -------------- */ - pseudo_bit_t reserved3[0x00620]; -/* -------------- */ -}; - -/* Transport and CI Error Counters */ - -struct arbelprm_transport_and_ci_error_counters_st { /* Little Endian */ - pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */ -/* -------------- */ - pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */ -/* -------------- */ - pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */ -/* -------------- */ - pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */ -/* -------------- */ - pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */ -/* -------------- */ - pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */ -/* -------------- */ - pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */ -/* -------------- */ - pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */ -/* -------------- */ - pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error. - Incremented each time a CQE with error is generated */ -/* -------------- */ - pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error. - Incremented each time a CQE with error is generated */ -/* -------------- */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */ -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */ -/* -------------- */ - pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */ -/* -------------- */ - pseudo_bit_t reserved2[0x00040]; -/* -------------- */ - pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors - NAK-Invalid Request on: - 1. Unsupported OpCode: Responder detected an unsupported OpCode. - 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such - as a missing "Last" packet. - Note: there is no PSN error, thus this does not indicate a dropped packet. */ -/* -------------- */ - pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors. - NAK may or may not be sent. - 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only): - Inbound request OpCode was either reserved, or was for a function not supported by this - QP. (E.g. RDMA or ATOMIC on QP not set up for this). - 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion. - 3. Too many RDMA READ or ATOMIC Requests: There were more requests received - and not ACKed than allowed for the connection. - 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder - detected an error in the sequence of OpCodes; a missing "Last" packet - 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder - detected an error in the sequence of OpCodes; a missing "First" packet - 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able - buffer space. - 7. Length error: RDMA WRITE request message contained too much or too little pay-load - data compared to the DMA length advertised in the first or only packet. - 8. Length error: Payload length was not consistent with the opcode: - a: 0 byte <= "only" <= PMTU bytes - b: ("first" or "middle") == PMTU bytes - c: 1byte <= "last" <= PMTU bytes - 9. Length error: Inbound message exceeded the size supported by the CA port. */ -/* -------------- */ - pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors. - NAK-Remote Access Error on: - R_Key Violation: Responder detected an invalid R_Key while executing an RDMA - Request. */ -/* -------------- */ - pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors. - R_Key Violation Responder detected an R_Key violation while executing an RDMA - request. - NAK may or may not be sent. */ -/* -------------- */ - pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors. - NAK-Remote Operation Error on: - Remote Operation Error: Responder encountered an error, (local to the responder), - which prevented it from completing the request. */ -/* -------------- */ - pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors. - NAK-Remote Operation Error on: - 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing - the packet. - 2. Remote Operation Error: Responder encountered an error, (local to the responder), - which prevented it from completing the request. */ -/* -------------- */ - pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */ -/* -------------- */ - pseudo_bit_t reserved4[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors */ -/* -------------- */ - pseudo_bit_t rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors */ -/* -------------- */ - pseudo_bit_t reserved5[0x00040]; -/* -------------- */ - pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */ -/* -------------- */ - pseudo_bit_t reserved6[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */ -/* -------------- */ - pseudo_bit_t reserved7[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */ -/* -------------- */ - pseudo_bit_t reserved8[0x00380]; -/* -------------- */ - pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */ -/* -------------- */ - pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */ -/* -------------- */ - pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */ -/* -------------- */ - pseudo_bit_t reserved9[0x00020]; -/* -------------- */ - pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */ -/* -------------- */ - pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */ -/* -------------- */ - pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */ -/* -------------- */ - pseudo_bit_t reserved10[0x00020]; -/* -------------- */ - pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */ -/* -------------- */ - pseudo_bit_t reserved11[0x003e0]; -/* -------------- */ - pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */ -/* -------------- */ - pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */ -/* -------------- */ - pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */ -/* -------------- */ - pseudo_bit_t reserved12[0x002a0]; -/* -------------- */ -}; - -/* Event_data Field - HCR Completion Event */ - -struct arbelprm_hcr_completion_event_st { /* Little Endian */ - pseudo_bit_t token[0x00010]; /* HCR Token */ - pseudo_bit_t reserved0[0x00010]; -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t status[0x00008]; /* HCR Status */ - pseudo_bit_t reserved2[0x00018]; -/* -------------- */ - pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */ -/* -------------- */ - pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ -}; - -/* Completion with Error CQE */ - -struct arbelprm_completion_with_error_st { /* Little Endian */ - pseudo_bit_t myqpn[0x00018]; /* Indicates the QP for which completion is being reported */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x00060]; -/* -------------- */ - pseudo_bit_t reserved2[0x00010]; - pseudo_bit_t vendor_code[0x00008]; - pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome: - 0x01 - Local Length Error - 0x02 - Local QP Operation Error - 0x03 - Local EE Context Operation Error - 0x04 - Local Protection Error - 0x05 - Work Request Flushed Error - 0x06 - Memory Window Bind Error - 0x10 - Bad Response Error - 0x11 - Local Access Error - 0x12 - Remote Invalid Request Error - 0x13 - Remote Access Error - 0x14 - Remote Operation Error - 0x15 - Transport Retry Counter Exceeded - 0x16 - RNR Retry Counter Exceeded - 0x20 - Local RDD Violation Error - 0x21 - Remote Invalid RD Request - 0x22 - Remote Aborted Error - 0x23 - Invalid EE Context Number - 0x24 - Invalid EE Context State - other - Reserved - Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t reserved4[0x00006]; - pseudo_bit_t wqe_addr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */ -/* -------------- */ - pseudo_bit_t reserved5[0x00007]; - pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */ - pseudo_bit_t reserved6[0x00010]; - pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for. - - The following values are reported in case of completion with error: - 0xFE - For completion with error on Receive Queues - 0xFF - For completion with error on Send Queues */ -/* -------------- */ -}; - -/* Resize CQ Input Mailbox */ - -struct arbelprm_resize_cq_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t start_addr_h[0x00020]; /* Start address of CQ[63:32]. - Must be aligned on CQE size (32 bytes) */ -/* -------------- */ - pseudo_bit_t start_addr_l[0x00020]; /* Start address of CQ[31:0]. - Must be aligned on CQE size (32 bytes) */ -/* -------------- */ - pseudo_bit_t reserved1[0x00018]; - pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */ - pseudo_bit_t reserved2[0x00003]; -/* -------------- */ - pseudo_bit_t reserved3[0x00060]; -/* -------------- */ - pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */ -/* -------------- */ - pseudo_bit_t reserved4[0x00100]; -/* -------------- */ -}; - -/* MAD_IFC Input Modifier */ - -struct arbelprm_mad_ifc_input_modifier_st { /* Little Endian */ - pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */ - pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set. - Required for trap generation when BKey check is enabled and for global routed packets. */ - pseudo_bit_t reserved0[0x00007]; - pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. - This field is required for trap generation upon MKey/BKey validation. */ -/* -------------- */ -}; - -/* MAD_IFC Input Mailbox */ - -struct arbelprm_mad_ifc_st { /* Little Endian */ - pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */ -/* -------------- */ - pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t reserved2[0x00004]; - pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ -/* -------------- */ - pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t reserved3[0x00010]; -/* -------------- */ - pseudo_bit_t reserved4[0x00180]; -/* -------------- */ - pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list. - Valid if Mad_extended_info bit (in the input modifier) and g bit are set. - Otherwise this field is reserved. */ -/* -------------- */ - pseudo_bit_t reserved5[0x004c0]; -/* -------------- */ -}; - -/* Query Debug Message */ - -struct arbelprm_query_debug_msg_st { /* Little Endian */ - pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */ -/* -------------- */ - pseudo_bit_t v[0x00001]; /* Physical translation is valid */ - pseudo_bit_t reserved0[0x0000b]; - pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */ -/* -------------- */ - pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */ -/* -------------- */ - pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */ -/* -------------- */ - pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */ -/* -------------- */ - pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */ -/* -------------- */ - pseudo_bit_t reserved1[0x000c0]; -/* -------------- */ - pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */ -/* -------------- */ - pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */ -/* -------------- */ - pseudo_bit_t reserved2[0x00040]; -/* -------------- */ - pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */ -/* -------------- */ - pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */ -/* -------------- */ - pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */ -/* -------------- */ - pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */ -/* -------------- */ - pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */ -/* -------------- */ - pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */ -/* -------------- */ - pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */ -/* -------------- */ - pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */ -/* -------------- */ - pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */ -/* -------------- */ - pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */ -/* -------------- */ - pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */ -/* -------------- */ - pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */ -/* -------------- */ - pseudo_bit_t buff6_addr[0x00020]; /* Address in firmware area of Trace Buffer 6 */ -/* -------------- */ - pseudo_bit_t buff6_size[0x00020]; /* Size of Trace Buffer 6 */ -/* -------------- */ - pseudo_bit_t buff7_addr[0x00020]; /* Address in firmware area of Trace Buffer 7 */ -/* -------------- */ - pseudo_bit_t buff7_size[0x00020]; /* Size of Trace Buffer 7 */ -/* -------------- */ - pseudo_bit_t reserved3[0x00400]; -/* -------------- */ -}; - -/* User Access Region */ - -struct arbelprm_uar_st { /* Little Endian */ - struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */ -/* -------------- */ - struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */ -/* -------------- */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - struct arbelprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */ -/* -------------- */ - pseudo_bit_t reserved1[0x03ec0]; -/* -------------- */ -}; - -/* Receive doorbell */ - -struct arbelprm_receive_doorbell_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t reserved2[0x00005]; - pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */ - pseudo_bit_t reserved3[0x00002]; - pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */ -/* -------------- */ -}; - -/* SET_IB Parameters */ - -struct arbelprm_set_ib_st { /* Little Endian */ - pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */ - pseudo_bit_t reserved0[0x00011]; - pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. - system_image_guid and sig must be the same for all ports. */ - pseudo_bit_t reserved1[0x0000d]; -/* -------------- */ - pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */ -/* -------------- */ - pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t reserved2[0x00180]; -/* -------------- */ -}; - -/* Multicast Group Member */ - -struct arbelprm_mgm_entry_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00006]; - pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number. - The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables. - next_gid_index=0 means end of the chain. */ -/* -------------- */ - pseudo_bit_t reserved1[0x00060]; -/* -------------- */ - pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format. - Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ -/* -------------- */ - pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format. - Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ -/* -------------- */ - pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format. - Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ -/* -------------- */ - pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format. - Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ -/* -------------- */ - struct arbelprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */ -/* -------------- */ - struct arbelprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */ -/* -------------- */ - struct arbelprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */ -/* -------------- */ - struct arbelprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */ -/* -------------- */ - struct arbelprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */ -/* -------------- */ - struct arbelprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */ -/* -------------- */ - struct arbelprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */ -/* -------------- */ - struct arbelprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */ -/* -------------- */ -}; - -/* INIT_IB Parameters */ - -struct arbelprm_init_ib_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00004]; - pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15. - Legal values are 1,2,4 and 8. */ - pseudo_bit_t port_width_cap[0x00004];/* IB Port Width - 1 - 1x - 3 - 1x, 4x - 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208) - else - Reserved */ - pseudo_bit_t mtu_cap[0x00004]; /* Maximum MTU Supported - 0x0 - Reserved - 0x1 - 256 - 0x2 - 512 - 0x3 - 1024 - 0x4 - 2048 - 0x5 - 0xF Reserved */ - pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */ - pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified. - node_guid and ng must be the same for all ports. */ - pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. - system_image_guid and sig must be the same for all ports. */ - pseudo_bit_t reserved1[0x0000d]; -/* -------------- */ - pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */ - pseudo_bit_t reserved2[0x00010]; -/* -------------- */ - pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port. - Must be the same for both ports. */ - pseudo_bit_t reserved3[0x00010]; -/* -------------- */ - pseudo_bit_t reserved4[0x00020]; -/* -------------- */ - pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */ -/* -------------- */ - pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */ -/* -------------- */ - pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t reserved5[0x006c0]; -/* -------------- */ -}; - -/* Query Device Limitations */ - -struct arbelprm_query_dev_lim_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */ - pseudo_bit_t reserved1[0x00003]; - pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */ - pseudo_bit_t reserved2[0x00004]; - pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */ - pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */ -/* -------------- */ - pseudo_bit_t log_max_ee[0x00005]; /* Log2 of the Maximum number of EE contexts supported */ - pseudo_bit_t reserved3[0x00003]; - pseudo_bit_t log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */ - pseudo_bit_t reserved4[0x00004]; - pseudo_bit_t log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set. - */ - pseudo_bit_t reserved5[0x00007]; - pseudo_bit_t log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use - The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1 - This parameter is valid only if the SRQ bit is set. */ -/* -------------- */ - pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */ - pseudo_bit_t reserved6[0x00003]; - pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */ - pseudo_bit_t reserved7[0x00004]; - pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */ - pseudo_bit_t reserved8[0x00008]; -/* -------------- */ - pseudo_bit_t log_max_eq[0x00003]; /* Log2 of the Maximum number of EQs */ - pseudo_bit_t reserved9[0x00005]; - pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use - The reserved resources are numbered from 0 to num_rsvd_eqs-1 - If 0 - no resources are reserved. */ - pseudo_bit_t reserved10[0x00004]; - pseudo_bit_t log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */ - pseudo_bit_t reserved11[0x00002]; - pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */ -/* -------------- */ - pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */ - pseudo_bit_t reserved12[0x00002]; - pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */ - pseudo_bit_t reserved13[0x00004]; - pseudo_bit_t log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */ - pseudo_bit_t reserved14[0x00004]; - pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1 - */ -/* -------------- */ - pseudo_bit_t reserved15[0x00020]; -/* -------------- */ - pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */ - pseudo_bit_t reserved16[0x0000a]; - pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */ - pseudo_bit_t reserved17[0x0000a]; -/* -------------- */ - pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */ - pseudo_bit_t reserved18[0x00016]; - pseudo_bit_t log2_rsvd_rdbs[0x00004];/* Log (base 2) of the number of RDB entries reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsvd_rdbs-1 */ -/* -------------- */ - pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */ - pseudo_bit_t reserved19[0x0001f]; -/* -------------- */ - pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */ - pseudo_bit_t max_vl[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */ - pseudo_bit_t max_port_width[0x00004];/* IB Port Width - 1 - 1x - 3 - 1x, 4x - 11 - 1x, 4x or 12x - else - Reserved */ - pseudo_bit_t max_mtu[0x00004]; /* Maximum MTU Supported - 0x0 - Reserved - 0x1 - 256 - 0x2 - 512 - 0x3 - 1024 - 0x4 - 2048 - 0x5 - 0xF Reserved */ - pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb. - The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */ - pseudo_bit_t reserved20[0x0000b]; -/* -------------- */ - pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */ - pseudo_bit_t reserved21[0x0001c]; -/* -------------- */ - pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */ - pseudo_bit_t reserved22[0x0000c]; - pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported - bit 0 - full bw - bit 1 - 1/4 bw - bit 2 - 1/8 bw - bit 3 - 1/2 bw; */ -/* -------------- */ - pseudo_bit_t reserved23[0x00020]; -/* -------------- */ - pseudo_bit_t rc[0x00001]; /* RC Transport supported */ - pseudo_bit_t uc[0x00001]; /* UC Transport Supported */ - pseudo_bit_t ud[0x00001]; /* UD Transport Supported */ - pseudo_bit_t rd[0x00001]; /* RD Transport Supported */ - pseudo_bit_t raw_ipv6[0x00001]; /* Raw IPv6 Transport Supported */ - pseudo_bit_t raw_ether[0x00001]; /* Raw Ethertype Transport Supported */ - pseudo_bit_t srq[0x00001]; /* SRQ is supported - */ - pseudo_bit_t ipo_ib_checksum[0x00001];/* IP over IB checksum is supported */ - pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */ - pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */ - pseudo_bit_t reserved24[0x00006]; - pseudo_bit_t mw[0x00001]; /* Memory windows supported */ - pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */ - pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */ - pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */ - pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */ - pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */ - pseudo_bit_t reserved25[0x00002]; - pseudo_bit_t pg[0x00001]; /* Paging on demand supported */ - pseudo_bit_t r[0x00001]; /* Router mode supported */ - pseudo_bit_t reserved26[0x00006]; -/* -------------- */ - pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2). - For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */ - pseudo_bit_t reserved27[0x00008]; - pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */ - pseudo_bit_t reserved28[0x00006]; - pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use - The reserved resources are numbered from 0 to num_reserved_uars-1 - Note that UAR number num_reserved_uars is always for the kernel. */ -/* -------------- */ - pseudo_bit_t reserved29[0x00020]; -/* -------------- */ - pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */ - pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */ - pseudo_bit_t reserved30[0x00008]; -/* -------------- */ - pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */ - pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */ - pseudo_bit_t reserved31[0x00008]; -/* -------------- */ - pseudo_bit_t reserved32[0x00040]; -/* -------------- */ - pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */ - pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT. - The reserved resources are numbered from 0 to num_reserved_mcgs-1 - If 0 - no resources are reserved. */ - pseudo_bit_t reserved33[0x00004]; - pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */ - pseudo_bit_t reserved34[0x00008]; -/* -------------- */ - pseudo_bit_t log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */ - pseudo_bit_t reserved35[0x00006]; - pseudo_bit_t num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use - The reserved resources are numbered from 0 to num_reserved_rdds-1. - If 0 - no resources are reserved. */ - pseudo_bit_t log_max_pd[0x00006]; /* Log2 of the maximum number of PDs */ - pseudo_bit_t reserved36[0x00006]; - pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use - The reserved resources are numbered from 0 to num_reserved_pds-1 - If 0 - no resources are reserved. */ -/* -------------- */ - pseudo_bit_t reserved37[0x000c0]; -/* -------------- */ - pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device - For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ - pseudo_bit_t eec_entry_sz[0x00010]; /* EEC Entry Size for the device - For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ -/* -------------- */ - pseudo_bit_t eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device - For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ - pseudo_bit_t eeec_entry_sz[0x00010];/* Extended EEC entry size for the device - For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ -/* -------------- */ - pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device - For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ - pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device - For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ -/* -------------- */ - pseudo_bit_t uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size - For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ - pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device - For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ -/* -------------- */ - pseudo_bit_t mpt_entry_sz[0x00010]; /* MPT entry size in Bytes for the device. - For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ - pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device. - For the InfiniHost-III-EX MT25208 entry size is 8 bytes */ -/* -------------- */ - pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */ - pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism: - 0 - Type 2A - QP Number Association; or - 1 - Type 2B - QP Number and PD Association. */ - pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */ - pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. (The device does not supports Block List) */ - pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */ - pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */ - pseudo_bit_t reserved38[0x00002]; - pseudo_bit_t log_pbl_sz[0x00006]; /* Log2 of the Maximum Physical Buffer List size in Bytes supported by this HCA when invoking the Allocate L_Key verb. - */ - pseudo_bit_t reserved39[0x00012]; -/* -------------- */ - pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */ -/* -------------- */ - pseudo_bit_t lamr[0x00001]; /* When set the device requires local attached memory in order to operate. - When set, ICM pages, Firmware Area and ICM auxiliary pages must be allocated in the local attached memory. */ - pseudo_bit_t reserved40[0x0001f]; -/* -------------- */ - pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */ -/* -------------- */ - pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */ -/* -------------- */ - pseudo_bit_t reserved41[0x002c0]; -/* -------------- */ -}; - -/* QUERY_ADAPTER Parameters Block */ - -struct arbelprm_query_adapter_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t reserved1[0x00018]; - pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */ -/* -------------- */ - pseudo_bit_t reserved2[0x00060]; -/* -------------- */ - struct arbelprm_vsd_st vsd; -/* -------------- */ -}; - -/* QUERY_FW Parameters Block */ - -struct arbelprm_query_fw_st { /* Little Endian */ - pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */ - pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */ -/* -------------- */ - pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */ - pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */ -/* -------------- */ - pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */ - pseudo_bit_t reserved0[0x0000e]; - pseudo_bit_t wqe_h_mode[0x00001]; /* Hermon mode. If '1', then WQE and AV format is the advanced format */ - pseudo_bit_t zb_wq_cq[0x00001]; /* If '1', then ZB mode of WQ and CQ are enabled (i.e. real Memfree PRM is supported) */ -/* -------------- */ - pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */ - pseudo_bit_t reserved1[0x00017]; - pseudo_bit_t dt[0x00001]; /* Debug Trace Support - 0 - Debug trace is not supported - 1 - Debug trace is supported */ -/* -------------- */ - pseudo_bit_t cmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells */ - pseudo_bit_t reserved2[0x0001f]; -/* -------------- */ - pseudo_bit_t reserved3[0x00060]; -/* -------------- */ - pseudo_bit_t clr_int_base_addr_h[0x00020];/* Bits [63:32] of Clear interrupt register physical address. - Points to 64 bit register. */ -/* -------------- */ - pseudo_bit_t clr_int_base_addr_l[0x00020];/* Bits [31:0] of Clear interrupt register physical address. - Points to 64 bit register. */ -/* -------------- */ - pseudo_bit_t reserved4[0x00040]; -/* -------------- */ - pseudo_bit_t error_buf_start_h[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */ -/* -------------- */ - pseudo_bit_t error_buf_start_l[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */ -/* -------------- */ - pseudo_bit_t error_buf_size[0x00020];/* Size in words */ -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ - pseudo_bit_t eq_arm_base_addr_h[0x00020];/* Bits [63:32] of EQ Arm DBs physical address. - Points to 64 bit register. - Setting bit x in the offset, arms EQ number x. - */ -/* -------------- */ - pseudo_bit_t eq_arm_base_addr_l[0x00020];/* Bits [31:0] of EQ Arm DBs physical address. - Points to 64 bit register. - Setting bit x in the offset, arms EQ number x. */ -/* -------------- */ - pseudo_bit_t eq_set_ci_base_addr_h[0x00020];/* Bits [63:32] of EQ Set CI DBs Table physical address. - Points to a the EQ Set CI DBs Table base address. */ -/* -------------- */ - pseudo_bit_t eq_set_ci_base_addr_l[0x00020];/* Bits [31:0] of EQ Set CI DBs Table physical address. - Points to a the EQ Set CI DBs Table base address. */ -/* -------------- */ - pseudo_bit_t cmd_db_dw1[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ - pseudo_bit_t cmd_db_dw0[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ -/* -------------- */ - pseudo_bit_t cmd_db_dw3[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ - pseudo_bit_t cmd_db_dw2[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ -/* -------------- */ - pseudo_bit_t cmd_db_dw5[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ - pseudo_bit_t cmd_db_dw4[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ -/* -------------- */ - pseudo_bit_t cmd_db_dw7[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ - pseudo_bit_t cmd_db_dw6[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ -/* -------------- */ - pseudo_bit_t cmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */ -/* -------------- */ - pseudo_bit_t cmd_db_addr_base_l[0x00020];/* Low bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */ -/* -------------- */ - pseudo_bit_t reserved6[0x004c0]; -/* -------------- */ -}; - -/* ACCESS_LAM */ - -struct arbelprm_access_lam_st { /* Little Endian */ - struct arbelprm_access_lam_inject_errors_st access_lam_inject_errors; -/* -------------- */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ -}; - -/* ENABLE_LAM Parameters Block */ - -struct arbelprm_enable_lam_st { /* Little Endian */ - pseudo_bit_t lam_start_adr_h[0x00020];/* LAM start address [63:32] */ -/* -------------- */ - pseudo_bit_t lam_start_adr_l[0x00020];/* LAM start address [31:0] */ -/* -------------- */ - pseudo_bit_t lam_end_adr_h[0x00020];/* LAM end address [63:32] */ -/* -------------- */ - pseudo_bit_t lam_end_adr_l[0x00020];/* LAM end address [31:0] */ -/* -------------- */ - pseudo_bit_t di[0x00002]; /* Data Integrity Configuration: - 00 - none - 01 - Parity - 10 - ECC Detection Only - 11 - ECC With Correction */ - pseudo_bit_t ap[0x00002]; /* Auto Precharge Mode - 00 - No auto precharge - 01 - Auto precharge per transaction - 10 - Auto precharge per 64 bytes - 11 - reserved */ - pseudo_bit_t dh[0x00001]; /* When set, LAM is Hidden and can not be accessed directly from the PCI bus. */ - pseudo_bit_t reserved0[0x0001b]; -/* -------------- */ - pseudo_bit_t reserved1[0x00160]; -/* -------------- */ - struct arbelprm_dimminfo_st dimm0; /* Logical DIMM 0 Parameters */ -/* -------------- */ - struct arbelprm_dimminfo_st dimm1; /* Logical DIMM 1 Parameters */ -/* -------------- */ - pseudo_bit_t reserved2[0x00400]; -/* -------------- */ -}; - -/* Memory Access Parameters for UD Address Vector Table */ - -struct arbelprm_udavtable_memory_parameters_st { /* Little Endian */ - pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */ -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */ - pseudo_bit_t reserved0[0x00005]; - pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */ - pseudo_bit_t reserved1[0x00002]; -/* -------------- */ -}; - -/* INIT_HCA & QUERY_HCA Parameters Block */ - -struct arbelprm_init_hca_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00060]; -/* -------------- */ - pseudo_bit_t reserved1[0x00010]; - pseudo_bit_t time_stamp_granularity[0x00008];/* This field controls the granularity in which CQE Timestamp counter is incremented. - The TimeStampGranularity units is 1/4 of a microseconds. (e.g is TimeStampGranularity is configured to 0x2, CQE Timestamp will be incremented every one microsecond) - When sets to Zero, timestamp reporting in the CQE is disabled. - This feature is currently not supported. - */ - pseudo_bit_t hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */ -/* -------------- */ - pseudo_bit_t reserved2[0x00008]; - pseudo_bit_t router_qp[0x00010]; /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet. - Valid only if RE bit is set */ - pseudo_bit_t reserved3[0x00007]; - pseudo_bit_t re[0x00001]; /* Router Mode Enable - If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */ -/* -------------- */ - pseudo_bit_t udp[0x00001]; /* UD Port Check Enable - 0 - Port field in Address Vector is ignored - 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */ - pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations - 0 - Host is Little Endian - 1 - Host is Big endian - */ - pseudo_bit_t reserved4[0x00001]; - pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */ - pseudo_bit_t sph[0x00001]; /* 0 - SW calculates TCP/UDP Pseudo-Header checksum and inserts it into the TCP/UDP checksum field when sending a packet - 1 - HW calculates TCP/UDP Pseudo-Header checksum when sending a packet - */ - pseudo_bit_t rph[0x00001]; /* 0 - Not HW calculation of TCP/UDP Pseudo-Header checksum are done when receiving a packet - 1 - HW calculates TCP/UDP Pseudo-Header checksum when receiving a packet - */ - pseudo_bit_t reserved5[0x00002]; - pseudo_bit_t responder_exu[0x00004];/* Indicate the relation between the execution enegines allocation dedicated for responder versus the engines dedicated for reqvester . - responder_exu/16 = (number of responder exu engines)/(total number of engines) - Legal values are 0x0-0xF. 0 is "auto". - - */ - pseudo_bit_t reserved6[0x00004]; - pseudo_bit_t wqe_quota[0x0000f]; /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */ - pseudo_bit_t wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */ -/* -------------- */ - pseudo_bit_t reserved7[0x00040]; -/* -------------- */ - struct arbelprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters; -/* -------------- */ - pseudo_bit_t reserved8[0x00100]; -/* -------------- */ - struct arbelprm_multicastparam_st multicast_parameters; -/* -------------- */ - pseudo_bit_t reserved9[0x00080]; -/* -------------- */ - struct arbelprm_tptparams_st tpt_parameters; -/* -------------- */ - pseudo_bit_t reserved10[0x00080]; -/* -------------- */ - struct arbelprm_uar_params_st uar_parameters;/* UAR Parameters */ -/* -------------- */ - pseudo_bit_t reserved11[0x00600]; -/* -------------- */ -}; - -/* Event Queue Context Table Entry */ - -struct arbelprm_eqc_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t st[0x00004]; /* Event delivery state machine - 0x9 - Armed - 0xA - Fired - 0xB - Always_Armed (auto-rearm) - other - reserved */ - pseudo_bit_t reserved1[0x00005]; - pseudo_bit_t oi[0x00001]; /* Oerrun ignore. - If set, HW will not check EQ full condition when writing new EQEs. */ - pseudo_bit_t tr[0x00001]; /* Translation Required. If set - EQ access undergo address translation. */ - pseudo_bit_t reserved2[0x00005]; - pseudo_bit_t owner[0x00004]; /* 0 - SW ownership - 1 - HW ownership - Valid for the QUERY_EQ and HW2SW_EQ commands only */ - pseudo_bit_t status[0x00004]; /* EQ status: - 0000 - OK - 1010 - EQ write failure - Valid for the QUERY_EQ and HW2SW_EQ commands only */ -/* -------------- */ - pseudo_bit_t start_address_h[0x00020];/* Start Address of Event Queue[63:32]. */ -/* -------------- */ - pseudo_bit_t start_address_l[0x00020];/* Start Address of Event Queue[31:0]. - Must be aligned on 32-byte boundary */ -/* -------------- */ - pseudo_bit_t reserved3[0x00018]; - pseudo_bit_t log_eq_size[0x00005]; /* Amount of entries in this EQ is 2^log_eq_size. - Log_eq_size must be bigger than 1. - Maximum EQ size is 2^17 EQEs (max Log_eq_size is 17). */ - pseudo_bit_t reserved4[0x00003]; -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ - pseudo_bit_t intr[0x00008]; /* Interrupt (message) to be generated to report event to INT layer. - 00iiiiii - set to INTA given in QUERY_ADAPTER in order to generate INTA messages on Express. - 10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported). - All other values are reserved and should not be used. - - If interrupt generation is not required, ST field must be set upon creation to Fired state. No EQ arming doorbell should be performed. In this case hardware will not generate any interrupt. */ - pseudo_bit_t reserved6[0x00018]; -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* PD to be used to access EQ */ - pseudo_bit_t reserved7[0x00008]; -/* -------------- */ - pseudo_bit_t lkey[0x00020]; /* Memory key (L-Key) to be used to access EQ */ -/* -------------- */ - pseudo_bit_t reserved8[0x00040]; -/* -------------- */ - pseudo_bit_t consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue. - Must be initalized to zero while opening EQ */ -/* -------------- */ - pseudo_bit_t producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA. - Must be initalized to zero while opening EQ. */ -/* -------------- */ - pseudo_bit_t reserved9[0x00080]; -/* -------------- */ -}; - -/* Memory Translation Table (MTT) Entry */ - -struct arbelprm_mtt_st { /* Little Endian */ - pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ -/* -------------- */ - pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */ - pseudo_bit_t reserved0[0x0000b]; - pseudo_bit_t ptag_l[0x00014]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ -/* -------------- */ -}; - -/* Memory Protection Table (MPT) Entry */ - -struct arbelprm_mpt_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */ - pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */ - pseudo_bit_t lr[0x00001]; /* If set - local read access enabled */ - pseudo_bit_t lw[0x00001]; /* If set - local write access enabled */ - pseudo_bit_t rr[0x00001]; /* If set - remote read access enabled. */ - pseudo_bit_t rw[0x00001]; /* If set - remote write access enabled */ - pseudo_bit_t a[0x00001]; /* If set - remote Atomic access is enabled */ - pseudo_bit_t eb[0x00001]; /* If set - Bind is enabled. Valid for region entry only. */ - pseudo_bit_t reserved1[0x0000c]; - pseudo_bit_t status[0x00004]; /* Region/Window Status - 0xF - not valid (SW ownership) - 0x3 - FREE state - else - HW ownership - Unbound Type I windows are doneted reg_wnd_len field equals zero. - Unbound Type II windows are donated by Status=FREE. */ -/* -------------- */ - pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. - page_size should be less than 20. */ - pseudo_bit_t reserved2[0x00002]; - pseudo_bit_t type[0x00001]; /* Applicable for windows only, must be zero for regions - 0 - Type one window - 1 - Type two window */ - pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */ -/* -------------- */ - pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. - */ -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* Protection Domain */ - pseudo_bit_t reserved3[0x00001]; - pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. - Must be set for type2 windows and non-shared physical memory regions. - Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */ - pseudo_bit_t zb[0x00001]; /* When set, this region is Zero Based Region */ - pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */ - pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. - Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. - If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail. - */ - pseudo_bit_t reserved4[0x00003]; -/* -------------- */ - pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */ -/* -------------- */ - pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */ -/* -------------- */ - pseudo_bit_t reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */ -/* -------------- */ - pseudo_bit_t reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */ -/* -------------- */ - pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. - On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to. - The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */ -/* -------------- */ - pseudo_bit_t win_cnt[0x00020]; /* Number of windows bound to this region. Valid for regions only. - The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */ -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ - pseudo_bit_t mtt_adr_h[0x00006]; /* Base (first) address of the MTT relative to MTT base in the ICM */ - pseudo_bit_t reserved6[0x0001a]; -/* -------------- */ - pseudo_bit_t reserved7[0x00003]; - pseudo_bit_t mtt_adr_l[0x0001d]; /* Base (first) address of the MTT relative to MTT base address in the ICM. Must be aligned on 8 bytes. */ -/* -------------- */ - pseudo_bit_t mtt_sz[0x00020]; /* Number of MTT entries allocated for this MR. - When Fast Registration Operations can not be executed on this region (FRE bit is zero) this field is reserved. - When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value is zero, there is no limit for the numbers of MTTs and the HCA does not check this field when executing fast register WQE. */ -/* -------------- */ - pseudo_bit_t reserved8[0x00040]; -/* -------------- */ -}; - -/* Completion Queue Context Table Entry */ - -struct arbelprm_completion_queue_context_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t st[0x00004]; /* Event delivery state machine - 0x0 - reserved - 0x9 - ARMED (Request for Notification) - 0x6 - ARMED SOLICITED (Request Solicited Notification) - 0xA - FIRED - other - reserved - - Must be 0x0 in CQ initialization. - Valid for the QUERY_CQ and HW2SW_CQ commands only. */ - pseudo_bit_t reserved1[0x00005]; - pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled. - When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */ - pseudo_bit_t reserved2[0x0000a]; - pseudo_bit_t status[0x00004]; /* CQ status - 0000 - OK - 1001 - CQ overflow - 1010 - CQ write failure - Valid for the QUERY_CQ and HW2SW_CQ commands only */ -/* -------------- */ - pseudo_bit_t start_address_h[0x00020];/* Start address of CQ[63:32]. - Must be aligned on CQE size (32 bytes) */ -/* -------------- */ - pseudo_bit_t start_address_l[0x00020];/* Start address of CQ[31:0]. - Must be aligned on CQE size (32 bytes) */ -/* -------------- */ - pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */ - pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries). - Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */ - pseudo_bit_t reserved3[0x00003]; -/* -------------- */ - pseudo_bit_t reserved4[0x00020]; -/* -------------- */ - pseudo_bit_t c_eqn[0x00008]; /* Event Queue this CQ reports completion events to. - Valid values are 0 to 63 - If configured to value other than 0-63, completion events will not be reported on the CQ. */ - pseudo_bit_t reserved5[0x00018]; -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* Protection Domain to be used to access CQ. - Must be the same PD of the CQ L_Key. */ - pseudo_bit_t reserved6[0x00008]; -/* -------------- */ - pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */ -/* -------------- */ - pseudo_bit_t last_notified_indx[0x00020];/* Maintained by HW. - Valid for QUERY_CQ and HW2SW_CQ commands only. */ -/* -------------- */ - pseudo_bit_t solicit_producer_indx[0x00020];/* Maintained by HW. - Valid for QUERY_CQ and HW2SW_CQ commands only. - */ -/* -------------- */ - pseudo_bit_t consumer_counter[0x00020];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ. - Must be 0x0 in CQ initialization. - Valid for the QUERY_CQ and HW2SW_CQ commands only. */ -/* -------------- */ - pseudo_bit_t producer_counter[0x00020];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ. - CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added.. - Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */ -/* -------------- */ - pseudo_bit_t cqn[0x00018]; /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table - Valid for the QUERY_CQ and HW2SW_CQ commands only */ - pseudo_bit_t reserved7[0x00008]; -/* -------------- */ - pseudo_bit_t cq_ci_db_record[0x00020];/* Index in the UAR Context Table Entry. - HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ Consumer Counter doorbell record. - This value can be retrieved from the HW in the QUERY_CQ command. */ -/* -------------- */ - pseudo_bit_t cq_state_db_record[0x00020];/* Index in the UAR Context Table Entry. - HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ state doorbell record. - This value can be retrieved from the HW in the QUERY_CQ command. */ -/* -------------- */ - pseudo_bit_t reserved8[0x00020]; -/* -------------- */ -}; - -/* GPIO_event_data */ - -struct arbelprm_gpio_event_data_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00060]; -/* -------------- */ - pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ -/* -------------- */ - pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ -}; - -/* Event_data Field - QP/EE Events */ - -struct arbelprm_qp_ee_event_st { /* Little Endian */ - pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t reserved2[0x0001c]; - pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field - Not valid on SRQ events */ - pseudo_bit_t reserved3[0x00003]; -/* -------------- */ - pseudo_bit_t reserved4[0x00060]; -/* -------------- */ -}; - -/* InfiniHost-III-EX Type0 Configuration Header */ - -struct arbelprm_mt25208_type0_st { /* Little Endian */ - pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */ - pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode - 25218 (decimal) - InfiniHost-III EX mode (the mode described in this manual) - 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode - */ -/* -------------- */ - pseudo_bit_t command[0x00010]; /* PCI Command Register */ - pseudo_bit_t status[0x00010]; /* PCI Status Register */ -/* -------------- */ - pseudo_bit_t revision_id[0x00008]; - pseudo_bit_t class_code_hca_class_code[0x00018]; -/* -------------- */ - pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */ - pseudo_bit_t latency_timer[0x00008]; - pseudo_bit_t header_type[0x00008]; /* hardwired to zero */ - pseudo_bit_t bist[0x00008]; -/* -------------- */ - pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */ - pseudo_bit_t reserved0[0x00010]; - pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */ -/* -------------- */ - pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */ -/* -------------- */ - pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */ - pseudo_bit_t reserved1[0x00010]; - pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */ -/* -------------- */ - pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */ -/* -------------- */ - pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */ - pseudo_bit_t reserved2[0x00010]; - pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ -/* -------------- */ - pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ -/* -------------- */ - pseudo_bit_t cardbus_cis_pointer[0x00020]; -/* -------------- */ - pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */ - pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */ -/* -------------- */ - pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ - pseudo_bit_t reserved3[0x0000a]; - pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ -/* -------------- */ - pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */ - pseudo_bit_t reserved4[0x00018]; -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ - pseudo_bit_t interrupt_line[0x00008]; - pseudo_bit_t interrupt_pin[0x00008]; - pseudo_bit_t min_gnt[0x00008]; - pseudo_bit_t max_latency[0x00008]; -/* -------------- */ - pseudo_bit_t reserved6[0x00100]; -/* -------------- */ - pseudo_bit_t msi_cap_id[0x00008]; - pseudo_bit_t msi_next_cap_ptr[0x00008]; - pseudo_bit_t msi_en[0x00001]; - pseudo_bit_t multiple_msg_cap[0x00003]; - pseudo_bit_t multiple_msg_en[0x00003]; - pseudo_bit_t cap_64_bit_addr[0x00001]; - pseudo_bit_t reserved7[0x00008]; -/* -------------- */ - pseudo_bit_t msg_addr_l[0x00020]; -/* -------------- */ - pseudo_bit_t msg_addr_h[0x00020]; -/* -------------- */ - pseudo_bit_t msg_data[0x00010]; - pseudo_bit_t reserved8[0x00010]; -/* -------------- */ - pseudo_bit_t reserved9[0x00080]; -/* -------------- */ - pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */ - pseudo_bit_t pm_next_cap_ptr[0x00008]; - pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h - [3] PME clock - 0h - [4] RsvP - [5] Device specific initialization - 0h - [8:6] AUX current - 0h - [9] D1 support - 0h - [10] D2 support - 0h - [15:11] PME support - 0h */ -/* -------------- */ - pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */ - pseudo_bit_t pm_control_status_brdg_ext[0x00008]; - pseudo_bit_t data[0x00008]; -/* -------------- */ - pseudo_bit_t reserved10[0x00040]; -/* -------------- */ - pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */ - pseudo_bit_t vpd_next_cap_id[0x00008]; - pseudo_bit_t vpd_address[0x0000f]; - pseudo_bit_t f[0x00001]; -/* -------------- */ - pseudo_bit_t vpd_data[0x00020]; -/* -------------- */ - pseudo_bit_t reserved11[0x00040]; -/* -------------- */ - pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */ - pseudo_bit_t pciex_next_cap_ptr[0x00008]; - pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h - [7:4] Device/Port Type - 0h - [8] Slot implemented - 0h - [13:9] Interrupt message number - */ -/* -------------- */ - pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h - [4:3] Phantom Function supported - 0h - [5] Extended Tag Filed supported - 0h - [8:6] Endpoint L0s Acceptable Latency - TBD - [11:9] Endpoint L1 Acceptable Latency - TBD - [12] Attention Button Present - configured through InfiniBurn - [13] Attention Indicator Present - configured through InfiniBurn - [14] Power Indicator Present - configured through InfiniBurn - [25:18] Captured Slot Power Limit Value - [27:26] Captured Slot Power Limit Scale */ -/* -------------- */ - pseudo_bit_t device_control[0x00010]; - pseudo_bit_t device_status[0x00010]; -/* -------------- */ - pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h - [9:4] Maximum Link Width - 8h - [11:10] Active State Power Management Support - 3h - [14:12] L0s Exit Latency - TBD - [17:15] L1 Exit Latency - TBD - [31:24] Port Number - 0h */ -/* -------------- */ - pseudo_bit_t link_control[0x00010]; - pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h - [9:4] Negotiated Link Width - [12] Slot clock configuration - 1h */ -/* -------------- */ - pseudo_bit_t reserved12[0x00260]; -/* -------------- */ - pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */ - pseudo_bit_t capability_version[0x00004];/* 1h */ - pseudo_bit_t next_capability_offset[0x0000c];/* 0h */ -/* -------------- */ - pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status - 4 Data Link Protocol Error Status - 12 Poisoned TLP Status - 13 Flow Control Protocol Error Status - 14 Completion Timeout Status - 15 Completer Abort Status - 16 Unexpected Completion Status - 17 Receiver Overflow Status - 18 Malformed TLP Status - 19 ECRC Error Status - 20 Unsupported Request Error Status */ -/* -------------- */ - pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask - 4 Data Link Protocol Error Mask - 12 Poisoned TLP Mask - 13 Flow Control Protocol Error Mask - 14 Completion Timeout Mask - 15 Completer Abort Mask - 16 Unexpected Completion Mask - 17 Receiver Overflow Mask - 18 Malformed TLP Mask - 19 ECRC Error Mask - 20 Unsupported Request Error Mask */ -/* -------------- */ - pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity - 4 Data Link Protocol Error Severity - 12 Poisoned TLP Severity - 13 Flow Control Protocol Error Severity - 14 Completion Timeout Severity - 15 Completer Abort Severity - 16 Unexpected Completion Severity - 17 Receiver Overflow Severity - 18 Malformed TLP Severity - 19 ECRC Error Severity - 20 Unsupported Request Error Severity */ -/* -------------- */ - pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status - 6 Bad TLP Status - 7 Bad DLLP Status - 8 REPLAY_NUM Rollover Status - 12 Replay Timer Timeout Status */ -/* -------------- */ - pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask - 6 Bad TLP Mask - 7 Bad DLLP Mask - 8 REPLAY_NUM Rollover Mask - 12 Replay Timer Timeout Mask */ -/* -------------- */ - pseudo_bit_t advance_error_capabilities_and_control_register[0x00020]; -/* -------------- */ - struct arbelprm_header_log_register_st header_log_register; -/* -------------- */ - pseudo_bit_t reserved13[0x006a0]; -/* -------------- */ -}; - -/* Event Data Field - Performance Monitor */ - -struct arbelprm_performance_monitor_event_st { /* Little Endian */ - struct arbelprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */ -/* -------------- */ - pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC - 0x02 - RQPC - 0x03 - CQC - 0x04 - Rkey - 0x05 - TLB - 0x06 - port0 - 0x07 - port1 */ - pseudo_bit_t reserved0[0x00018]; -/* -------------- */ - pseudo_bit_t reserved1[0x00040]; -/* -------------- */ -}; - -/* Event_data Field - Page Faults */ - -struct arbelprm_page_fault_event_data_st { /* Little Endian */ - pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ -/* -------------- */ - pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ -/* -------------- */ - pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */ -/* -------------- */ - pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */ - pseudo_bit_t reserved0[0x00003]; - pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */ - pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */ - pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */ - pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */ - pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */ -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */ -/* -------------- */ -}; - -/* WQE segments format */ - -struct arbelprm_wqe_segment_st { /* Little Endian */ - struct arbelprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */ -/* -------------- */ - pseudo_bit_t reserved0[0x00280]; -/* -------------- */ - struct arbelprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */ -/* -------------- */ - pseudo_bit_t reserved1[0x00100]; -/* -------------- */ - struct arbelprm_wqe_segment_ctrl_recv_st recv_wqe_segment_ctrl;/* Receive segment format */ -/* -------------- */ - pseudo_bit_t reserved2[0x00080]; -/* -------------- */ -}; - -/* Event_data Field - Port State Change */ - -struct arbelprm_port_state_change_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - pseudo_bit_t reserved1[0x0001c]; - pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */ - pseudo_bit_t reserved2[0x00002]; -/* -------------- */ - pseudo_bit_t reserved3[0x00060]; -/* -------------- */ -}; - -/* Event_data Field - Completion Queue Error */ - -struct arbelprm_completion_queue_error_st { /* Little Endian */ - pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t syndrome[0x00008]; /* Error syndrome - 0x01 - CQ overrun - 0x02 - CQ access violation error */ - pseudo_bit_t reserved2[0x00018]; -/* -------------- */ - pseudo_bit_t reserved3[0x00060]; -/* -------------- */ -}; - -/* Event_data Field - Completion Event */ - -struct arbelprm_completion_event_st { /* Little Endian */ - pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x000a0]; -/* -------------- */ -}; - -/* Event Queue Entry */ - -struct arbelprm_event_queue_entry_st { /* Little Endian */ - pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type. - Defined for events which have sub types, zero elsewhere. */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t event_type[0x00008]; /* Event Type */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */ -/* -------------- */ - pseudo_bit_t reserved2[0x00007]; - pseudo_bit_t owner[0x00001]; /* Owner of the entry - 0 SW - 1 HW */ - pseudo_bit_t reserved3[0x00018]; -/* -------------- */ -}; - -/* QP/EE State Transitions Command Parameters */ - -struct arbelprm_qp_ee_state_transitions_st { /* Little Endian */ - pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */ -/* -------------- */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - struct arbelprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data */ -/* -------------- */ - pseudo_bit_t reserved1[0x009c0]; -/* -------------- */ -}; - -/* Completion Queue Entry Format */ - -struct arbelprm_completion_queue_entry_st { /* Little Endian */ - pseudo_bit_t my_qpn[0x00018]; /* Indicates the QP for which completion is being reported */ - pseudo_bit_t reserved0[0x00004]; - pseudo_bit_t ver[0x00004]; /* CQE version. - 0 for InfiniHost-III-EX */ -/* -------------- */ - pseudo_bit_t my_ee[0x00018]; /* EE context (for RD only). - Invalid for Bind and Nop operation on RD. - For non RD services this filed reports the CQE timestamp. The Timestamp is a free running counter that is incremented every TimeStampGranularity tick. The counter rolls-over when it reaches saturation. TimeStampGranularity is configured in the INIT_HCA command. This feature is currently not supported. - */ - pseudo_bit_t checksum_15_8[0x00008];/* Checksum[15:8] - See IPoverIB checksum offloading chapter */ -/* -------------- */ - pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */ - pseudo_bit_t checksum_7_0[0x00008]; /* Checksum[7:0] - See IPoverIB checksum offloading chapter */ -/* -------------- */ - pseudo_bit_t rlid[0x00010]; /* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */ - pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. - Valid in responder of UD QP CQE only. - Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */ - pseudo_bit_t g[0x00001]; /* GRH present indicator. Valid in Responder of UD QP CQE only. */ - pseudo_bit_t ipok[0x00001]; /* IP OK - See IPoverIB checksum offloading chapter */ - pseudo_bit_t reserved1[0x00003]; - pseudo_bit_t sl[0x00004]; /* Service Level of the message. Valid in Responder of UD QP CQE only. */ -/* -------------- */ - pseudo_bit_t immediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only. - If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet. - If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet. - If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived. - If Opcode field indicates that this was send and invalidate, this field contains the key that was invalidated. - For CQE of send queue of the reliable connection service (but send and invalide), bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message. */ -/* -------------- */ - pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data actually transferred (valid for receive queue completions only) */ -/* -------------- */ - pseudo_bit_t reserved2[0x00006]; - pseudo_bit_t wqe_adr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */ -/* -------------- */ - pseudo_bit_t reserved3[0x00007]; - pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */ - pseudo_bit_t reserved4[0x0000f]; - pseudo_bit_t s[0x00001]; /* If set, completion is reported for Send queue, if cleared - receive queue. */ - pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for. - For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field. - For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field. - For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only) - - The following values are reported in case of completion with error: - 0xFE - For completion with error on Receive Queues - 0xFF - For completion with error on Send Queues */ -/* -------------- */ -}; - -/* */ - -struct arbelprm_ecc_detect_event_data_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t cause_lsb[0x00001]; - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t cause_msb[0x00001]; - pseudo_bit_t reserved2[0x00002]; - pseudo_bit_t err_rmw[0x00001]; - pseudo_bit_t err_src_id[0x00003]; - pseudo_bit_t err_da[0x00002]; - pseudo_bit_t err_ba[0x00002]; - pseudo_bit_t reserved3[0x00011]; - pseudo_bit_t overflow[0x00001]; -/* -------------- */ - pseudo_bit_t err_ra[0x00010]; - pseudo_bit_t err_ca[0x00010]; -/* -------------- */ -}; - -/* Event_data Field - ECC Detection Event */ - -struct arbelprm_scrubbing_event_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause: - single ECC error in the 64bit lsb data, on the rise edge of the clock */ - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause: - single ECC error in the 64bit msb data, on the fall edge of the clock */ - pseudo_bit_t reserved2[0x00002]; - pseudo_bit_t err_rmw[0x00001]; /* transaction type: - 0 - read - 1 - read/modify/write */ - pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */ - pseudo_bit_t err_da[0x00002]; /* Error DIMM address */ - pseudo_bit_t err_ba[0x00002]; /* Error bank address */ - pseudo_bit_t reserved3[0x00011]; - pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */ -/* -------------- */ - pseudo_bit_t err_ra[0x00010]; /* Error row address */ - pseudo_bit_t err_ca[0x00010]; /* Error column address */ -/* -------------- */ -}; - -/* Miscellaneous Counters */ - -struct arbelprm_misc_counters_st { /* Little Endian */ - pseudo_bit_t ddr_scan_cnt[0x00020]; /* Number of times whole of LAM was scanned */ -/* -------------- */ - pseudo_bit_t reserved0[0x007e0]; -/* -------------- */ -}; - -/* LAM_EN Output Parameter */ - -struct arbelprm_lam_en_out_param_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ -}; - -/* Extended_Completion_Queue_Entry */ - -struct arbelprm_extended_completion_queue_entry_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ -}; - -/* */ - -struct arbelprm_eq_cmd_doorbell_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ -}; - -/* 0 */ - -struct arbelprm_arbel_prm_st { /* Little Endian */ - struct arbelprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */ -/* -------------- */ - pseudo_bit_t reserved0[0x7ff00]; -/* -------------- */ - struct arbelprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */ -/* -------------- */ - pseudo_bit_t reserved1[0x7f000]; -/* -------------- */ - struct arbelprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */ -/* -------------- */ - pseudo_bit_t reserved2[0x7ff00]; -/* -------------- */ - struct arbelprm_completion_event_st completion_event;/* Event_data Field - Completion Event */ -/* -------------- */ - pseudo_bit_t reserved3[0x7ff40]; -/* -------------- */ - struct arbelprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */ -/* -------------- */ - pseudo_bit_t reserved4[0x7ff40]; -/* -------------- */ - struct arbelprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */ -/* -------------- */ - pseudo_bit_t reserved5[0x7ff40]; -/* -------------- */ - struct arbelprm_wqe_segment_st wqe_segment;/* WQE segments format */ -/* -------------- */ - pseudo_bit_t reserved6[0x7f000]; -/* -------------- */ - struct arbelprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */ -/* -------------- */ - pseudo_bit_t reserved7[0x7ff40]; -/* -------------- */ - struct arbelprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */ -/* -------------- */ - pseudo_bit_t reserved8[0xfff20]; -/* -------------- */ - struct arbelprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */ -/* -------------- */ - pseudo_bit_t reserved9[0x7f000]; -/* -------------- */ - struct arbelprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */ -/* -------------- */ - pseudo_bit_t reserved10[0x00040]; -/* -------------- */ - struct arbelprm_gpio_event_data_st gpio_event_data; -/* -------------- */ - pseudo_bit_t reserved11[0x7fe40]; -/* -------------- */ - struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ -/* -------------- */ - pseudo_bit_t reserved12[0x7ff00]; -/* -------------- */ - struct arbelprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */ -/* -------------- */ - pseudo_bit_t reserved13[0x7fa00]; -/* -------------- */ - struct arbelprm_address_path_st address_path;/* Address Path */ -/* -------------- */ - pseudo_bit_t reserved14[0x7ff00]; -/* -------------- */ - struct arbelprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */ -/* -------------- */ - pseudo_bit_t reserved15[0x7fe00]; -/* -------------- */ - struct arbelprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */ -/* -------------- */ - pseudo_bit_t reserved16[0x7fe00]; -/* -------------- */ - struct arbelprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */ -/* -------------- */ - pseudo_bit_t reserved17[0x7ffc0]; -/* -------------- */ - struct arbelprm_eqc_st eqc; /* Event Queue Context Table Entry */ -/* -------------- */ - pseudo_bit_t reserved18[0x7fe00]; -/* -------------- */ - struct arbelprm_performance_monitors_st performance_monitors;/* Performance Monitors */ -/* -------------- */ - pseudo_bit_t reserved19[0x7ff80]; -/* -------------- */ - struct arbelprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */ -/* -------------- */ - pseudo_bit_t reserved20[0xfff20]; -/* -------------- */ - struct arbelprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */ -/* -------------- */ - pseudo_bit_t reserved21[0x7f000]; -/* -------------- */ - struct arbelprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */ -/* -------------- */ - pseudo_bit_t reserved22[0x7fc00]; -/* -------------- */ - struct arbelprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */ -/* -------------- */ - pseudo_bit_t reserved23[0x7ffc0]; -/* -------------- */ - struct arbelprm_multicastparam_st multicastparam;/* Multicast Support Parameters */ -/* -------------- */ - pseudo_bit_t reserved24[0x7ff00]; -/* -------------- */ - struct arbelprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */ -/* -------------- */ - pseudo_bit_t reserved25[0x7ff00]; -/* -------------- */ - struct arbelprm_enable_lam_st enable_lam;/* ENABLE_LAM Parameters Block */ -/* -------------- */ - struct arbelprm_access_lam_st access_lam; -/* -------------- */ - pseudo_bit_t reserved26[0x7f700]; -/* -------------- */ - struct arbelprm_dimminfo_st dimminfo;/* Logical DIMM Information */ -/* -------------- */ - pseudo_bit_t reserved27[0x7ff00]; -/* -------------- */ - struct arbelprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */ -/* -------------- */ - pseudo_bit_t reserved28[0x7f800]; -/* -------------- */ - struct arbelprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */ -/* -------------- */ - pseudo_bit_t reserved29[0x7f800]; -/* -------------- */ - struct arbelprm_query_dev_lim_st query_dev_lim;/* Query Device Limitations */ -/* -------------- */ - pseudo_bit_t reserved30[0x7f800]; -/* -------------- */ - struct arbelprm_uar_params_st uar_params;/* UAR Parameters */ -/* -------------- */ - pseudo_bit_t reserved31[0x7ff00]; -/* -------------- */ - struct arbelprm_init_ib_st init_ib; /* INIT_IB Parameters */ -/* -------------- */ - pseudo_bit_t reserved32[0x7f800]; -/* -------------- */ - struct arbelprm_mgm_entry_st mgm_entry;/* Multicast Group Member */ -/* -------------- */ - pseudo_bit_t reserved33[0x7fe00]; -/* -------------- */ - struct arbelprm_set_ib_st set_ib; /* SET_IB Parameters */ -/* -------------- */ - pseudo_bit_t reserved34[0x7fe00]; -/* -------------- */ - struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */ -/* -------------- */ - pseudo_bit_t reserved35[0x7ff80]; -/* -------------- */ - struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */ -/* -------------- */ - pseudo_bit_t reserved36[0x7ffc0]; -/* -------------- */ - struct arbelprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */ -/* -------------- */ - pseudo_bit_t reserved37[0x7ffc0]; -/* -------------- */ - struct arbelprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */ -/* -------------- */ - pseudo_bit_t reserved38[0xfffc0]; -/* -------------- */ - struct arbelprm_uar_st uar; /* User Access Region */ -/* -------------- */ - pseudo_bit_t reserved39[0x7c000]; -/* -------------- */ - struct arbelprm_mgmqp_st mgmqp; /* Multicast Group Member QP */ -/* -------------- */ - pseudo_bit_t reserved40[0x7ffe0]; -/* -------------- */ - struct arbelprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */ -/* -------------- */ - pseudo_bit_t reserved41[0x7f800]; -/* -------------- */ - struct arbelprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */ -/* -------------- */ - pseudo_bit_t reserved42[0x00900]; -/* -------------- */ - struct arbelprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */ -/* -------------- */ - pseudo_bit_t reserved43[0x7e6e0]; -/* -------------- */ - struct arbelprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */ -/* -------------- */ - pseudo_bit_t reserved44[0x7fe00]; -/* -------------- */ - struct arbelprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */ -/* -------------- */ - pseudo_bit_t reserved45[0x7ff00]; -/* -------------- */ - struct arbelprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */ -/* -------------- */ - pseudo_bit_t reserved46[0x7ff40]; -/* -------------- */ - struct arbelprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */ -/* -------------- */ - pseudo_bit_t reserved47[0x7f000]; -/* -------------- */ - struct arbelprm_performance_counters_st performance_counters;/* Performance Counters */ -/* -------------- */ - pseudo_bit_t reserved48[0x9ff800]; -/* -------------- */ - struct arbelprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ -/* -------------- */ - pseudo_bit_t reserved49[0x7ff00]; -/* -------------- */ - struct arbelprm_pbl_st pbl; /* Physical Buffer List */ -/* -------------- */ - pseudo_bit_t reserved50[0x7ff00]; -/* -------------- */ - struct arbelprm_srq_context_st srq_context;/* SRQ Context */ -/* -------------- */ - pseudo_bit_t reserved51[0x7fe80]; -/* -------------- */ - struct arbelprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */ -/* -------------- */ - pseudo_bit_t reserved52[0x7f800]; -/* -------------- */ - struct arbelprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */ -/* -------------- */ - pseudo_bit_t reserved53[0x7ff80]; -/* -------------- */ - struct arbelprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */ -/* -------------- */ - pseudo_bit_t reserved54[0x7ffc0]; -/* -------------- */ - struct arbelprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */ -/* -------------- */ - pseudo_bit_t reserved55[0x7ffc0]; -/* -------------- */ - struct arbelprm_qp_db_record_st qp_db_record;/* QP_DB_Record */ -/* -------------- */ - pseudo_bit_t reserved56[0x1fffc0]; -/* -------------- */ - struct arbelprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */ -/* -------------- */ - struct arbelprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */ -/* -------------- */ - pseudo_bit_t reserved57[0x01000]; -/* -------------- */ - struct arbelprm_eq_arm_db_region_st eq_arm_db_region;/* EQ Arm Doorbell Region */ -/* -------------- */ - pseudo_bit_t reserved58[0x00fc0]; -/* -------------- */ - struct arbelprm_clr_int_st clr_int; /* Clear Interrupt Register */ -/* -------------- */ - pseudo_bit_t reserved59[0xffcfc0]; -/* -------------- */ -}; -#endif /* H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H */ diff --git a/gpxe/src/drivers/infiniband/MT25408_PRM.h b/gpxe/src/drivers/infiniband/MT25408_PRM.h deleted file mode 100644 index 419e25ac..00000000 --- a/gpxe/src/drivers/infiniband/MT25408_PRM.h +++ /dev/null @@ -1,3319 +0,0 @@ -/* - This software is available to you under a choice of one of two - licenses. You may choose to be licensed under the terms of the GNU - General Public License (GPL) Version 2, available at - <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD - license, available in the LICENSE.TXT file accompanying this - software. These details are also available at - <http://openib.org/license.html>. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - SOFTWARE. - - Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. -*/ - -FILE_LICENCE ( GPL2_ONLY ); - -/*** - *** This file was generated at "Mon Apr 16 23:22:02 2007" - *** by: - *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix hermonprm_ -bits -fixnames MT25408_PRM.csp - ***/ - -#ifndef H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H -#define H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H - -/* UD Address Vector */ - -struct hermonprm_ud_address_vector_st { /* Little Endian */ - pseudo_bit_t pd[0x00018]; /* Protection Domain */ - pseudo_bit_t port_number[0x00002]; /* Port number - 1 - Port 1 - 2 - Port 2 - other - reserved */ - pseudo_bit_t reserved0[0x00005]; - pseudo_bit_t fl[0x00001]; /* force loopback */ -/* -------------- */ - pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ - pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ - pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ - pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. - 0 - 4X injection rate - 1 - 1X injection rate - other - reserved - */ - pseudo_bit_t reserved2[0x00004]; - pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table - mgid_index = (port_number-1) * 2^log_max_gid + gid_index - Where: - 1. log_max_gid is taken from QUERY_DEV_CAP command - 2. gid_index is the index to the GID table */ - pseudo_bit_t reserved3[0x00009]; -/* -------------- */ - pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ - pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ - pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ -/* -------------- */ - pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ -/* -------------- */ - pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ -/* -------------- */ - pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ -/* -------------- */ - pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */ -/* -------------- */ -}; - -/* Send doorbell */ - -struct hermonprm_send_doorbell_st { /* Little Endian */ - pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */ - pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */ - pseudo_bit_t reserved0[0x00002]; - pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */ - pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */ -/* -------------- */ - pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */ - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ -/* -------------- */ -}; - -/* Send wqe segment data inline */ - -struct hermonprm_wqe_segment_data_inline_st { /* Little Endian */ - pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */ - pseudo_bit_t reserved0[0x00015]; - pseudo_bit_t always1[0x00001]; -/* -------------- */ - pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t reserved2[0x00040]; -/* -------------- */ -}; - -/* Send wqe segment data ptr */ - -struct hermonprm_wqe_segment_data_ptr_st { /* Little Endian */ - pseudo_bit_t byte_count[0x0001f]; - pseudo_bit_t always0[0x00001]; -/* -------------- */ - pseudo_bit_t l_key[0x00020]; -/* -------------- */ - pseudo_bit_t local_address_h[0x00020]; -/* -------------- */ - pseudo_bit_t local_address_l[0x00020]; -/* -------------- */ -}; - -/* Send wqe segment rd */ - -struct hermonprm_local_invalidate_segment_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - pseudo_bit_t mem_key[0x00018]; - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t reserved2[0x000a0]; -/* -------------- */ -}; - -/* Fast_Registration_Segment ####michal - doesn't match PRM (fields were added, see below) new table size in bytes - 0x30 */ - -struct hermonprm_fast_registration_segment_st { /* Little Endian */ - pseudo_bit_t reserved0[0x0001b]; - pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */ - pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */ - pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */ - pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */ - pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */ -/* -------------- */ - pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list ### michal - this field is replaced with mem_key .32 */ -/* -------------- */ - pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. ###michal-this field is replaced with pbl_ptr_63_32 */ -/* -------------- */ - pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. - page_size should be less than 20. ###michal - field doesn't exsist (see replacement above) */ - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t zb[0x00001]; /* Zero Based Region ###michal - field doesn't exsist (see replacement above) */ - pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list ###michal - field doesn't exsist (see replacement above) */ -/* -------------- */ - pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */ -/* -------------- */ - pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */ -/* -------------- */ - pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */ -/* -------------- */ - pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */ -/* -------------- */ -}; - -/* Send wqe segment atomic */ - -struct hermonprm_wqe_segment_atomic_st { /* Little Endian */ - pseudo_bit_t swap_add_h[0x00020]; -/* -------------- */ - pseudo_bit_t swap_add_l[0x00020]; -/* -------------- */ - pseudo_bit_t compare_h[0x00020]; -/* -------------- */ - pseudo_bit_t compare_l[0x00020]; -/* -------------- */ -}; - -/* Send wqe segment remote address */ - -struct hermonprm_wqe_segment_remote_address_st { /* Little Endian */ - pseudo_bit_t remote_virt_addr_h[0x00020]; -/* -------------- */ - pseudo_bit_t remote_virt_addr_l[0x00020]; -/* -------------- */ - pseudo_bit_t rkey[0x00020]; -/* -------------- */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ -}; - -/* end wqe segment bind */ - -struct hermonprm_wqe_segment_bind_st { /* Little Endian */ - pseudo_bit_t reserved0[0x0001d]; - pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */ - pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window. - */ - pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */ -/* -------------- */ - pseudo_bit_t reserved1[0x0001e]; - pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */ - pseudo_bit_t type[0x00001]; /* Window type. - 0 - Type one window - 1 - Type two window - */ -/* -------------- */ - pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */ -/* -------------- */ - pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */ -/* -------------- */ - pseudo_bit_t start_address_h[0x00020]; -/* -------------- */ - pseudo_bit_t start_address_l[0x00020]; -/* -------------- */ - pseudo_bit_t length_h[0x00020]; -/* -------------- */ - pseudo_bit_t length_l[0x00020]; -/* -------------- */ -}; - -/* Send wqe segment ud */ - -struct hermonprm_wqe_segment_ud_st { /* Little Endian */ - struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ -/* -------------- */ - pseudo_bit_t destination_qp[0x00018]; - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t q_key[0x00020]; -/* -------------- */ - pseudo_bit_t reserved1[0x00040]; -/* -------------- */ -}; - -/* Send wqe segment rd */ - -struct hermonprm_wqe_segment_rd_st { /* Little Endian */ - pseudo_bit_t destination_qp[0x00018]; - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t q_key[0x00020]; -/* -------------- */ - pseudo_bit_t reserved1[0x00040]; -/* -------------- */ -}; - -/* Send wqe segment ctrl */ - -struct hermonprm_wqe_segment_ctrl_send_st { /* Little Endian */ - pseudo_bit_t opcode[0x00005]; - pseudo_bit_t reserved0[0x0001a]; - pseudo_bit_t owner[0x00001]; -/* -------------- */ - pseudo_bit_t ds[0x00006]; /* descriptor (wqe) size in 16bytes chunk */ - pseudo_bit_t f[0x00001]; /* fence */ - pseudo_bit_t reserved1[0x00019]; -/* -------------- */ - pseudo_bit_t fl[0x00001]; /* Force LoopBack */ - pseudo_bit_t s[0x00001]; /* Remote Solicited Event */ - pseudo_bit_t c[0x00002]; /* completion required: 0b00 - no 0b11 - yes */ - pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */ - pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */ - pseudo_bit_t reserved2[0x00001]; - pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */ - pseudo_bit_t src_remote_buf[0x00018]; -/* -------------- */ - pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */ -/* -------------- */ -}; - -/* Address Path # ###michal - match to PRM */ - -struct hermonprm_address_path_st { /* Little Endian */ - pseudo_bit_t pkey_index[0x00007]; /* PKey table index */ - pseudo_bit_t reserved0[0x00016]; - pseudo_bit_t sv[0x00001]; /* Service VLAN on QP */ - pseudo_bit_t cv[0x00001]; /* Customer VLAN in QP */ - pseudo_bit_t fl[0x00001]; /* Force LoopBack */ -/* -------------- */ - pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ - pseudo_bit_t my_lid_smac_idx[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ - pseudo_bit_t grh_ip[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ - pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. - 0 - 100% injection rate - 1 - 25% injection rate - 2 - 12.5% injection rate - 3 - 50% injection rate - 7: 2.5 Gb/s. - 8: 10 Gb/s. - 9: 30 Gb/s. - 10: 5 Gb/s. - 11: 20 Gb/s. - 12: 40 Gb/s. - 13: 60 Gb/s. - 14: 80 Gb/s. - 15: 120 Gb/s. */ - pseudo_bit_t reserved2[0x00004]; - pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table */ - pseudo_bit_t reserved3[0x00004]; - pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details. - The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */ -/* -------------- */ - pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ - pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ - pseudo_bit_t reserved4[0x00004]; -/* -------------- */ - pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ -/* -------------- */ - pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ -/* -------------- */ - pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ -/* -------------- */ - pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */ -/* -------------- */ - pseudo_bit_t reserved5[0x00008]; - pseudo_bit_t sp[0x00001]; /* if set, spoofing protection is enforced on this QP and Ethertype headers are restricted */ - pseudo_bit_t reserved6[0x00002]; - pseudo_bit_t fvl[0x00001]; /* force VLAN */ - pseudo_bit_t fsip[0x00001]; /* force source IP */ - pseudo_bit_t fsm[0x00001]; /* force source MAC */ - pseudo_bit_t reserved7[0x0000a]; - pseudo_bit_t sched_queue[0x00008]; -/* -------------- */ - pseudo_bit_t dmac_47_32[0x00010]; - pseudo_bit_t vlan_index[0x00007]; - pseudo_bit_t reserved8[0x00001]; - pseudo_bit_t counter_index[0x00008];/* Index to a table of counters that counts egress packets and bytes, 0xFF not valid */ -/* -------------- */ - pseudo_bit_t dmac_31_0[0x00020]; -/* -------------- */ -}; - -/* HCA Command Register (HCR) #### michal - match PRM */ - -struct hermonprm_hca_command_register_st { /* Little Endian */ - pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */ -/* -------------- */ - pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */ -/* -------------- */ - pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */ -/* -------------- */ - pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */ -/* -------------- */ - pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */ -/* -------------- */ - pseudo_bit_t reserved0[0x00010]; - pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */ -/* -------------- */ - pseudo_bit_t opcode[0x0000c]; /* Command opcode */ - pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */ - pseudo_bit_t reserved1[0x00005]; - pseudo_bit_t t[0x00001]; /* Toggle */ - pseudo_bit_t e[0x00001]; /* Event Request - 0 - Don't report event (software will poll the GO bit) - 1 - Report event to EQ when the command completes */ - pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR) - Software can write to the HCR only if Go bit is cleared. - Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */ - pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared) - 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */ -/* -------------- */ -}; - -/* CQ Doorbell */ - -struct hermonprm_cq_cmd_doorbell_st { /* Little Endian */ - pseudo_bit_t cqn[0x00018]; /* CQ number accessed */ - pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ - 0x0 - Reserved - 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter. - 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter. - 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated - Other - Reserved */ - pseudo_bit_t reserved0[0x00001]; - pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ. - This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited - completion or Request notification for multiple completions doorbells after receiving completion notification. - This field is initialized to Zero */ - pseudo_bit_t reserved1[0x00002]; -/* -------------- */ - pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */ -/* -------------- */ -}; - -/* RD-send doorbell */ - -struct hermonprm_rd_send_doorbell_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram) - Must be zero for Nop and Bind operations */ -/* -------------- */ - pseudo_bit_t reserved1[0x00008]; - pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ -/* -------------- */ - struct hermonprm_send_doorbell_st send_doorbell;/* Send Parameters */ -/* -------------- */ -}; - -/* Multicast Group Member QP #### michal - match PRM */ - -struct hermonprm_mgmqp_st { /* Little Endian */ - pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */ - pseudo_bit_t reserved0[0x00006]; - pseudo_bit_t blck_lb[0x00001]; /* Block self-loopback messages arriving to this qp */ - pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */ -/* -------------- */ -}; - -/* vsd */ - -struct hermonprm_vsd_st { /* Little Endian */ - pseudo_bit_t vsd_dw0[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw1[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw2[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw3[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw4[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw5[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw6[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw7[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw8[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw9[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw10[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw11[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw12[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw13[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw14[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw15[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw16[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw17[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw18[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw19[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw20[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw21[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw22[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw23[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw24[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw25[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw26[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw27[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw28[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw29[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw30[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw31[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw32[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw33[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw34[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw35[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw36[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw37[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw38[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw39[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw40[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw41[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw42[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw43[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw44[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw45[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw46[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw47[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw48[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw49[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw50[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw51[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw52[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw53[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw54[0x00020]; -/* -------------- */ - pseudo_bit_t vsd_dw55[0x00020]; -/* -------------- */ -}; - -/* UAR Parameters */ - -struct hermonprm_uar_params_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page. - Size of UAR Page is 4KB*2^UAR_Page_Size */ - pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */ - pseudo_bit_t reserved1[0x00014]; -/* -------------- */ - pseudo_bit_t reserved2[0x000a0]; -/* -------------- */ -}; - -/* Translation and Protection Tables Parameters */ - -struct hermonprm_tptparams_st { /* Little Endian */ - pseudo_bit_t dmpt_base_adr_h[0x00020];/* dMPT - Memory Protection Table base physical address [63:32]. - Entry size is 64 bytes. - Table must be aligned to its size. - Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ -/* -------------- */ - pseudo_bit_t dmpt_base_adr_l[0x00020];/* dMPT - Memory Protection Table base physical address [31:0]. - Entry size is 64 bytes. - Table must be aligned to its size. - Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ -/* -------------- */ - pseudo_bit_t log_dmpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the dMPT table. */ - pseudo_bit_t reserved0[0x00002]; - pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout - - The field returned in RNR Naks generated when a page fault is detected. - It has no effect when on-demand-paging is not used. */ - pseudo_bit_t reserved1[0x00013]; -/* -------------- */ - pseudo_bit_t reserved2[0x00020]; -/* -------------- */ - pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32]. - Table must be aligned to its size. - Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ -/* -------------- */ - pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0]. - Table must be aligned to its size. - Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ -/* -------------- */ - pseudo_bit_t cmpt_base_adr_h[0x00020];/* cMPT - Memory Protection Table base physical address [63:32]. - Entry size is 64 bytes. - Table must be aligned to its size. */ -/* -------------- */ - pseudo_bit_t cmpt_base_adr_l[0x00020];/* cMPT - Memory Protection Table base physical address [31:0]. - Entry size is 64 bytes. - Table must be aligned to its size. */ -/* -------------- */ -}; - -/* Multicast Support Parameters #### michal - match PRM */ - -struct hermonprm_multicastparam_st { /* Little Endian */ - pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32]. - The base address must be aligned to the entry size. - Address may be set to 0xFFFFFFFF if multicast is not supported. */ -/* -------------- */ - pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. - The base address must be aligned to the entry size. - Address may be set to 0xFFFFFFFF if multicast is not supported. */ -/* -------------- */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - pseudo_bit_t log_mc_table_entry_sz[0x00005];/* Log2 of the Size of multicast group member (MGM) entry. - Must be greater than 5 (to allow CTRL and GID sections). - That implies the number of QPs per MC table entry. */ - pseudo_bit_t reserved1[0x0000b]; - pseudo_bit_t reserved2[0x00010]; -/* -------------- */ - pseudo_bit_t log_mc_table_hash_sz[0x00005];/* Number of entries in multicast DGID hash table (must be power of 2) - INIT_HCA - the required number of entries - QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */ - pseudo_bit_t reserved3[0x0001b]; -/* -------------- */ - pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */ - pseudo_bit_t reserved4[0x00013]; - pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function - 0 - Default hash function - other - reserved */ - pseudo_bit_t reserved5[0x00005]; -/* -------------- */ - pseudo_bit_t reserved6[0x00020]; -/* -------------- */ -}; - -/* QPC/EEC/CQC/EQC/RDB Parameters #### michal - doesn't match PRM (field name are differs. see below) */ - -struct hermonprm_qpcbaseaddr_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32] - Table must be aligned on its size */ -/* -------------- */ - pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */ - pseudo_bit_t qpc_base_addr_l[0x0001b];/* QPC Base Address [31:7] - Table must be aligned on its size */ -/* -------------- */ - pseudo_bit_t reserved1[0x00040]; -/* -------------- */ - pseudo_bit_t reserved2[0x00040]; -/* -------------- */ - pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32] - Table must be aligned on its size - Address may be set to 0xFFFFFFFF if SRQ is not supported. */ -/* -------------- */ - pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */ - pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5] - Table must be aligned on its size - Address may be set to 0xFFFFFFFF if SRQ is not supported. */ -/* -------------- */ - pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32] - Table must be aligned on its size */ -/* -------------- */ - pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */ - pseudo_bit_t cqc_base_addr_l[0x0001b];/* CQC Base Address [31:6] - Table must be aligned on its size */ -/* -------------- */ - pseudo_bit_t reserved3[0x00040]; -/* -------------- */ - pseudo_bit_t altc_base_addr_h[0x00020];/* AltC Base Address (altc_base_addr_h) [63:32] - Table has same number of entries as QPC table. - Table must be aligned to entry size. */ -/* -------------- */ - pseudo_bit_t altc_base_addr_l[0x00020];/* AltC Base Address (altc_base_addr_l) [31:0] - Table has same number of entries as QPC table. - Table must be aligned to entry size. */ -/* -------------- */ - pseudo_bit_t reserved4[0x00040]; -/* -------------- */ - pseudo_bit_t auxc_base_addr_h[0x00020]; -/* -------------- */ - pseudo_bit_t auxc_base_addr_l[0x00020]; -/* -------------- */ - pseudo_bit_t reserved5[0x00040]; -/* -------------- */ - pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32] - Address may be set to 0xFFFFFFFF if EQs are not supported. - Table must be aligned to entry size. */ -/* -------------- */ - pseudo_bit_t log_num_of_eq[0x00005];/* Log base 2 of number of supported EQs. - Must be 6 or less in InfiniHost-III-EX. */ - pseudo_bit_t eqc_base_addr_l[0x0001b];/* EQC Base Address [31:6] - Address may be set to 0xFFFFFFFF if EQs are not supported. - Table must be aligned to entry size. */ -/* -------------- */ - pseudo_bit_t reserved6[0x00040]; -/* -------------- */ - pseudo_bit_t rdmardc_base_addr_h[0x00020];/* rdmardc_base_addr_h: Base address of table that holds remote read and remote atomic requests [63:32]. */ -/* -------------- */ - pseudo_bit_t log_num_rd[0x00003]; /* Log (base 2) of the maximum number of RdmaRdC entries per QP. This denotes the maximum number of outstanding reads/atomics as a responder. */ - pseudo_bit_t reserved7[0x00002]; - pseudo_bit_t rdmardc_base_addr_l[0x0001b];/* rdmardc_base_addr_l: Base address of table that holds remote read and remote atomic requests [31:0]. - Table must be aligned to RDB entry size (32 bytes). */ -/* -------------- */ - pseudo_bit_t reserved8[0x00040]; -/* -------------- */ -}; - -/* Header_Log_Register */ - -struct hermonprm_header_log_register_st { /* Little Endian */ - pseudo_bit_t place_holder[0x00020]; -/* -------------- */ - pseudo_bit_t reserved0[0x00060]; -/* -------------- */ -}; - -/* Performance Monitors */ - -struct hermonprm_performance_monitors_st { /* Little Endian */ - pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */ - pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */ - pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */ - pseudo_bit_t reserved0[0x00001]; - pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ - pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ - pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ - pseudo_bit_t reserved1[0x00001]; - pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ - pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ - pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ - pseudo_bit_t reserved2[0x00001]; - pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ - pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ - pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ - pseudo_bit_t reserved3[0x00001]; - pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */ - pseudo_bit_t reserved4[0x00003]; - pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */ - pseudo_bit_t reserved5[0x00003]; -/* -------------- */ - pseudo_bit_t clock_counter[0x00020]; -/* -------------- */ - pseudo_bit_t event_counter1[0x00020]; -/* -------------- */ - pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */ -/* -------------- */ -}; - -/* MLX WQE segment format */ - -struct hermonprm_wqe_segment_ctrl_mlx_st { /* Little Endian */ - pseudo_bit_t opcode[0x00005]; /* must be 0xA = SEND */ - pseudo_bit_t reserved0[0x0001a]; - pseudo_bit_t owner[0x00001]; -/* -------------- */ - pseudo_bit_t ds[0x00006]; /* Descriptor Size */ - pseudo_bit_t reserved1[0x0001a]; -/* -------------- */ - pseudo_bit_t fl[0x00001]; /* Force LoopBack */ - pseudo_bit_t reserved2[0x00001]; - pseudo_bit_t c[0x00002]; /* Create CQE (for "requested signalling" QP) */ - pseudo_bit_t icrc[0x00001]; /* last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. 1 - Leave last dword as is. */ - pseudo_bit_t reserved3[0x00003]; - pseudo_bit_t sl[0x00004]; - pseudo_bit_t max_statrate[0x00004]; - pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */ - pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */ - pseudo_bit_t reserved4[0x0000e]; -/* -------------- */ - pseudo_bit_t reserved5[0x00010]; - pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */ -/* -------------- */ -}; - -/* Send WQE segment format */ - -struct hermonprm_send_wqe_segment_st { /* Little Endian */ - struct hermonprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */ -/* -------------- */ - struct hermonprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */ -/* -------------- */ - struct hermonprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */ -/* -------------- */ - struct hermonprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */ -/* -------------- */ - pseudo_bit_t reserved0[0x00180]; -/* -------------- */ - struct hermonprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */ -/* -------------- */ - struct hermonprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */ -/* -------------- */ - struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ -/* -------------- */ - struct hermonprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */ -/* -------------- */ - struct hermonprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */ -/* -------------- */ - struct hermonprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */ -/* -------------- */ - pseudo_bit_t reserved1[0x00200]; -/* -------------- */ -}; - -/* QP and EE Context Entry */ - -struct hermonprm_queue_pair_ee_context_entry_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t reserved1[0x00001]; - pseudo_bit_t reserved2[0x00002]; - pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm) - 11-Migrated - 00-Armed - 01-Rearm - 10-Reserved - Should be set to 11 for UD QPs and for QPs which do not support APM */ - pseudo_bit_t reserved3[0x00003]; - pseudo_bit_t st[0x00004]; /* Transport Service Type: RC: 0, UC: 1, RD: 2, UD: 3, FCMND:4, FEXCH:5, SRC:6, MLX 7, Raw Eth 11 */ - pseudo_bit_t reserved4[0x00008]; - pseudo_bit_t state[0x00004]; /* QP/EE state: - 0 - RST - 1 - INIT - 2 - RTR - 3 - RTS - 4 - SQEr - 5 - SQD (Send Queue Drained) - 6 - ERR - 7 - Send Queue Draining - 8 - Reserved - 9 - Suspended - A- F - Reserved - (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */ -/* -------------- */ - pseudo_bit_t pd[0x00018]; - pseudo_bit_t reserved5[0x00008]; -/* -------------- */ - pseudo_bit_t reserved6[0x00004]; - pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */ - pseudo_bit_t reserved7[0x00003]; - pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes. - Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ - pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */ - pseudo_bit_t reserved8[0x00001]; - pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. - Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ - pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */ - pseudo_bit_t reserved9[0x00001]; - pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max. - Must be equal to MTU for UD and MLX QPs. */ - pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative): - 0x1 - 256 bytes - 0x2 - 512 - 0x3 - 1024 - 0x4 - 2048 - other - reserved - - Should be configured to 0x4 for UD and MLX QPs. */ -/* -------------- */ - pseudo_bit_t usr_page[0x00018]; /* UAR number to ring doorbells for this QP (aliased to doorbell and Blue Flame pages) */ - pseudo_bit_t reserved10[0x00008]; -/* -------------- */ - pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained - This field is valid for QUERY and ERR2RST commands only. */ - pseudo_bit_t reserved11[0x00008]; -/* -------------- */ - pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */ - pseudo_bit_t reserved12[0x00008]; -/* -------------- */ - struct hermonprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */ -/* -------------- */ - struct hermonprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */ -/* -------------- */ - pseudo_bit_t reserved13[0x00003]; - pseudo_bit_t reserved14[0x00001]; - pseudo_bit_t reserved15[0x00001]; - pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only). - The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */ - pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only). - The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */ - pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */ - pseudo_bit_t reserved16[0x00001]; - pseudo_bit_t rnr_retry[0x00003]; - pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */ - pseudo_bit_t reserved17[0x00002]; - pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */ - pseudo_bit_t reserved18[0x00004]; - pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */ -/* -------------- */ - pseudo_bit_t reserved19[0x00020]; -/* -------------- */ - pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */ - pseudo_bit_t reserved20[0x00008]; -/* -------------- */ - pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */ - pseudo_bit_t reserved21[0x00008]; -/* -------------- */ - pseudo_bit_t reserved22[0x00040]; -/* -------------- */ - pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */ - pseudo_bit_t reserved23[0x00008]; -/* -------------- */ - pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */ - pseudo_bit_t reserved24[0x00008]; -/* -------------- */ - pseudo_bit_t reserved25[0x00004]; - pseudo_bit_t ric[0x00001]; /* Invalid Credits. - 1 - place "Invalid Credits" to ACKs sent from this queue. - 0 - ACKs report the actual number of end to end credits on the connection. - Not valid (reserved) in EE context. - Must be set to 1 on QPs which are attached to SRQ. */ - pseudo_bit_t reserved26[0x00001]; - pseudo_bit_t page_offset[0x00006]; /* start address of wqes in first page (11:6), bits [5:0] reserved */ - pseudo_bit_t reserved27[0x00001]; - pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */ - pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */ - pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */ - pseudo_bit_t reserved28[0x00005]; - pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. - Must be 0 for EE context. */ - pseudo_bit_t reserved29[0x00008]; -/* -------------- */ - pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */ - pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). - Not valid (reserved) in EE context. */ - pseudo_bit_t reserved30[0x00003]; -/* -------------- */ - pseudo_bit_t srcd[0x00010]; /* Scalable Reliable Connection Domain. Valid for SRC transport service */ - pseudo_bit_t reserved31[0x00010]; -/* -------------- */ - pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */ - pseudo_bit_t reserved32[0x00008]; -/* -------------- */ - pseudo_bit_t db_record_addr_h[0x00020];/* QP DB Record physical address */ -/* -------------- */ - pseudo_bit_t reserved33[0x00002]; - pseudo_bit_t db_record_addr_l[0x0001e];/* QP DB Record physical address */ -/* -------------- */ - pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams. - On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message. - Not valid (reserved) in EE context. */ -/* -------------- */ - pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. - SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */ - pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */ - pseudo_bit_t reserved34[0x00007]; -/* -------------- */ - pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */ - pseudo_bit_t reserved35[0x00008]; -/* -------------- */ - pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. - Must be 0x0 in SQ initialization. - (QUERY_QPEE only). */ - pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ. - Must be 0x0 in RQ initialization. - (QUERY_QPEE only). */ -/* -------------- */ - pseudo_bit_t reserved36[0x00040]; -/* -------------- */ - pseudo_bit_t rmc_parent_qpn[0x00018];/* reliable multicast parent queue number */ - pseudo_bit_t hs[0x00001]; /* Header Separation. If set, the byte count of the first scatter entry will be ignored. The buffer specified by the first scatter entry will contain packet headers (up to TCP). CQE will report number of bytes scattered to the first scatter entry. Intended for use on IPoverIB on UD QP or Raw Ethernet QP. */ - pseudo_bit_t is[0x00001]; /* when set - inline scatter is enabled for this RQ */ - pseudo_bit_t reserved37[0x00001]; - pseudo_bit_t rme[0x00002]; /* Reliable Multicast - 00 - disabled - 01 - parent QP (requester) - 10 - child QP (requester) - 11 - responder QP - Note that Reliable Multicast is a preliminary definition which can be subject to change. */ - pseudo_bit_t reserved38[0x00002]; - pseudo_bit_t mkey_rmp[0x00001]; /* If set, MKey used to access TPT for incoming RDMA-write request is calculated by adding MKey from the packet to base_MKey field in the QPC. Can be set only for QPs that are not target for RDMA-read request. */ -/* -------------- */ - pseudo_bit_t base_mkey[0x00018]; /* Base Mkey bits [31:8]. Lower 8 bits must be zero. */ - pseudo_bit_t num_rmc_peers[0x00008];/* Number of remote peers in Reliable Multicast group */ -/* -------------- */ - pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ - pseudo_bit_t reserved39[0x00010]; - pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ - pseudo_bit_t reserved40[0x00002]; -/* -------------- */ - pseudo_bit_t reserved41[0x00003]; - pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ -/* -------------- */ - pseudo_bit_t vft_lan[0x0000c]; - pseudo_bit_t vft_prio[0x00003]; /* The Priority filed in the VFT header for FCP */ - pseudo_bit_t reserved42[0x00001]; - pseudo_bit_t cs_ctl[0x00009]; /* The Priority filed in the VFT header for FCP */ - pseudo_bit_t reserved43[0x00006]; - pseudo_bit_t ve[0x00001]; /* Should we add/check the VFT header */ -/* -------------- */ - pseudo_bit_t exch_base[0x00010]; /* For init QP only - The base exchanges */ - pseudo_bit_t reserved44[0x00008]; - pseudo_bit_t exch_size[0x00004]; /* For CMMD QP only - The size (from base) exchanges is 2exchanges_size */ - pseudo_bit_t reserved45[0x00003]; - pseudo_bit_t fc[0x00001]; /* When set it mean that this QP is used for FIBRE CHANNEL. */ -/* -------------- */ - pseudo_bit_t remote_id[0x00018]; /* Peer NX port ID */ - pseudo_bit_t reserved46[0x00008]; -/* -------------- */ - pseudo_bit_t fcp_mtu[0x0000a]; /* In 4*Bytes units. The MTU Size */ - pseudo_bit_t reserved47[0x00006]; - pseudo_bit_t my_id_indx[0x00008]; /* Index to My NX port ID table */ - pseudo_bit_t vft_hop_count[0x00008];/* HopCnt value for the VFT header */ -/* -------------- */ - pseudo_bit_t reserved48[0x000c0]; -/* -------------- */ -}; - -/* */ - -struct hermonprm_mcg_qp_dw_st { /* Little Endian */ - pseudo_bit_t qpn[0x00018]; - pseudo_bit_t reserved0[0x00006]; - pseudo_bit_t blck_lb[0x00001]; - pseudo_bit_t reserved1[0x00001]; -/* -------------- */ -}; - -/* Clear Interrupt [63:0] #### michal - match to PRM */ - -struct hermonprm_clr_int_st { /* Little Endian */ - pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32] - Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. - This register is write-only. Reading from this register will cause undefined result - */ -/* -------------- */ - pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0] - Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. - This register is write-only. Reading from this register will cause undefined result */ -/* -------------- */ -}; - -/* EQ Set CI DBs Table */ - -struct hermonprm_eq_set_ci_table_st { /* Little Endian */ - pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved2[0x00020]; -/* -------------- */ - pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved4[0x00020]; -/* -------------- */ - pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ - pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved6[0x00020]; -/* -------------- */ - pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved7[0x00020]; -/* -------------- */ - pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved8[0x00020]; -/* -------------- */ - pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved9[0x00020]; -/* -------------- */ - pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved10[0x00020]; -/* -------------- */ - pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved11[0x00020]; -/* -------------- */ - pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved12[0x00020]; -/* -------------- */ - pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved13[0x00020]; -/* -------------- */ - pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved14[0x00020]; -/* -------------- */ - pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved15[0x00020]; -/* -------------- */ - pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved16[0x00020]; -/* -------------- */ - pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved17[0x00020]; -/* -------------- */ - pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved18[0x00020]; -/* -------------- */ - pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved19[0x00020]; -/* -------------- */ - pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved20[0x00020]; -/* -------------- */ - pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved21[0x00020]; -/* -------------- */ - pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved22[0x00020]; -/* -------------- */ - pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved23[0x00020]; -/* -------------- */ - pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved24[0x00020]; -/* -------------- */ - pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved25[0x00020]; -/* -------------- */ - pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved26[0x00020]; -/* -------------- */ - pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved27[0x00020]; -/* -------------- */ - pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved28[0x00020]; -/* -------------- */ - pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved29[0x00020]; -/* -------------- */ - pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved30[0x00020]; -/* -------------- */ - pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved31[0x00020]; -/* -------------- */ - pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved32[0x00020]; -/* -------------- */ - pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved33[0x00020]; -/* -------------- */ - pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved34[0x00020]; -/* -------------- */ - pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved35[0x00020]; -/* -------------- */ - pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved36[0x00020]; -/* -------------- */ - pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved37[0x00020]; -/* -------------- */ - pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved38[0x00020]; -/* -------------- */ - pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved39[0x00020]; -/* -------------- */ - pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved40[0x00020]; -/* -------------- */ - pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved41[0x00020]; -/* -------------- */ - pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved42[0x00020]; -/* -------------- */ - pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved43[0x00020]; -/* -------------- */ - pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved44[0x00020]; -/* -------------- */ - pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved45[0x00020]; -/* -------------- */ - pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved46[0x00020]; -/* -------------- */ - pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved47[0x00020]; -/* -------------- */ - pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved48[0x00020]; -/* -------------- */ - pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved49[0x00020]; -/* -------------- */ - pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved50[0x00020]; -/* -------------- */ - pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved51[0x00020]; -/* -------------- */ - pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved52[0x00020]; -/* -------------- */ - pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved53[0x00020]; -/* -------------- */ - pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved54[0x00020]; -/* -------------- */ - pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved55[0x00020]; -/* -------------- */ - pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved56[0x00020]; -/* -------------- */ - pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved57[0x00020]; -/* -------------- */ - pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved58[0x00020]; -/* -------------- */ - pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved59[0x00020]; -/* -------------- */ - pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved60[0x00020]; -/* -------------- */ - pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved61[0x00020]; -/* -------------- */ - pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved62[0x00020]; -/* -------------- */ - pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */ -/* -------------- */ - pseudo_bit_t reserved63[0x00020]; -/* -------------- */ -}; - -/* InfiniHost-III-EX Configuration Registers #### michal - match to PRM */ - -struct hermonprm_configuration_registers_st { /* Little Endian */ - pseudo_bit_t reserved0[0x403400]; -/* -------------- */ - struct hermonprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */ -/* -------------- */ - pseudo_bit_t reserved1[0x3fcb20]; -/* -------------- */ -}; - -/* QP_DB_Record ### michal = gdror fixed */ - -struct hermonprm_qp_db_record_st { /* Little Endian */ - pseudo_bit_t receive_wqe_counter[0x00010];/* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */ - pseudo_bit_t reserved0[0x00010]; -/* -------------- */ -}; - -/* CQ_ARM_DB_Record */ - -struct hermonprm_cq_arm_db_record_st { /* Little Endian */ - pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */ -/* -------------- */ - pseudo_bit_t cmd[0x00003]; /* 0x0 - No command - 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter. - 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter. - 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated - Other - Reserved */ - pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */ - pseudo_bit_t res[0x00003]; /* Must be 0x2 */ - pseudo_bit_t cq_number[0x00018]; /* CQ number */ -/* -------------- */ -}; - -/* CQ_CI_DB_Record */ - -struct hermonprm_cq_ci_db_record_st { /* Little Endian */ - pseudo_bit_t counter[0x00020]; /* CQ counter */ -/* -------------- */ - pseudo_bit_t reserved0[0x00005]; - pseudo_bit_t res[0x00003]; /* Must be 0x1 */ - pseudo_bit_t cq_number[0x00018]; /* CQ number */ -/* -------------- */ -}; - -/* Virtual_Physical_Mapping */ - -struct hermonprm_virtual_physical_mapping_st { /* Little Endian */ - pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */ -/* -------------- */ - pseudo_bit_t reserved0[0x0000c]; - pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */ -/* -------------- */ - pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */ -/* -------------- */ - pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */ - pseudo_bit_t reserved1[0x00006]; - pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */ -/* -------------- */ -}; - -/* MOD_STAT_CFG #### michal - gdror fix */ - -struct hermonprm_mod_stat_cfg_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00010]; - pseudo_bit_t rx_options[0x00004]; /* number of RX options to sweep when doing SerDes parameters AutoNegotiation. */ - pseudo_bit_t reserved1[0x00003]; - pseudo_bit_t rx_options_m[0x00001]; /* Modify rx_options */ - pseudo_bit_t tx_options[0x00004]; /* number of TX options to sweep when doing SerDes parameters AutoNegotiation. */ - pseudo_bit_t reserved2[0x00003]; - pseudo_bit_t tx_options_m[0x00001]; /* Modify tx_options */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t pre_amp[0x00004]; /* Pre Amplitude */ - pseudo_bit_t pre_emp_pre_amp[0x00004]; - pseudo_bit_t pre_emp_out[0x00004]; /* Pre Emphasis Out */ - pseudo_bit_t voltage[0x00004]; - pseudo_bit_t equ[0x00004]; /* Equalization */ - pseudo_bit_t reserved4[0x0000b]; - pseudo_bit_t serdes_m[0x00001]; /* Modify serdes parameters */ -/* -------------- */ - pseudo_bit_t lid[0x00010]; /* default LID */ - pseudo_bit_t lid_m[0x00001]; /* Modify default LID */ - pseudo_bit_t reserved5[0x00003]; - pseudo_bit_t port_en[0x00001]; /* enable port (E_Key) */ - pseudo_bit_t port_en_m[0x00001]; /* Modify port_en */ - pseudo_bit_t reserved6[0x0000a]; -/* -------------- */ - pseudo_bit_t reserved7[0x0001f]; - pseudo_bit_t guid_hi_m[0x00001]; /* Modify guid_hi */ -/* -------------- */ - pseudo_bit_t guid_hi[0x00020]; -/* -------------- */ - pseudo_bit_t reserved8[0x0001f]; - pseudo_bit_t guid_lo_m[0x00001]; /* Modify guid_lo */ -/* -------------- */ - pseudo_bit_t guid_lo[0x00020]; -/* -------------- */ - pseudo_bit_t reserved9[0x0001f]; - pseudo_bit_t nodeguid_hi_m[0x00001]; -/* -------------- */ - pseudo_bit_t nodeguid_hi[0x00020]; -/* -------------- */ - pseudo_bit_t reserved10[0x0001f]; - pseudo_bit_t nodeguid_lo_m[0x00001]; -/* -------------- */ - pseudo_bit_t nodeguid_lo[0x00020]; -/* -------------- */ - pseudo_bit_t reserved11[0x00680]; -/* -------------- */ -}; - -/* SRQ Context */ - -struct hermonprm_srq_context_st { /* Little Endian */ - pseudo_bit_t srqn[0x00018]; /* SRQ number */ - pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. - Maximum value is 0x10, i.e. 16M WQEs. */ - pseudo_bit_t state[0x00004]; /* SRQ State: - 1111 - SW Ownership - 0000 - HW Ownership - 0001 - Error - Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ -/* -------------- */ - pseudo_bit_t src_domain[0x00010]; /* The Scalable RC Domain. Messages coming to receive ports specifying this SRQ as receive queue will be served only if SRC_Domain of the SRQ matches SRC_Domain of the transport QP of this message. */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t log_srq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */ - pseudo_bit_t reserved1[0x00005]; -/* -------------- */ - pseudo_bit_t cqn[0x00018]; /* Completion Queue to report SRC messages directed to this SRQ. */ - pseudo_bit_t page_offset[0x00006]; /* The offset of the first WQE from the beginning of 4Kbyte page (Figure 52,“Work Queue Buffer Structure”) */ - pseudo_bit_t reserved2[0x00002]; -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ - pseudo_bit_t reserved4[0x00010]; - pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ - pseudo_bit_t reserved5[0x00002]; -/* -------------- */ - pseudo_bit_t reserved6[0x00003]; - pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* SRQ protection domain */ - pseudo_bit_t reserved7[0x00008]; -/* -------------- */ - pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ - pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then an SRQ limit event is fired and the LWM is set to zero. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ -/* -------------- */ - pseudo_bit_t srq_wqe_counter[0x00010];/* A 16-bit counter incremented for each WQE posted to the SRQ. Must be 0x0 in SRQ initialization. Valid only upon the QUERY_SRQ command. */ - pseudo_bit_t reserved8[0x00010]; -/* -------------- */ - pseudo_bit_t reserved9[0x00020]; -/* -------------- */ - pseudo_bit_t db_record_addr_h[0x00020];/* SRQ DB Record physical address [63:32] */ -/* -------------- */ - pseudo_bit_t reserved10[0x00002]; - pseudo_bit_t db_record_addr_l[0x0001e];/* SRQ DB Record physical address [31:2] */ -/* -------------- */ -}; - -/* PBL */ - -struct hermonprm_pbl_st { /* Little Endian */ - pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */ -/* -------------- */ - pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */ -/* -------------- */ - pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */ -/* -------------- */ - pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */ -/* -------------- */ - pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */ -/* -------------- */ - pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */ -/* -------------- */ - pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */ -/* -------------- */ - pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */ -/* -------------- */ -}; - -/* Performance Counters #### michal - gdror fixed */ - -struct hermonprm_performance_counters_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t reserved1[0x00080]; -/* -------------- */ - pseudo_bit_t reserved2[0x00080]; -/* -------------- */ - pseudo_bit_t reserved3[0x00060]; -/* -------------- */ - pseudo_bit_t reserved4[0x00620]; -/* -------------- */ -}; - -/* Transport and CI Error Counters */ - -struct hermonprm_transport_and_ci_error_counters_st { /* Little Endian */ - pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */ -/* -------------- */ - pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */ -/* -------------- */ - pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */ -/* -------------- */ - pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */ -/* -------------- */ - pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */ -/* -------------- */ - pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */ -/* -------------- */ - pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */ -/* -------------- */ - pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */ -/* -------------- */ - pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error. - Incremented each time a CQE with error is generated */ -/* -------------- */ - pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error. - Incremented each time a CQE with error is generated */ -/* -------------- */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */ -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */ -/* -------------- */ - pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */ -/* -------------- */ - pseudo_bit_t reserved2[0x00040]; -/* -------------- */ - pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors - NAK-Invalid Request on: - 1. Unsupported OpCode: Responder detected an unsupported OpCode. - 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such - as a missing "Last" packet. - Note: there is no PSN error, thus this does not indicate a dropped packet. */ -/* -------------- */ - pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors. - NAK may or may not be sent. - 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only): - Inbound request OpCode was either reserved, or was for a function not supported by this - QP. (E.g. RDMA or ATOMIC on QP not set up for this). - 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion. - 3. Too many RDMA READ or ATOMIC Requests: There were more requests received - and not ACKed than allowed for the connection. - 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder - detected an error in the sequence of OpCodes; a missing "Last" packet - 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder - detected an error in the sequence of OpCodes; a missing "First" packet - 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able - buffer space. - 7. Length error: RDMA WRITE request message contained too much or too little pay-load - data compared to the DMA length advertised in the first or only packet. - 8. Length error: Payload length was not consistent with the opcode: - a: 0 byte <= "only" <= PMTU bytes - b: ("first" or "middle") == PMTU bytes - c: 1byte <= "last" <= PMTU bytes - 9. Length error: Inbound message exceeded the size supported by the CA port. */ -/* -------------- */ - pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors. - NAK-Remote Access Error on: - R_Key Violation: Responder detected an invalid R_Key while executing an RDMA - Request. */ -/* -------------- */ - pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors. - R_Key Violation Responder detected an R_Key violation while executing an RDMA - request. - NAK may or may not be sent. */ -/* -------------- */ - pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors. - NAK-Remote Operation Error on: - Remote Operation Error: Responder encountered an error, (local to the responder), - which prevented it from completing the request. */ -/* -------------- */ - pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors. - NAK-Remote Operation Error on: - 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing - the packet. - 2. Remote Operation Error: Responder encountered an error, (local to the responder), - which prevented it from completing the request. */ -/* -------------- */ - pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */ -/* -------------- */ - pseudo_bit_t rq_num_rnr[0x00020]; /* Responder - the number of RNR Naks sent */ -/* -------------- */ - pseudo_bit_t sq_num_rnr[0x00020]; /* Requester - the number of RNR Naks received */ -/* -------------- */ - pseudo_bit_t reserved4[0x00040]; -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */ -/* -------------- */ - pseudo_bit_t reserved6[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */ -/* -------------- */ - pseudo_bit_t reserved7[0x00020]; -/* -------------- */ - pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */ -/* -------------- */ - pseudo_bit_t reserved8[0x00380]; -/* -------------- */ - pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */ -/* -------------- */ - pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */ -/* -------------- */ - pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */ -/* -------------- */ - pseudo_bit_t reserved9[0x00020]; -/* -------------- */ - pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */ -/* -------------- */ - pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */ -/* -------------- */ - pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */ -/* -------------- */ - pseudo_bit_t reserved10[0x00020]; -/* -------------- */ - pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */ -/* -------------- */ - pseudo_bit_t reserved11[0x003e0]; -/* -------------- */ - pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */ -/* -------------- */ - pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */ -/* -------------- */ - pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */ -/* -------------- */ - pseudo_bit_t reserved12[0x002a0]; -/* -------------- */ -}; - -/* Event_data Field - HCR Completion Event #### michal - match PRM */ - -struct hermonprm_hcr_completion_event_st { /* Little Endian */ - pseudo_bit_t token[0x00010]; /* HCR Token */ - pseudo_bit_t reserved0[0x00010]; -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t status[0x00008]; /* HCR Status */ - pseudo_bit_t reserved2[0x00018]; -/* -------------- */ - pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */ -/* -------------- */ - pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ -}; - -/* Completion with Error CQE #### michal - gdror fixed */ - -struct hermonprm_completion_with_error_st { /* Little Endian */ - pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x000a0]; -/* -------------- */ - pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome: - 0x01 - Local Length Error - 0x02 - Local QP Operation Error - 0x03 - Local EE Context Operation Error - 0x04 - Local Protection Error - 0x05 - Work Request Flushed Error - 0x06 - Memory Window Bind Error - 0x10 - Bad Response Error - 0x11 - Local Access Error - 0x12 - Remote Invalid Request Error - 0x13 - Remote Access Error - 0x14 - Remote Operation Error - 0x15 - Transport Retry Counter Exceeded - 0x16 - RNR Retry Counter Exceeded - 0x20 - Local RDD Violation Error - 0x21 - Remote Invalid RD Request - 0x22 - Remote Aborted Error - 0x23 - Invalid EE Context Number - 0x24 - Invalid EE Context State - other - Reserved - Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */ - pseudo_bit_t vendor_error_syndrome[0x00008]; - pseudo_bit_t wqe_counter[0x00010]; -/* -------------- */ - pseudo_bit_t opcode[0x00005]; /* The opcode of WQE completion is reported for. - - The following values are reported in case of completion with error: - 0xFE - For completion with error on Receive Queues - 0xFF - For completion with error on Send Queues */ - pseudo_bit_t reserved2[0x00001]; - pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ - pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ - pseudo_bit_t reserved3[0x00018]; -/* -------------- */ -}; - -/* Resize CQ Input Mailbox */ - -struct hermonprm_resize_cq_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - pseudo_bit_t reserved1[0x00006]; - pseudo_bit_t page_offset[0x00006]; - pseudo_bit_t reserved2[0x00014]; -/* -------------- */ - pseudo_bit_t reserved3[0x00018]; - pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */ - pseudo_bit_t reserved4[0x00003]; -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ - pseudo_bit_t mtt_base_addr_h[0x00008]; - pseudo_bit_t reserved6[0x00010]; - pseudo_bit_t log2_page_size[0x00006]; - pseudo_bit_t reserved7[0x00002]; -/* -------------- */ - pseudo_bit_t reserved8[0x00003]; - pseudo_bit_t mtt_base_addr_l[0x0001d]; -/* -------------- */ - pseudo_bit_t reserved9[0x00020]; -/* -------------- */ - pseudo_bit_t reserved10[0x00100]; -/* -------------- */ -}; - -/* MAD_IFC Input Modifier */ - -struct hermonprm_mad_ifc_input_modifier_st { /* Little Endian */ - pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */ - pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set. - Required for trap generation when BKey check is enabled and for global routed packets. */ - pseudo_bit_t reserved0[0x00007]; - pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. - This field is required for trap generation upon MKey/BKey validation. */ -/* -------------- */ -}; - -/* MAD_IFC Input Mailbox ###michal -gdror fixed */ - -struct hermonprm_mad_ifc_st { /* Little Endian */ - pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */ -/* -------------- */ - pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t reserved2[0x00008]; -/* -------------- */ - pseudo_bit_t reserved3[0x00010]; - pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t reserved4[0x00004]; - pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ -/* -------------- */ - pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD. - This field is reserved if Mad_extended_info indication in the input modifier is clear. */ - pseudo_bit_t reserved5[0x00010]; -/* -------------- */ - pseudo_bit_t reserved6[0x00160]; -/* -------------- */ - pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list. - Valid if Mad_extended_info bit (in the input modifier) and g bit are set. - Otherwise this field is reserved. */ -/* -------------- */ - pseudo_bit_t reserved7[0x004c0]; -/* -------------- */ -}; - -/* Query Debug Message #### michal - gdror fixed */ - -struct hermonprm_query_debug_msg_st { /* Little Endian */ - pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */ -/* -------------- */ - pseudo_bit_t v[0x00001]; /* Physical translation is valid */ - pseudo_bit_t reserved0[0x0000b]; - pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */ -/* -------------- */ - pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */ -/* -------------- */ - pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */ -/* -------------- */ - pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */ -/* -------------- */ - pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */ -/* -------------- */ - pseudo_bit_t reserved1[0x000c0]; -/* -------------- */ - pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */ -/* -------------- */ - pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */ -/* -------------- */ - pseudo_bit_t reserved2[0x00040]; -/* -------------- */ - pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */ -/* -------------- */ - pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */ -/* -------------- */ - pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */ -/* -------------- */ - pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */ -/* -------------- */ - pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */ -/* -------------- */ - pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */ -/* -------------- */ - pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */ -/* -------------- */ - pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */ -/* -------------- */ - pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */ -/* -------------- */ - pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */ -/* -------------- */ - pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */ -/* -------------- */ - pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */ -/* -------------- */ - pseudo_bit_t reserved3[0x00080]; -/* -------------- */ - pseudo_bit_t hw_buff_addr[0x00020]; /* Dror Mux Bohrer tracer */ -/* -------------- */ - pseudo_bit_t hw_buff_size[0x00020]; -/* -------------- */ - pseudo_bit_t reserved4[0x003c0]; -/* -------------- */ -}; - -/* User Access Region */ - -struct hermonprm_uar_st { /* Little Endian */ - struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */ -/* -------------- */ - struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ -/* -------------- */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - struct hermonprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */ -/* -------------- */ - pseudo_bit_t reserved1[0x03ec0]; -/* -------------- */ -}; - -/* Receive doorbell */ - -struct hermonprm_receive_doorbell_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t reserved2[0x00005]; - pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */ - pseudo_bit_t reserved3[0x00002]; - pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */ -/* -------------- */ -}; - -/* SET_IB Parameters */ - -struct hermonprm_set_ib_st { /* Little Endian */ - pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */ - pseudo_bit_t reserved0[0x00011]; - pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. - system_image_guid and sig must be the same for all ports. */ - pseudo_bit_t reserved1[0x0000d]; -/* -------------- */ - pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */ -/* -------------- */ - pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t reserved2[0x00180]; -/* -------------- */ -}; - -/* Multicast Group Member #### michal - gdror fixed */ - -struct hermonprm_mgm_entry_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00006]; - pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number. - The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables. - next_gid_index=0 means end of the chain. */ -/* -------------- */ - pseudo_bit_t reserved1[0x00060]; -/* -------------- */ - pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format. - Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ -/* -------------- */ - pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format. - Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ -/* -------------- */ - pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format. - Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ -/* -------------- */ - pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format. - Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ -/* -------------- */ - struct hermonprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */ -/* -------------- */ - struct hermonprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */ -/* -------------- */ - struct hermonprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */ -/* -------------- */ - struct hermonprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */ -/* -------------- */ - struct hermonprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */ -/* -------------- */ - struct hermonprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */ -/* -------------- */ - struct hermonprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */ -/* -------------- */ - struct hermonprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */ -/* -------------- */ -}; - -/* INIT_PORT Parameters #### michal - match PRM */ - -struct hermonprm_init_port_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00004]; - pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15. - Legal values are 1,2,4 and 8. */ - pseudo_bit_t port_width_cap[0x00004];/* IB Port Width - 1 - 1x - 3 - 1x, 4x - 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208) - else - Reserved */ - pseudo_bit_t reserved1[0x00004]; - pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */ - pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified. - node_guid and ng must be the same for all ports. */ - pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. - system_image_guid and sig must be the same for all ports. */ - pseudo_bit_t reserved2[0x0000d]; -/* -------------- */ - pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */ - pseudo_bit_t mtu[0x00010]; /* Maximum MTU Supported in bytes - must be: 256, 512, 1024, 2048 or 4096 - For Eth port, can be any - Field must not cross device capabilities as reported - */ -/* -------------- */ - pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port. - Must be the same for both ports. */ - pseudo_bit_t reserved3[0x00010]; -/* -------------- */ - pseudo_bit_t reserved4[0x00020]; -/* -------------- */ - pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */ -/* -------------- */ - pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */ -/* -------------- */ - pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set - Must be the same for both ports. */ -/* -------------- */ - pseudo_bit_t reserved5[0x006c0]; -/* -------------- */ -}; - -/* Query Device Capablities #### michal - gdror fixed */ - -struct hermonprm_query_dev_cap_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */ - pseudo_bit_t reserved1[0x00003]; - pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */ - pseudo_bit_t reserved2[0x00004]; - pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */ - pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */ -/* -------------- */ - pseudo_bit_t log_max_scqs[0x00004]; /* log base 2 of number of supported schedule queues */ - pseudo_bit_t reserved3[0x00004]; - pseudo_bit_t num_rsvd_scqs[0x00006]; - pseudo_bit_t reserved4[0x00002]; - pseudo_bit_t log_max_srqs[0x00005]; - pseudo_bit_t reserved5[0x00007]; - pseudo_bit_t log2_rsvd_srqs[0x00004]; -/* -------------- */ - pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */ - pseudo_bit_t reserved6[0x00003]; - pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */ - pseudo_bit_t reserved7[0x00004]; - pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */ - pseudo_bit_t reserved8[0x00008]; -/* -------------- */ - pseudo_bit_t log_max_eq[0x00004]; /* Log2 of the Maximum number of EQs */ - pseudo_bit_t reserved9[0x00004]; - pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use - The reserved resources are numbered from 0 to num_rsvd_eqs-1 - If 0 - no resources are reserved. */ - pseudo_bit_t reserved10[0x00004]; - pseudo_bit_t log_max_d_mpts[0x00006];/* Log (base 2) of the maximum number of data MPT entries (the number of Regions/Windows) */ - pseudo_bit_t reserved11[0x00002]; - pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */ -/* -------------- */ - pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */ - pseudo_bit_t reserved12[0x00002]; - pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */ - pseudo_bit_t reserved13[0x00004]; - pseudo_bit_t log_max_mrw_sz[0x00007];/* Log2 of the Maximum Size of Memory Region/Window. is it in PRM layout? */ - pseudo_bit_t reserved14[0x00005]; - pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use - The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1 - */ -/* -------------- */ - pseudo_bit_t reserved15[0x00020]; -/* -------------- */ - pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */ - pseudo_bit_t reserved16[0x0000a]; - pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */ - pseudo_bit_t reserved17[0x0000a]; -/* -------------- */ - pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */ - pseudo_bit_t reserved18[0x0001a]; -/* -------------- */ - pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */ - pseudo_bit_t reserved19[0x0001f]; -/* -------------- */ - pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */ - pseudo_bit_t max_vl_ib[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */ - pseudo_bit_t ib_port_width[0x00004];/* IB Port Width - 1 - 1x - 3 - 1x, 4x - 11 - 1x, 4x or 12x - else - Reserved */ - pseudo_bit_t ib_mtu[0x00004]; /* Maximum MTU Supported - 0x0 - Reserved - 0x1 - 256 - 0x2 - 512 - 0x3 - 1024 - 0x4 - 2048 - 0x5 - 4096 - 0x6-0xF Reserved */ - pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb. - The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */ - pseudo_bit_t port_type[0x00004]; /* Hermon New. bit per port. bit0 is first port. value '1' is ehternet. '0' is IB */ - pseudo_bit_t reserved20[0x00004]; - pseudo_bit_t w[0x00001]; /* Hermon New. 10GB eth support */ - pseudo_bit_t j[0x00001]; /* Hermon New. Jumbo frame support */ - pseudo_bit_t reserved21[0x00001]; -/* -------------- */ - pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */ - pseudo_bit_t reserved22[0x00004]; - pseudo_bit_t log_ethtype[0x00004]; /* Hermon New. log2 eth type table size */ - pseudo_bit_t reserved23[0x00004]; - pseudo_bit_t log_drain_size[0x00008];/* Log (base 2) of minimum size of the NoDropVLDrain buffer, specified in 4Kpages units */ - pseudo_bit_t log_max_msg[0x00005]; /* Log (base 2) of the maximum message size supported by the device */ - pseudo_bit_t reserved24[0x00003]; -/* -------------- */ - pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */ - pseudo_bit_t reserved25[0x0000c]; - pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported - bit 0 - full bw - bit 1 - 1/4 bw - bit 2 - 1/8 bw - bit 3 - 1/2 bw; */ -/* -------------- */ - pseudo_bit_t reserved26[0x00020]; -/* -------------- */ - pseudo_bit_t rc[0x00001]; /* RC Transport supported */ - pseudo_bit_t uc[0x00001]; /* UC Transport Supported */ - pseudo_bit_t ud[0x00001]; /* UD Transport Supported */ - pseudo_bit_t src[0x00001]; /* SRC Transport Supported. Hermon New instead of RD. */ - pseudo_bit_t rcm[0x00001]; /* Reliable Multicast support. Hermon New instead of IPv6 Transport Supported */ - pseudo_bit_t fcoib[0x00001]; /* Hermon New */ - pseudo_bit_t srq[0x00001]; /* SRQ is supported - */ - pseudo_bit_t checksum[0x00001]; /* IP over IB checksum is supported */ - pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */ - pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */ - pseudo_bit_t vmm[0x00001]; /* Hermon New */ - pseudo_bit_t fcoe[0x00001]; - pseudo_bit_t dpdp[0x00001]; /* Dual Port Different Protocols */ - pseudo_bit_t raw_ethertype[0x00001]; - pseudo_bit_t raw_ipv6[0x00001]; - pseudo_bit_t blh[0x00001]; - pseudo_bit_t mw[0x00001]; /* Memory windows supported */ - pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */ - pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */ - pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */ - pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */ - pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */ - pseudo_bit_t reserved28[0x00002]; - pseudo_bit_t pg[0x00001]; /* Paging on demand supported */ - pseudo_bit_t r[0x00001]; /* Router mode supported */ - pseudo_bit_t reserved29[0x00006]; -/* -------------- */ - pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2). - For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */ - pseudo_bit_t reserved30[0x00008]; - pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */ - pseudo_bit_t reserved31[0x00006]; - pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use - The reserved resources are numbered from 0 to num_reserved_uars-1 - Note that UAR number num_reserved_uars is always for the kernel. */ -/* -------------- */ - pseudo_bit_t log_max_bf_pages[0x00006];/* Maximum number of BlueFlame pages is 2^log_max_bf_pages */ - pseudo_bit_t reserved32[0x00002]; - pseudo_bit_t log_max_bf_regs_per_page[0x00006];/* Maximum number of BlueFlame registers per page is 2^log_max_bf_regs_per_page. It may be that only the beginning of a page contains BlueFlame registers. */ - pseudo_bit_t reserved33[0x00002]; - pseudo_bit_t log_bf_reg_size[0x00005];/* BlueFlame register size in bytes is 2^log_bf_reg_size */ - pseudo_bit_t reserved34[0x0000a]; - pseudo_bit_t bf[0x00001]; /* If set to "1" then BlueFlame may be used. */ -/* -------------- */ - pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */ - pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */ - pseudo_bit_t reserved35[0x00008]; -/* -------------- */ - pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */ - pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */ - pseudo_bit_t reserved36[0x00008]; -/* -------------- */ - pseudo_bit_t reserved37[0x00001]; - pseudo_bit_t fexch_base_mpt_31_25[0x00007];/* Hermon New. FC mpt base mpt number */ - pseudo_bit_t fcp_ud_base_23_8[0x00010];/* Hermon New. FC ud QP base QPN */ - pseudo_bit_t fexch_base_qp_23_16[0x00008];/* Hermon New. FC Exchange QP base QPN */ -/* -------------- */ - pseudo_bit_t reserved38[0x00020]; -/* -------------- */ - pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */ - pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT. - The reserved resources are numbered from 0 to num_reserved_mcgs-1 - If 0 - no resources are reserved. */ - pseudo_bit_t reserved39[0x00004]; - pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */ - pseudo_bit_t reserved40[0x00008]; -/* -------------- */ - pseudo_bit_t log_max_srcds[0x00004];/* Log2 of the maximum number of SRC Domains */ - pseudo_bit_t reserved41[0x00008]; - pseudo_bit_t num_rsvd_scrds[0x00004];/* The number of SRCDs reserved for firmware use - The reserved resources are numbered from 0 to num_reserved_rdds-1. - If 0 - no resources are reserved. */ - pseudo_bit_t log_max_pd[0x00005]; /* Log2 of the maximum number of PDs */ - pseudo_bit_t reserved42[0x00007]; - pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use - The reserved resources are numbered from 0 to num_reserved_pds-1 - If 0 - no resources are reserved. */ -/* -------------- */ - pseudo_bit_t reserved43[0x000c0]; -/* -------------- */ - pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device - For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ - pseudo_bit_t rdmardc_entry_sz[0x00010];/* RdmaRdC Entry Size for the device - For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ -/* -------------- */ - pseudo_bit_t altc_entry_sz[0x00010];/* Extended QPC entry size for the device - For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ - pseudo_bit_t aux_entry_sz[0x00010]; /* Auxilary context entry size */ -/* -------------- */ - pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device - For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ - pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device - For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ -/* -------------- */ - pseudo_bit_t c_mpt_entry_sz[0x00010];/* cMPT entry size in Bytes for the device. - For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ - pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device - For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ -/* -------------- */ - pseudo_bit_t d_mpt_entry_sz[0x00010];/* dMPT entry size in Bytes for the device. - For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ - pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device. - For the InfiniHost-III-EX MT25208 entry size is 8 bytes */ -/* -------------- */ - pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */ - pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism: - 0 - Type 2A - QP Number Association; or - 1 - Type 2B - QP Number and PD Association. */ - pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */ - pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. */ - pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */ - pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */ - pseudo_bit_t reserved44[0x0001a]; -/* -------------- */ - pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */ -/* -------------- */ - pseudo_bit_t reserved45[0x00020]; -/* -------------- */ - pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */ -/* -------------- */ - pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */ -/* -------------- */ - pseudo_bit_t reserved46[0x002c0]; -/* -------------- */ -}; - -/* QUERY_ADAPTER Parameters Block #### michal - gdror fixed */ - -struct hermonprm_query_adapter_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t reserved1[0x00018]; - pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */ -/* -------------- */ - pseudo_bit_t reserved2[0x00060]; -/* -------------- */ - struct hermonprm_vsd_st vsd; /* ###michal- this field was replaced by 2 fields : vsd .1664; vsd(continued/psid .128; */ -/* -------------- */ -}; - -/* QUERY_FW Parameters Block #### michal - doesn't match PRM */ - -struct hermonprm_query_fw_st { /* Little Endian */ - pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */ - pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */ -/* -------------- */ - pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */ - pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */ -/* -------------- */ - pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */ - pseudo_bit_t reserved0[0x00010]; -/* -------------- */ - pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */ - pseudo_bit_t reserved1[0x00017]; - pseudo_bit_t dt[0x00001]; /* Debug Trace Support - 0 - Debug trace is not supported - 1 - Debug trace is supported */ -/* -------------- */ - pseudo_bit_t reserved2[0x00001]; - pseudo_bit_t ccq[0x00001]; /* CCQ support */ - pseudo_bit_t reserved3[0x00006]; - pseudo_bit_t fw_seconds[0x00008]; /* FW timestamp - seconds. Dispalyed as Hexadecimal number */ - pseudo_bit_t fw_minutes[0x00008]; /* FW timestamp - minutes. Dispalyed as Hexadecimal number */ - pseudo_bit_t fw_hour[0x00008]; /* FW timestamp - hour. Dispalyed as Hexadecimal number */ -/* -------------- */ - pseudo_bit_t fw_day[0x00008]; /* FW timestamp - day. Dispalyed as Hexadecimal number */ - pseudo_bit_t fw_month[0x00008]; /* FW timestamp - month. Dispalyed as Hexadecimal number */ - pseudo_bit_t fw_year[0x00010]; /* FW timestamp - year. Dispalyed as Hexadecimal number (e.g. 0x2005) */ -/* -------------- */ - pseudo_bit_t reserved4[0x00040]; -/* -------------- */ - pseudo_bit_t clr_int_base_offset_h[0x00020];/* Bits [63:32] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ -/* -------------- */ - pseudo_bit_t clr_int_base_offset_l[0x00020];/* Bits [31:0] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ -/* -------------- */ - pseudo_bit_t reserved5[0x0001e]; - pseudo_bit_t clr_int_bar[0x00002]; /* PCI base address register (BAR) where clr_int register is located. - 00 - BAR 0-1 - 01 - BAR 2-3 - 10 - BAR 4-5 - 11 - Reserved - The PCI BARs of ConnectX are 64 bit BARs. - In ConnectX, clr_int register is located on BAR 0-1. */ -/* -------------- */ - pseudo_bit_t reserved6[0x00020]; -/* -------------- */ - pseudo_bit_t error_buf_offset_h[0x00020];/* Read Only buffer for catastrophic error reports (bits [63:32] of offset from error_buf_bar register in PCI address space.) */ -/* -------------- */ - pseudo_bit_t error_buf_offset_l[0x00020];/* Read Only buffer for catastrophic error reports (bits [31:0] of offset from error_buf_bar register in PCI address space.) */ -/* -------------- */ - pseudo_bit_t error_buf_size[0x00020];/* Size in words */ -/* -------------- */ - pseudo_bit_t reserved7[0x0001e]; - pseudo_bit_t error_buf_bar[0x00002];/* PCI base address register (BAR) where error_buf register is located. - 00 - BAR 0-1 - 01 - BAR 2-3 - 10 - BAR 4-5 - 11 - Reserved - The PCI BARs of ConnectX are 64 bit BARs. - In ConnectX, error_buf register is located on BAR 0-1. */ -/* -------------- */ - pseudo_bit_t reserved8[0x00600]; -/* -------------- */ -}; - -/* Memory Access Parameters for UD Address Vector Table */ - -struct hermonprm_udavtable_memory_parameters_st { /* Little Endian */ - pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */ -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */ - pseudo_bit_t reserved0[0x00005]; - pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */ - pseudo_bit_t reserved1[0x00002]; -/* -------------- */ -}; - -/* INIT_HCA & QUERY_HCA Parameters Block ####michal-doesn't match PRM (see differs below) new size in bytes:0x300 */ - -struct hermonprm_init_hca_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00018]; - pseudo_bit_t version[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x00040]; -/* -------------- */ - pseudo_bit_t reserved2[0x00010]; - pseudo_bit_t hca_core_clock[0x00010];/* Internal Clock freq in MHz */ -/* -------------- */ - pseudo_bit_t router_qp[0x00018]; /* QP number for router mode (8 LSBits should be 0). Low order 8 bits are taken from the TClass field of the incoming packet. - Valid only if RE bit is set */ - pseudo_bit_t reserved3[0x00005]; - pseudo_bit_t ipr2[0x00001]; /* Hermon New. IP router on port 2 */ - pseudo_bit_t ipr1[0x00001]; /* Hermon New. IP router on port 1 */ - pseudo_bit_t ibr[0x00001]; /* InfiniBand Router Mode */ -/* -------------- */ - pseudo_bit_t udp[0x00001]; /* UD Port Check Enable - 0 - Port field in Address Vector is ignored - 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */ - pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations - 0 - Host is Little Endian - 1 - Host is Big endian - */ - pseudo_bit_t reserved4[0x00001]; - pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */ - pseudo_bit_t reserved5[0x0001c]; -/* -------------- */ - pseudo_bit_t reserved6[0x00040]; -/* -------------- */ - struct hermonprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;/* ## michal - this field has chenged to - "qpc_cqc_eqc_parameters" - gdror, this is ok for now */ -/* -------------- */ - pseudo_bit_t reserved7[0x00100]; -/* -------------- */ - struct hermonprm_multicastparam_st multicast_parameters;/* ##michal- this field has chenged to - "IBUD/IPv6_multicast_parameters" - gdror - this is OK for now */ -/* -------------- */ - pseudo_bit_t reserved8[0x00080]; -/* -------------- */ - struct hermonprm_tptparams_st tpt_parameters; -/* -------------- */ - pseudo_bit_t reserved9[0x00080]; -/* -------------- */ - struct hermonprm_uar_params_st uar_parameters;/* UAR Parameters */ -/* -------------- */ - pseudo_bit_t reserved10[0x00600]; -/* -------------- */ -}; - -/* Event Queue Context Table Entry #### michal - gdror fixed */ - -struct hermonprm_eqc_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t st[0x00004]; /* Event delivery state machine - 0x9 - Armed - 0xA - Fired - 0xB - Always_Armed (auto-rearm) - other - reserved */ - pseudo_bit_t reserved1[0x00005]; - pseudo_bit_t oi[0x00001]; /* Oerrun ignore. - If set, HW will not check EQ full condition when writing new EQEs. */ - pseudo_bit_t ec[0x00001]; /* is set, all EQEs are written (coalesced) to first EQ entry */ - pseudo_bit_t reserved2[0x00009]; - pseudo_bit_t status[0x00004]; /* EQ status: - 0000 - OK - 1010 - EQ write failure - Valid for the QUERY_EQ and HW2SW_EQ commands only */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t reserved4[0x00005]; - pseudo_bit_t page_offset[0x00007]; /* offset bits[11:5] of first EQE in the EQ relative to the first page in memory region mapping this EQ */ - pseudo_bit_t reserved5[0x00014]; -/* -------------- */ - pseudo_bit_t reserved6[0x00018]; - pseudo_bit_t log_eq_size[0x00005]; /* Log (base 2) of the EQ size (in entries). Maximum EQ size is 2^22 EQEs (max log_eq_size is 22) */ - pseudo_bit_t reserved7[0x00003]; -/* -------------- */ - pseudo_bit_t eq_max_count[0x00010]; /* Event Generation Moderation counter */ - pseudo_bit_t eq_period[0x00010]; /* Event Generation moderation timed, microseconds */ -/* -------------- */ - pseudo_bit_t intr[0x0000a]; /* MSI-X table entry index to be used to signal interrupts on this EQ. Reserved if MSI-X are not enabled in the PCI configuration header. */ - pseudo_bit_t reserved8[0x00016]; -/* -------------- */ - pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] relative to INIT_HCA.mtt_base_addr */ - pseudo_bit_t reserved9[0x00010]; - pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ - pseudo_bit_t reserved10[0x00002]; -/* -------------- */ - pseudo_bit_t reserved11[0x00003]; - pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] relative to INIT_HCA.mtt_base_addr */ -/* -------------- */ - pseudo_bit_t reserved12[0x00040]; -/* -------------- */ - pseudo_bit_t consumer_counter[0x00018];/* Consumer counter. The counter is incremented for each EQE polled from the EQ. - Must be 0x0 in EQ initialization. - Maintained by HW (valid for the QUERY_EQ command only). */ - pseudo_bit_t reserved13[0x00008]; -/* -------------- */ - pseudo_bit_t producer_counter[0x00018];/* Producer Coutner. The counter is incremented for each EQE that is written by the HW to the EQ. - EQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a EQE needs to be added. - Maintained by HW (valid for the QUERY_EQ command only) */ - pseudo_bit_t reserved14[0x00008]; -/* -------------- */ - pseudo_bit_t reserved15[0x00080]; -/* -------------- */ -}; - -/* Memory Translation Table (MTT) Entry #### michal - match to PRM */ - -struct hermonprm_mtt_st { /* Little Endian */ - pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ -/* -------------- */ - pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */ - pseudo_bit_t reserved0[0x00002]; - pseudo_bit_t ptag_l[0x0001d]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ -/* -------------- */ -}; - -/* Memory Protection Table (MPT) Entry ### doesn't match PRM (new fields were added). new size in bytes : 0x54 */ - -struct hermonprm_mpt_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */ - pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation is performed for this region */ - pseudo_bit_t lr[0x00001]; /* If set - local read access is enabled. Must be set for all MPT Entries. */ - pseudo_bit_t lw[0x00001]; /* If set - local write access is enabled */ - pseudo_bit_t rr[0x00001]; /* If set - remote read access is enabled. */ - pseudo_bit_t rw[0x00001]; /* If set - remote write access is enabled */ - pseudo_bit_t atomic[0x00001]; /* If set - remote Atomic access is allowed. */ - pseudo_bit_t eb[0x00001]; /* If set - bind is enabled. Valid only for regions. */ - pseudo_bit_t atc_req[0x00001]; /* If set, second hop of address translation (PA to MA) to be performed in the device prior to issuing the uplink request. */ - pseudo_bit_t atc_xlated[0x00001]; /* If set, uplink cycle to be issues with “ATC_translated” indicator to force bypass of the chipset IOMMU. */ - pseudo_bit_t reserved1[0x00001]; - pseudo_bit_t no_snoop[0x00001]; /* If set, issue PCIe cycle with ûno Snoopÿ attribute - cycle not to be snooped in CPU caches */ - pseudo_bit_t reserved2[0x00008]; - pseudo_bit_t status[0x00004]; /* 0xF - Not Valid 0x3 - Free. else - HW ownership.Unbound Type1 windows are denoted by reg_wnd_len=0. Unbound Type II windows are denoted by Status = Free. */ -/* -------------- */ - pseudo_bit_t reserved3[0x00007]; - pseudo_bit_t bqp[0x00001]; /* 0 - not bound to qp (type 1 window, MR)1 - bound to qp (type 2 window) */ - pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */ -/* -------------- */ - pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. */ -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* Protection Domain. If VMM support is enabled PD[17:23] specify Guest VM Identifier */ - pseudo_bit_t en_rinv[0x00001]; /* Enable remote invalidation */ - pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. Must be set for type2 windows and non-shared physical memory regions. Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */ - pseudo_bit_t nce[0x00001]; /* Data can be cached in Network Cache (see ûNetwork Cacheÿ on page 81) */ - pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */ - pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail */ - pseudo_bit_t w_dif[0x00001]; /* Wire space contains dif */ - pseudo_bit_t m_dif[0x00001]; /* Memory space contains dif */ - pseudo_bit_t reserved4[0x00001]; -/* -------------- */ - pseudo_bit_t start_addr_h[0x00020]; /* Start Address - Virtual Address where this region/window starts */ -/* -------------- */ - pseudo_bit_t start_addr_l[0x00020]; /* Start Address - Virtual Address where this region/window starts */ -/* -------------- */ - pseudo_bit_t len_h[0x00020]; /* Region/Window Length */ -/* -------------- */ - pseudo_bit_t len_l[0x00020]; /* Region/Window Length */ -/* -------------- */ - pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */ -/* -------------- */ - pseudo_bit_t win_cnt[0x00018]; /* Number of windows bound to this region. Valid for regions only.The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */ - pseudo_bit_t reserved5[0x00008]; -/* -------------- */ - pseudo_bit_t mtt_rep[0x00004]; /* Log (base 2) of the number of time an MTT is replicated.E.g. for 64KB virtual blocks from 512B blocks, a replication factor of 2^7 is needed (MTT_REPLICATION_FACTOR=7).Up to 1MB of replicated block works */ - pseudo_bit_t reserved6[0x00011]; - pseudo_bit_t block_mode[0x00001]; /* If set, the page size is not power of two, and entity_size is in bytes. */ - pseudo_bit_t len64[0x00001]; /* Region/Window Length[64]. This bit added to enable registering 2^64 bytes per region */ - pseudo_bit_t fbo_en[0x00001]; /* If set, mtt_fbo field is valid, otherwise it is calculated from least significant bytes of the address. Must be set when mtt_rep is used or MPT is block-mode region */ - pseudo_bit_t reserved7[0x00008]; -/* -------------- */ - pseudo_bit_t mtt_adr_h[0x00008]; /* Offset to MTT list for this region. Must be aligned on 8 bytes. */ - pseudo_bit_t reserved8[0x00018]; -/* -------------- */ - pseudo_bit_t mtt_adr_l[0x00020]; /* Offset to MTT list for this region. Must be aligned on 8 bytes.###michal-relpaced with: RESERVED .3;mtt_adr_l .29; gdror - this is OK to leave it this way. */ -/* -------------- */ - pseudo_bit_t mtt_size[0x00020]; /* Number of MTT entries allocated for this MR.When Fast Registration Operations cannot be executed on this region (FRE bit is zero) this field is reserved.When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value cannot be zero. */ -/* -------------- */ - pseudo_bit_t entity_size[0x00015]; /* Page/block size. If MPT maps pages, the page size is 2entiry_size. If MPT maps blocks, the entity_size field specifies block size in bytes. The minimum amount of memory that can be mapped with single MTT is 512 bytes. */ - pseudo_bit_t reserved9[0x0000b]; -/* -------------- */ - pseudo_bit_t mtt_fbo[0x00015]; /* First byte offset in the zero-based region - the first byte within the first block/page start address refers to. When mtt_rep is being used, fbo points within the replicated block (i.e. block-size x 2^mtt_rep) */ - pseudo_bit_t reserved10[0x0000b]; -/* -------------- */ -}; - -/* Completion Queue Context Table Entry #### michal - match PRM */ - -struct hermonprm_completion_queue_context_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t st[0x00004]; /* Event delivery state machine - 0x0 - reserved - 0x9 - ARMED (Request for Notification) - 0x6 - ARMED SOLICITED (Request Solicited Notification) - 0xA - FIRED - other - reserved - - Must be 0x0 in CQ initialization. - Valid for the QUERY_CQ and HW2SW_CQ commands only. */ - pseudo_bit_t reserved1[0x00005]; - pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled. - When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */ - pseudo_bit_t cc[0x00001]; /* is set, all CQEs are written (coalesced) to first CQ entry */ - pseudo_bit_t reserved2[0x00009]; - pseudo_bit_t status[0x00004]; /* CQ status - 0000 - OK - 1001 - CQ overflow - 1010 - CQ write failure - Valid for the QUERY_CQ and HW2SW_CQ commands only */ -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t reserved4[0x00005]; - pseudo_bit_t page_offset[0x00007]; /* offset of first CQE in the CQ relative to the first page in memory region mapping this CQ */ - pseudo_bit_t reserved5[0x00014]; -/* -------------- */ - pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */ - pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries). - Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */ - pseudo_bit_t reserved6[0x00003]; -/* -------------- */ - pseudo_bit_t cq_max_count[0x00010]; /* Event Generation Moderation counter */ - pseudo_bit_t cq_period[0x00010]; /* Event Generation moderation timed, microseconds */ -/* -------------- */ - pseudo_bit_t c_eqn[0x00009]; /* Event Queue this CQ reports completion events to. - Valid values are 0 to 63 - If configured to value other than 0-63, completion events will not be reported on the CQ. */ - pseudo_bit_t reserved7[0x00017]; -/* -------------- */ - pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ - pseudo_bit_t reserved8[0x00010]; - pseudo_bit_t log2_page_size[0x00006]; - pseudo_bit_t reserved9[0x00002]; -/* -------------- */ - pseudo_bit_t reserved10[0x00003]; - pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ -/* -------------- */ - pseudo_bit_t last_notified_indx[0x00018];/* Maintained by HW. - Valid for QUERY_CQ and HW2SW_CQ commands only. */ - pseudo_bit_t reserved11[0x00008]; -/* -------------- */ - pseudo_bit_t solicit_producer_indx[0x00018];/* Maintained by HW. - Valid for QUERY_CQ and HW2SW_CQ commands only. - */ - pseudo_bit_t reserved12[0x00008]; -/* -------------- */ - pseudo_bit_t consumer_counter[0x00018];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ. - */ - pseudo_bit_t reserved13[0x00008]; -/* -------------- */ - pseudo_bit_t producer_counter[0x00018];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ. - CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added.. - Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */ - pseudo_bit_t reserved14[0x00008]; -/* -------------- */ - pseudo_bit_t reserved15[0x00020]; -/* -------------- */ - pseudo_bit_t reserved16[0x00020]; -/* -------------- */ - pseudo_bit_t db_record_addr_h[0x00020];/* CQ DB Record physical address [63:32] */ -/* -------------- */ - pseudo_bit_t reserved17[0x00003]; - pseudo_bit_t db_record_addr_l[0x0001d];/* CQ DB Record physical address [31:3] */ -/* -------------- */ -}; - -/* GPIO_event_data #### michal - gdror fixed */ - -struct hermonprm_gpio_event_data_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00060]; -/* -------------- */ - pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ -/* -------------- */ - pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ -}; - -/* Event_data Field - QP/EE Events #### michal - doesn't match PRM */ - -struct hermonprm_qp_ee_event_st { /* Little Endian */ - pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for ###michal - field changed to QP number */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t reserved2[0x0001c]; - pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field - Not valid on SRQ events ###michal - field replaced with RESERVED */ - pseudo_bit_t reserved3[0x00003]; -/* -------------- */ - pseudo_bit_t reserved4[0x00060]; -/* -------------- */ -}; - -/* InfiniHost-III-EX Type0 Configuration Header ####michal - doesn't match PRM (new fields added, see below) */ - -struct hermonprm_mt25208_type0_st { /* Little Endian */ - pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */ - pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode - 25408 (decimal) - InfiniHost-III EX mode (the mode described in this manual) - 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode - */ -/* -------------- */ - pseudo_bit_t command[0x00010]; /* PCI Command Register */ - pseudo_bit_t status[0x00010]; /* PCI Status Register */ -/* -------------- */ - pseudo_bit_t revision_id[0x00008]; - pseudo_bit_t class_code_hca_class_code[0x00018]; -/* -------------- */ - pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */ - pseudo_bit_t latency_timer[0x00008]; - pseudo_bit_t header_type[0x00008]; /* hardwired to zero */ - pseudo_bit_t bist[0x00008]; -/* -------------- */ - pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */ - pseudo_bit_t reserved0[0x00010]; - pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */ -/* -------------- */ - pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */ -/* -------------- */ - pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */ - pseudo_bit_t reserved1[0x00010]; - pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */ -/* -------------- */ - pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */ -/* -------------- */ - pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */ - pseudo_bit_t reserved2[0x00010]; - pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ -/* -------------- */ - pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ -/* -------------- */ - pseudo_bit_t cardbus_cis_pointer[0x00020]; -/* -------------- */ - pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */ - pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */ -/* -------------- */ - pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ - pseudo_bit_t reserved3[0x0000a]; - pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ -/* -------------- */ - pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */ - pseudo_bit_t reserved4[0x00018]; -/* -------------- */ - pseudo_bit_t reserved5[0x00020]; -/* -------------- */ - pseudo_bit_t interrupt_line[0x00008]; - pseudo_bit_t interrupt_pin[0x00008]; - pseudo_bit_t min_gnt[0x00008]; - pseudo_bit_t max_latency[0x00008]; -/* -------------- */ - pseudo_bit_t reserved6[0x00100]; -/* -------------- */ - pseudo_bit_t msi_cap_id[0x00008]; - pseudo_bit_t msi_next_cap_ptr[0x00008]; - pseudo_bit_t msi_en[0x00001]; - pseudo_bit_t multiple_msg_cap[0x00003]; - pseudo_bit_t multiple_msg_en[0x00003]; - pseudo_bit_t cap_64_bit_addr[0x00001]; - pseudo_bit_t reserved7[0x00008]; -/* -------------- */ - pseudo_bit_t msg_addr_l[0x00020]; -/* -------------- */ - pseudo_bit_t msg_addr_h[0x00020]; -/* -------------- */ - pseudo_bit_t msg_data[0x00010]; - pseudo_bit_t reserved8[0x00010]; -/* -------------- */ - pseudo_bit_t reserved9[0x00080]; -/* -------------- */ - pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */ - pseudo_bit_t pm_next_cap_ptr[0x00008]; - pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h - [3] PME clock - 0h - [4] RsvP - [5] Device specific initialization - 0h - [8:6] AUX current - 0h - [9] D1 support - 0h - [10] D2 support - 0h - [15:11] PME support - 0h */ -/* -------------- */ - pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */ - pseudo_bit_t pm_control_status_brdg_ext[0x00008]; - pseudo_bit_t data[0x00008]; -/* -------------- */ - pseudo_bit_t reserved10[0x00040]; -/* -------------- */ - pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */ - pseudo_bit_t vpd_next_cap_id[0x00008]; - pseudo_bit_t vpd_address[0x0000f]; - pseudo_bit_t f[0x00001]; -/* -------------- */ - pseudo_bit_t vpd_data[0x00020]; -/* -------------- */ - pseudo_bit_t reserved11[0x00040]; -/* -------------- */ - pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */ - pseudo_bit_t pciex_next_cap_ptr[0x00008]; - pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h - [7:4] Device/Port Type - 0h - [8] Slot implemented - 0h - [13:9] Interrupt message number - */ -/* -------------- */ - pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h - [4:3] Phantom Function supported - 0h - [5] Extended Tag Filed supported - 0h - [8:6] Endpoint L0s Acceptable Latency - TBD - [11:9] Endpoint L1 Acceptable Latency - TBD - [12] Attention Button Present - configured through InfiniBurn - [13] Attention Indicator Present - configured through InfiniBurn - [14] Power Indicator Present - configured through InfiniBurn - [25:18] Captured Slot Power Limit Value - [27:26] Captured Slot Power Limit Scale */ -/* -------------- */ - pseudo_bit_t device_control[0x00010]; - pseudo_bit_t device_status[0x00010]; -/* -------------- */ - pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h - [9:4] Maximum Link Width - 8h - [11:10] Active State Power Management Support - 3h - [14:12] L0s Exit Latency - TBD - [17:15] L1 Exit Latency - TBD - [31:24] Port Number - 0h */ -/* -------------- */ - pseudo_bit_t link_control[0x00010]; - pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h - [9:4] Negotiated Link Width - [12] Slot clock configuration - 1h */ -/* -------------- */ - pseudo_bit_t reserved12[0x00260]; -/* -------------- */ - pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */ - pseudo_bit_t capability_version[0x00004];/* 1h */ - pseudo_bit_t next_capability_offset[0x0000c];/* 0h */ -/* -------------- */ - pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status - 4 Data Link Protocol Error Status - 12 Poisoned TLP Status - 13 Flow Control Protocol Error Status - 14 Completion Timeout Status - 15 Completer Abort Status - 16 Unexpected Completion Status - 17 Receiver Overflow Status - 18 Malformed TLP Status - 19 ECRC Error Status - 20 Unsupported Request Error Status */ -/* -------------- */ - pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask - 4 Data Link Protocol Error Mask - 12 Poisoned TLP Mask - 13 Flow Control Protocol Error Mask - 14 Completion Timeout Mask - 15 Completer Abort Mask - 16 Unexpected Completion Mask - 17 Receiver Overflow Mask - 18 Malformed TLP Mask - 19 ECRC Error Mask - 20 Unsupported Request Error Mask */ -/* -------------- */ - pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity - 4 Data Link Protocol Error Severity - 12 Poisoned TLP Severity - 13 Flow Control Protocol Error Severity - 14 Completion Timeout Severity - 15 Completer Abort Severity - 16 Unexpected Completion Severity - 17 Receiver Overflow Severity - 18 Malformed TLP Severity - 19 ECRC Error Severity - 20 Unsupported Request Error Severity */ -/* -------------- */ - pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status - 6 Bad TLP Status - 7 Bad DLLP Status - 8 REPLAY_NUM Rollover Status - 12 Replay Timer Timeout Status */ -/* -------------- */ - pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask - 6 Bad TLP Mask - 7 Bad DLLP Mask - 8 REPLAY_NUM Rollover Mask - 12 Replay Timer Timeout Mask */ -/* -------------- */ - pseudo_bit_t advance_error_capabilities_and_control_register[0x00020]; -/* -------------- */ - struct hermonprm_header_log_register_st header_log_register; -/* -------------- */ - pseudo_bit_t reserved13[0x006a0]; -/* -------------- */ -}; - -/* Event Data Field - Performance Monitor */ - -struct hermonprm_performance_monitor_event_st { /* Little Endian */ - struct hermonprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */ -/* -------------- */ - pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC - 0x02 - RQPC - 0x03 - CQC - 0x04 - Rkey - 0x05 - TLB - 0x06 - port0 - 0x07 - port1 */ - pseudo_bit_t reserved0[0x00018]; -/* -------------- */ - pseudo_bit_t reserved1[0x00040]; -/* -------------- */ -}; - -/* Event_data Field - Page Faults */ - -struct hermonprm_page_fault_event_data_st { /* Little Endian */ - pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ -/* -------------- */ - pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ -/* -------------- */ - pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */ -/* -------------- */ - pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */ - pseudo_bit_t reserved0[0x00003]; - pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */ - pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */ - pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */ - pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */ - pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */ -/* -------------- */ - pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */ -/* -------------- */ -}; - -/* WQE segments format */ - -struct hermonprm_wqe_segment_st { /* Little Endian */ - struct hermonprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */ -/* -------------- */ - pseudo_bit_t reserved0[0x00280]; -/* -------------- */ - struct hermonprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */ -/* -------------- */ - pseudo_bit_t reserved1[0x00100]; -/* -------------- */ - pseudo_bit_t recv_wqe_segment_ctrl[4][0x00020];/* Receive segment format */ -/* -------------- */ - pseudo_bit_t reserved2[0x00080]; -/* -------------- */ -}; - -/* Event_data Field - Port State Change #### michal - match PRM */ - -struct hermonprm_port_state_change_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00040]; -/* -------------- */ - pseudo_bit_t reserved1[0x0001c]; - pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */ - pseudo_bit_t reserved2[0x00002]; -/* -------------- */ - pseudo_bit_t reserved3[0x00060]; -/* -------------- */ -}; - -/* Event_data Field - Completion Queue Error #### michal - match PRM */ - -struct hermonprm_completion_queue_error_st { /* Little Endian */ - pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x00020]; -/* -------------- */ - pseudo_bit_t syndrome[0x00008]; /* Error syndrome - 0x01 - CQ overrun - 0x02 - CQ access violation error */ - pseudo_bit_t reserved2[0x00018]; -/* -------------- */ - pseudo_bit_t reserved3[0x00060]; -/* -------------- */ -}; - -/* Event_data Field - Completion Event #### michal - match PRM */ - -struct hermonprm_completion_event_st { /* Little Endian */ - pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t reserved1[0x000a0]; -/* -------------- */ -}; - -/* Event Queue Entry #### michal - match to PRM */ - -struct hermonprm_event_queue_entry_st { /* Little Endian */ - pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type. - Defined for events which have sub types, zero elsewhere. */ - pseudo_bit_t reserved0[0x00008]; - pseudo_bit_t event_type[0x00008]; /* Event Type */ - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */ -/* -------------- */ - pseudo_bit_t reserved2[0x00007]; - pseudo_bit_t owner[0x00001]; /* Owner of the entry - 0 SW - 1 HW */ - pseudo_bit_t reserved3[0x00018]; -/* -------------- */ -}; - -/* QP/EE State Transitions Command Parameters ###michal - doesn't match PRM (field name changed) */ - -struct hermonprm_qp_ee_state_transitions_st { /* Little Endian */ - pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */ -/* -------------- */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - struct hermonprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data ###michal - field has replaced with "qpc_data" (size .1948) */ -/* -------------- */ - pseudo_bit_t reserved1[0x00800]; -/* -------------- */ -}; - -/* Completion Queue Entry Format #### michal - fixed by gdror */ - -struct hermonprm_completion_queue_entry_st { /* Little Endian */ - pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ - pseudo_bit_t reserved0[0x00002]; - pseudo_bit_t d2s[0x00001]; /* Duplicate to Sniffer. This bit is set if both Send and Receive queues are subject for sniffer queue. The HW delivers - packet only to send-associated sniffer receive queue. */ - pseudo_bit_t fcrc_sd[0x00001]; /* FCRC: If set, FC CRC is correct in FC frame encapsulated in payload. Valid for Raw Frame FC receive queue only. - SD: CQ associated with Sniffer receive queue. If set, packets were skipped due to lack of receive buffers on the Sniffer receive queue */ - pseudo_bit_t fl[0x00001]; /* Force Loopback Valid for responder RawEth and UD only. */ - pseudo_bit_t vlan[0x00002]; /* Valid for RawEth and UD over Ethernet only. Applicable for RawEth and UD over Ethernet Receive queue - 00 - No VLAN header was present in the packet - 01 - C-VLAN (802.1q) Header was present in the frame. - 10 - S-VLAN (802.1ad) Header was present in the frame. */ - pseudo_bit_t dife[0x00001]; /* DIF Error */ -/* -------------- */ - pseudo_bit_t immediate_rssvalue_invalidatekey[0x00020];/* For a responder CQE, if completed WQE Opcode is Send With Immediate or Write With Immediate, this field contains immediate field of the received message. - For a responder CQE, if completed WQE Opcode is Send With Invalidate, this field contains the R_key that was invalidated. - For a responder CQE of a GSI packet this filed contains the Pkey Index of the packet. - For IPoIB (UD) and RawEth CQEs this field contains the RSS hash function value. - Otherwise, this field is reserved. */ -/* -------------- */ - pseudo_bit_t srq_rqpn[0x00018]; /* For Responder UD QPs, Remote (source) QP number. - For Responder SRC QPs, SRQ number. - Otherwise, this field is reserved. */ - pseudo_bit_t ml_path_mac_index[0x00007];/* For responder UD over IB CQE: These are the lower LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. Invalid if incoming message DLID is the permissive LID or incoming message is multicast. - For responder UD over Ethernet and RawEth CQEs: Index of the MAC Table entry that the packet DMAC was matched against. - Otherwise, this field is reserved. */ - pseudo_bit_t g[0x00001]; /* For responder UD over IB CQE this bit indicates the presence of a GRH - For responder UD over Ethernet CQE this bit is set if IPv6 L3 header was present in the packet, this bit is cleared if IPv4 L3 Header was present in the packet. - Otherwise, this field is reserved. */ -/* -------------- */ - pseudo_bit_t slid_smac47_32[0x00010];/* For responder UD over IB CQE it is the source LID of the packet. - For responder UD over Ethernet and RawEth CQEs it is the source-MAC[47:32] of the packet. - Otherwise, this field is reserved. */ - pseudo_bit_t vid[0x0000c]; /* Frame VID, valid for Responder Raw Ethernet and UD over Ethernet QP. Otherwise, this field is reserved. */ - pseudo_bit_t sl[0x00004]; /* For responder UD over IB - the Service Level of the packet. - For responder UD over Ethernet and RawEth - it is VLAN-header[15:12] - Otherwise, this field is reserved. */ -/* -------------- */ - pseudo_bit_t smac31_0_rawether_ipoib_status[0x00020];/* For responder UD over Ethernet - source MAC[31:0] of the packet. - For responder RawEth and UD over IB - RawEth-IPoIB status {3 reserved, ipok,udp,tcp,ipv4opt,ipv6,ipv4vf,ipv4,rht(6),ipv6extmask(6),reserved(2),l2am,reserved(2),bfcs,reserved(2),enc} - Otherwise, this field is reserved. */ -/* -------------- */ - pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data transferred. Applicable for RDMA-read, Atomic and all receive operations. completions. - For Receive Queue that is subject for headers. separation, byte_cnt[31:24] specify number of bytes scattered to the first scatter entry (headers. length). Byte_cnt[23:0] specify total byte count received (including headers). */ -/* -------------- */ - pseudo_bit_t checksum[0x00010]; /* Valid for RawEth and IPoIB only. */ - pseudo_bit_t wqe_counter[0x00010]; -/* -------------- */ - pseudo_bit_t opcode[0x00005]; /* Send completions - same encoding as WQE. - Error coding is 0x1F - Receive: - 0x0 - RDMA-Write with Immediate - 0x1 - Send - 0x2 - Send with Immediate - 0x3 - Send & Invalidate - */ - pseudo_bit_t is[0x00001]; /* inline scatter */ - pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ - pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ - pseudo_bit_t reserved1[0x00010]; - pseudo_bit_t reserved2[0x00008]; -/* -------------- */ -}; - -/* */ - -struct hermonprm_mcg_qps_st { /* Little Endian */ - struct hermonprm_mcg_qp_dw_st dw[128]; -/* -------------- */ -}; - -/* */ - -struct hermonprm_mcg_hdr_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00006]; - pseudo_bit_t next_mcg[0x0001a]; -/* -------------- */ - pseudo_bit_t members_count[0x00018]; - pseudo_bit_t reserved1[0x00008]; -/* -------------- */ - pseudo_bit_t reserved2[0x00020]; -/* -------------- */ - pseudo_bit_t reserved3[0x00020]; -/* -------------- */ - pseudo_bit_t gid3[0x00020]; -/* -------------- */ - pseudo_bit_t gid2[0x00020]; -/* -------------- */ - pseudo_bit_t gid1[0x00020]; -/* -------------- */ - pseudo_bit_t gid0[0x00020]; -/* -------------- */ -}; - -/* */ - -struct hermonprm_sched_queue_context_st { /* Little Endian */ - pseudo_bit_t policy[0x00003]; /* Schedule Queue Policy - 0 - LLSQ, 1 - GBSQ, 2 - BESQ */ - pseudo_bit_t vl15[0x00001]; - pseudo_bit_t sl[0x00004]; /* SL this Schedule Queue is associated with (if vl15 bit is 0) */ - pseudo_bit_t port[0x00002]; /* Port this Schedule Queue is associated with */ - pseudo_bit_t reserved0[0x00006]; - pseudo_bit_t weight[0x00010]; /* Weight of this SchQ */ -/* -------------- */ -}; - -/* */ - -struct hermonprm_ecc_detect_event_data_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t cause_lsb[0x00001]; - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t cause_msb[0x00001]; - pseudo_bit_t reserved2[0x00002]; - pseudo_bit_t err_rmw[0x00001]; - pseudo_bit_t err_src_id[0x00003]; - pseudo_bit_t err_da[0x00002]; - pseudo_bit_t err_ba[0x00002]; - pseudo_bit_t reserved3[0x00011]; - pseudo_bit_t overflow[0x00001]; -/* -------------- */ - pseudo_bit_t err_ra[0x00010]; - pseudo_bit_t err_ca[0x00010]; -/* -------------- */ -}; - -/* Event_data Field - ECC Detection Event */ - -struct hermonprm_scrubbing_event_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00080]; -/* -------------- */ - pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause: - single ECC error in the 64bit lsb data, on the rise edge of the clock */ - pseudo_bit_t reserved1[0x00002]; - pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause: - single ECC error in the 64bit msb data, on the fall edge of the clock */ - pseudo_bit_t reserved2[0x00002]; - pseudo_bit_t err_rmw[0x00001]; /* transaction type: - 0 - read - 1 - read/modify/write */ - pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */ - pseudo_bit_t err_da[0x00002]; /* Error DIMM address */ - pseudo_bit_t err_ba[0x00002]; /* Error bank address */ - pseudo_bit_t reserved3[0x00011]; - pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */ -/* -------------- */ - pseudo_bit_t err_ra[0x00010]; /* Error row address */ - pseudo_bit_t err_ca[0x00010]; /* Error column address */ -/* -------------- */ -}; - -/* */ - -struct hermonprm_eq_cmd_doorbell_st { /* Little Endian */ - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ -}; - -/* 0 */ - -struct hermonprm_hermon_prm_st { /* Little Endian */ - struct hermonprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */ -/* -------------- */ - pseudo_bit_t reserved0[0x7ff00]; -/* -------------- */ - struct hermonprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */ -/* -------------- */ - pseudo_bit_t reserved1[0x7f000]; -/* -------------- */ - struct hermonprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */ -/* -------------- */ - pseudo_bit_t reserved2[0x7ff00]; -/* -------------- */ - struct hermonprm_completion_event_st completion_event;/* Event_data Field - Completion Event */ -/* -------------- */ - pseudo_bit_t reserved3[0x7ff40]; -/* -------------- */ - struct hermonprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */ -/* -------------- */ - pseudo_bit_t reserved4[0x7ff40]; -/* -------------- */ - struct hermonprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */ -/* -------------- */ - pseudo_bit_t reserved5[0x7ff40]; -/* -------------- */ - struct hermonprm_wqe_segment_st wqe_segment;/* WQE segments format */ -/* -------------- */ - pseudo_bit_t reserved6[0x7f000]; -/* -------------- */ - struct hermonprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */ -/* -------------- */ - pseudo_bit_t reserved7[0x7ff40]; -/* -------------- */ - struct hermonprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */ -/* -------------- */ - pseudo_bit_t reserved8[0xfff20]; -/* -------------- */ - struct hermonprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */ -/* -------------- */ - pseudo_bit_t reserved9[0x7f000]; -/* -------------- */ - struct hermonprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */ -/* -------------- */ - pseudo_bit_t reserved10[0x00040]; -/* -------------- */ - struct hermonprm_gpio_event_data_st gpio_event_data; -/* -------------- */ - pseudo_bit_t reserved11[0x7fe40]; -/* -------------- */ - struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ -/* -------------- */ - pseudo_bit_t reserved12[0x7ff00]; -/* -------------- */ - struct hermonprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */ -/* -------------- */ - pseudo_bit_t reserved13[0x7f840]; -/* -------------- */ - struct hermonprm_address_path_st address_path;/* Address Path */ -/* -------------- */ - pseudo_bit_t reserved14[0x7fea0]; -/* -------------- */ - struct hermonprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */ -/* -------------- */ - pseudo_bit_t reserved15[0x7fe00]; -/* -------------- */ - struct hermonprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */ -/* -------------- */ - pseudo_bit_t reserved16[0x7fe00]; -/* -------------- */ - struct hermonprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */ -/* -------------- */ - pseudo_bit_t reserved17[0x7ffc0]; -/* -------------- */ - struct hermonprm_eqc_st eqc; /* Event Queue Context Table Entry */ -/* -------------- */ - pseudo_bit_t reserved18[0x7fe00]; -/* -------------- */ - struct hermonprm_performance_monitors_st performance_monitors;/* Performance Monitors */ -/* -------------- */ - pseudo_bit_t reserved19[0x7ff80]; -/* -------------- */ - struct hermonprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */ -/* -------------- */ - pseudo_bit_t reserved20[0xfff20]; -/* -------------- */ - struct hermonprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */ -/* -------------- */ - pseudo_bit_t reserved21[0x7f000]; -/* -------------- */ - struct hermonprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */ -/* -------------- */ - pseudo_bit_t reserved22[0x7fc00]; -/* -------------- */ - struct hermonprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */ -/* -------------- */ - pseudo_bit_t reserved23[0x7ffc0]; -/* -------------- */ - struct hermonprm_multicastparam_st multicastparam;/* Multicast Support Parameters */ -/* -------------- */ - pseudo_bit_t reserved24[0x7ff00]; -/* -------------- */ - struct hermonprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */ -/* -------------- */ - pseudo_bit_t reserved25[0x7ff00]; -/* -------------- */ - pseudo_bit_t reserved26[0x00800]; -/* -------------- */ - pseudo_bit_t reserved27[0x00100]; -/* -------------- */ - pseudo_bit_t reserved28[0x7f700]; -/* -------------- */ - pseudo_bit_t reserved29[0x00100]; -/* -------------- */ - pseudo_bit_t reserved30[0x7ff00]; -/* -------------- */ - struct hermonprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */ -/* -------------- */ - pseudo_bit_t reserved31[0x7f800]; -/* -------------- */ - struct hermonprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */ -/* -------------- */ - pseudo_bit_t reserved32[0x7f800]; -/* -------------- */ - struct hermonprm_query_dev_cap_st query_dev_cap;/* Query Device Limitations */ -/* -------------- */ - pseudo_bit_t reserved33[0x7f800]; -/* -------------- */ - struct hermonprm_uar_params_st uar_params;/* UAR Parameters */ -/* -------------- */ - pseudo_bit_t reserved34[0x7ff00]; -/* -------------- */ - struct hermonprm_init_port_st init_port;/* INIT_PORT Parameters */ -/* -------------- */ - pseudo_bit_t reserved35[0x7f800]; -/* -------------- */ - struct hermonprm_mgm_entry_st mgm_entry;/* Multicast Group Member */ -/* -------------- */ - pseudo_bit_t reserved36[0x7fe00]; -/* -------------- */ - struct hermonprm_set_ib_st set_ib; /* SET_IB Parameters */ -/* -------------- */ - pseudo_bit_t reserved37[0x7fe00]; -/* -------------- */ - struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */ -/* -------------- */ - pseudo_bit_t reserved38[0x7ff80]; -/* -------------- */ - struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ -/* -------------- */ - pseudo_bit_t reserved39[0x7ffc0]; -/* -------------- */ - struct hermonprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */ -/* -------------- */ - pseudo_bit_t reserved40[0x7ffc0]; -/* -------------- */ - struct hermonprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */ -/* -------------- */ - pseudo_bit_t reserved41[0xfffc0]; -/* -------------- */ - struct hermonprm_uar_st uar; /* User Access Region */ -/* -------------- */ - pseudo_bit_t reserved42[0x7c000]; -/* -------------- */ - struct hermonprm_mgmqp_st mgmqp; /* Multicast Group Member QP */ -/* -------------- */ - pseudo_bit_t reserved43[0x7ffe0]; -/* -------------- */ - struct hermonprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */ -/* -------------- */ - pseudo_bit_t reserved44[0x7f800]; -/* -------------- */ - struct hermonprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */ -/* -------------- */ - pseudo_bit_t reserved45[0x00900]; -/* -------------- */ - struct hermonprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */ -/* -------------- */ - pseudo_bit_t reserved46[0x7e6e0]; -/* -------------- */ - struct hermonprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */ -/* -------------- */ - pseudo_bit_t reserved47[0x7fe00]; -/* -------------- */ - struct hermonprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */ -/* -------------- */ - pseudo_bit_t reserved48[0x7ff00]; -/* -------------- */ - struct hermonprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */ -/* -------------- */ - pseudo_bit_t reserved49[0x7ff40]; -/* -------------- */ - struct hermonprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */ -/* -------------- */ - pseudo_bit_t reserved50[0x7f000]; -/* -------------- */ - struct hermonprm_performance_counters_st performance_counters;/* Performance Counters */ -/* -------------- */ - pseudo_bit_t reserved51[0x9ff800]; -/* -------------- */ - struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ -/* -------------- */ - pseudo_bit_t reserved52[0x7ff00]; -/* -------------- */ - struct hermonprm_pbl_st pbl; /* Physical Buffer List */ -/* -------------- */ - pseudo_bit_t reserved53[0x7ff00]; -/* -------------- */ - struct hermonprm_srq_context_st srq_context;/* SRQ Context */ -/* -------------- */ - pseudo_bit_t reserved54[0x7fe80]; -/* -------------- */ - struct hermonprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */ -/* -------------- */ - pseudo_bit_t reserved55[0x7f800]; -/* -------------- */ - struct hermonprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */ -/* -------------- */ - pseudo_bit_t reserved56[0x7ff80]; -/* -------------- */ - struct hermonprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */ -/* -------------- */ - pseudo_bit_t reserved57[0x7ffc0]; -/* -------------- */ - struct hermonprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */ -/* -------------- */ - pseudo_bit_t reserved58[0x7ffc0]; -/* -------------- */ - struct hermonprm_qp_db_record_st qp_db_record;/* QP_DB_Record */ -/* -------------- */ - pseudo_bit_t reserved59[0x00020]; -/* -------------- */ - pseudo_bit_t reserved60[0x1fffc0]; -/* -------------- */ - struct hermonprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */ -/* -------------- */ - struct hermonprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */ -/* -------------- */ - pseudo_bit_t reserved61[0x01000]; -/* -------------- */ - pseudo_bit_t reserved62[0x00040]; -/* -------------- */ - pseudo_bit_t reserved63[0x00fc0]; -/* -------------- */ - struct hermonprm_clr_int_st clr_int; /* Clear Interrupt Register */ -/* -------------- */ - pseudo_bit_t reserved64[0xffcfc0]; -/* -------------- */ -}; -#endif /* H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H */ diff --git a/gpxe/src/drivers/infiniband/arbel.c b/gpxe/src/drivers/infiniband/arbel.c deleted file mode 100644 index 5bf35743..00000000 --- a/gpxe/src/drivers/infiniband/arbel.c +++ /dev/null @@ -1,2247 +0,0 @@ -/* - * Copyright (C) 2007 Michael Brown <mbrown@fensystems.co.uk>. - * - * Based in part upon the original driver by Mellanox Technologies - * Ltd. Portions may be Copyright (c) Mellanox Technologies Ltd. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -FILE_LICENCE ( GPL2_OR_LATER ); - -#include <stdint.h> -#include <stdlib.h> -#include <stdio.h> -#include <string.h> -#include <strings.h> -#include <unistd.h> -#include <errno.h> -#include <byteswap.h> -#include <gpxe/io.h> -#include <gpxe/pci.h> -#include <gpxe/malloc.h> -#include <gpxe/umalloc.h> -#include <gpxe/iobuf.h> -#include <gpxe/netdevice.h> -#include <gpxe/infiniband.h> -#include <gpxe/ib_smc.h> -#include "arbel.h" - -/** - * @file - * - * Mellanox Arbel Infiniband HCA - * - */ - -/*************************************************************************** - * - * Queue number allocation - * - *************************************************************************** - */ - -/** - * Allocate queue number - * - * @v q_inuse Queue usage bitmask - * @v max_inuse Maximum number of in-use queues - * @ret qn_offset Free queue number offset, or negative error - */ -static int arbel_alloc_qn_offset ( arbel_bitmask_t *q_inuse, - unsigned int max_inuse ) { - unsigned int qn_offset = 0; - arbel_bitmask_t mask = 1; - - while ( qn_offset < max_inuse ) { - if ( ( mask & *q_inuse ) == 0 ) { - *q_inuse |= mask; - return qn_offset; - } - qn_offset++; - mask <<= 1; - if ( ! mask ) { - mask = 1; - q_inuse++; - } - } - return -ENFILE; -} - -/** - * Free queue number - * - * @v q_inuse Queue usage bitmask - * @v qn_offset Queue number offset - */ -static void arbel_free_qn_offset ( arbel_bitmask_t *q_inuse, int qn_offset ) { - arbel_bitmask_t mask; - - mask = ( 1 << ( qn_offset % ( 8 * sizeof ( mask ) ) ) ); - q_inuse += ( qn_offset / ( 8 * sizeof ( mask ) ) ); - *q_inuse &= ~mask; -} - -/*************************************************************************** - * - * HCA commands - * - *************************************************************************** - */ - -/** - * Wait for Arbel command completion - * - * @v arbel Arbel device - * @ret rc Return status code - */ -static int arbel_cmd_wait ( struct arbel *arbel, - struct arbelprm_hca_command_register *hcr ) { - unsigned int wait; - - for ( wait = ARBEL_HCR_MAX_WAIT_MS ; wait ; wait-- ) { - hcr->u.dwords[6] = - readl ( arbel->config + ARBEL_HCR_REG ( 6 ) ); - if ( MLX_GET ( hcr, go ) == 0 ) - return 0; - mdelay ( 1 ); - } - return -EBUSY; -} - -/** - * Issue HCA command - * - * @v arbel Arbel device - * @v command Command opcode, flags and input/output lengths - * @v op_mod Opcode modifier (0 if no modifier applicable) - * @v in Input parameters - * @v in_mod Input modifier (0 if no modifier applicable) - * @v out Output parameters - * @ret rc Return status code - */ -static int arbel_cmd ( struct arbel *arbel, unsigned long command, - unsigned int op_mod, const void *in, - unsigned int in_mod, void *out ) { - struct arbelprm_hca_command_register hcr; - unsigned int opcode = ARBEL_HCR_OPCODE ( command ); - size_t in_len = ARBEL_HCR_IN_LEN ( command ); - size_t out_len = ARBEL_HCR_OUT_LEN ( command ); - void *in_buffer; - void *out_buffer; - unsigned int status; - unsigned int i; - int rc; - - assert ( in_len <= ARBEL_MBOX_SIZE ); - assert ( out_len <= ARBEL_MBOX_SIZE ); - - DBGC2 ( arbel, "Arbel %p command %02x in %zx%s out %zx%s\n", - arbel, opcode, in_len, - ( ( command & ARBEL_HCR_IN_MBOX ) ? "(mbox)" : "" ), out_len, - ( ( command & ARBEL_HCR_OUT_MBOX ) ? "(mbox)" : "" ) ); - - /* Check that HCR is free */ - if ( ( rc = arbel_cmd_wait ( arbel, &hcr ) ) != 0 ) { - DBGC ( arbel, "Arbel %p command interface locked\n", arbel ); - return rc; - } - - /* Prepare HCR */ - memset ( &hcr, 0, sizeof ( hcr ) ); - in_buffer = &hcr.u.dwords[0]; - if ( in_len && ( command & ARBEL_HCR_IN_MBOX ) ) { - in_buffer = arbel->mailbox_in; - MLX_FILL_1 ( &hcr, 1, in_param_l, virt_to_bus ( in_buffer ) ); - } - memcpy ( in_buffer, in, in_len ); - MLX_FILL_1 ( &hcr, 2, input_modifier, in_mod ); - out_buffer = &hcr.u.dwords[3]; - if ( out_len && ( command & ARBEL_HCR_OUT_MBOX ) ) { - out_buffer = arbel->mailbox_out; - MLX_FILL_1 ( &hcr, 4, out_param_l, - virt_to_bus ( out_buffer ) ); - } - MLX_FILL_3 ( &hcr, 6, - opcode, opcode, - opcode_modifier, op_mod, - go, 1 ); - DBGC2_HD ( arbel, &hcr, sizeof ( hcr ) ); - if ( in_len ) { - DBGC2 ( arbel, "Input:\n" ); - DBGC2_HD ( arbel, in, ( ( in_len < 512 ) ? in_len : 512 ) ); - } - - /* Issue command */ - for ( i = 0 ; i < ( sizeof ( hcr ) / sizeof ( hcr.u.dwords[0] ) ) ; - i++ ) { - writel ( hcr.u.dwords[i], - arbel->config + ARBEL_HCR_REG ( i ) ); - barrier(); - } - - /* Wait for command completion */ - if ( ( rc = arbel_cmd_wait ( arbel, &hcr ) ) != 0 ) { - DBGC ( arbel, "Arbel %p timed out waiting for command:\n", - arbel ); - DBGC_HD ( arbel, &hcr, sizeof ( hcr ) ); - return rc; - } - - /* Check command status */ - status = MLX_GET ( &hcr, status ); - if ( status != 0 ) { - DBGC ( arbel, "Arbel %p command failed with status %02x:\n", - arbel, status ); - DBGC_HD ( arbel, &hcr, sizeof ( hcr ) ); - return -EIO; - } - - /* Read output parameters, if any */ - hcr.u.dwords[3] = readl ( arbel->config + ARBEL_HCR_REG ( 3 ) ); - hcr.u.dwords[4] = readl ( arbel->config + ARBEL_HCR_REG ( 4 ) ); - memcpy ( out, out_buffer, out_len ); - if ( out_len ) { - DBGC2 ( arbel, "Output:\n" ); - DBGC2_HD ( arbel, out, ( ( out_len < 512 ) ? out_len : 512 ) ); - } - - return 0; -} - -static inline int -arbel_cmd_query_dev_lim ( struct arbel *arbel, - struct arbelprm_query_dev_lim *dev_lim ) { - return arbel_cmd ( arbel, - ARBEL_HCR_OUT_CMD ( ARBEL_HCR_QUERY_DEV_LIM, - 1, sizeof ( *dev_lim ) ), - 0, NULL, 0, dev_lim ); -} - -static inline int -arbel_cmd_query_fw ( struct arbel *arbel, struct arbelprm_query_fw *fw ) { - return arbel_cmd ( arbel, - ARBEL_HCR_OUT_CMD ( ARBEL_HCR_QUERY_FW, - 1, sizeof ( *fw ) ), - 0, NULL, 0, fw ); -} - -static inline int -arbel_cmd_init_hca ( struct arbel *arbel, - const struct arbelprm_init_hca *init_hca ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_INIT_HCA, - 1, sizeof ( *init_hca ) ), - 0, init_hca, 0, NULL ); -} - -static inline int -arbel_cmd_close_hca ( struct arbel *arbel ) { - return arbel_cmd ( arbel, - ARBEL_HCR_VOID_CMD ( ARBEL_HCR_CLOSE_HCA ), - 0, NULL, 0, NULL ); -} - -static inline int -arbel_cmd_init_ib ( struct arbel *arbel, unsigned int port, - const struct arbelprm_init_ib *init_ib ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_INIT_IB, - 1, sizeof ( *init_ib ) ), - 0, init_ib, port, NULL ); -} - -static inline int -arbel_cmd_close_ib ( struct arbel *arbel, unsigned int port ) { - return arbel_cmd ( arbel, - ARBEL_HCR_VOID_CMD ( ARBEL_HCR_CLOSE_IB ), - 0, NULL, port, NULL ); -} - -static inline int -arbel_cmd_sw2hw_mpt ( struct arbel *arbel, unsigned int index, - const struct arbelprm_mpt *mpt ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_SW2HW_MPT, - 1, sizeof ( *mpt ) ), - 0, mpt, index, NULL ); -} - -static inline int -arbel_cmd_map_eq ( struct arbel *arbel, unsigned long index_map, - const struct arbelprm_event_mask *mask ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_MAP_EQ, - 0, sizeof ( *mask ) ), - 0, mask, index_map, NULL ); -} - -static inline int -arbel_cmd_sw2hw_eq ( struct arbel *arbel, unsigned int index, - const struct arbelprm_eqc *eqctx ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_SW2HW_EQ, - 1, sizeof ( *eqctx ) ), - 0, eqctx, index, NULL ); -} - -static inline int -arbel_cmd_hw2sw_eq ( struct arbel *arbel, unsigned int index, - struct arbelprm_eqc *eqctx ) { - return arbel_cmd ( arbel, - ARBEL_HCR_OUT_CMD ( ARBEL_HCR_HW2SW_EQ, - 1, sizeof ( *eqctx ) ), - 1, NULL, index, eqctx ); -} - -static inline int -arbel_cmd_sw2hw_cq ( struct arbel *arbel, unsigned long cqn, - const struct arbelprm_completion_queue_context *cqctx ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_SW2HW_CQ, - 1, sizeof ( *cqctx ) ), - 0, cqctx, cqn, NULL ); -} - -static inline int -arbel_cmd_hw2sw_cq ( struct arbel *arbel, unsigned long cqn, - struct arbelprm_completion_queue_context *cqctx) { - return arbel_cmd ( arbel, - ARBEL_HCR_OUT_CMD ( ARBEL_HCR_HW2SW_CQ, - 1, sizeof ( *cqctx ) ), - 0, NULL, cqn, cqctx ); -} - -static inline int -arbel_cmd_rst2init_qpee ( struct arbel *arbel, unsigned long qpn, - const struct arbelprm_qp_ee_state_transitions *ctx ){ - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_RST2INIT_QPEE, - 1, sizeof ( *ctx ) ), - 0, ctx, qpn, NULL ); -} - -static inline int -arbel_cmd_init2rtr_qpee ( struct arbel *arbel, unsigned long qpn, - const struct arbelprm_qp_ee_state_transitions *ctx ){ - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_INIT2RTR_QPEE, - 1, sizeof ( *ctx ) ), - 0, ctx, qpn, NULL ); -} - -static inline int -arbel_cmd_rtr2rts_qpee ( struct arbel *arbel, unsigned long qpn, - const struct arbelprm_qp_ee_state_transitions *ctx ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_RTR2RTS_QPEE, - 1, sizeof ( *ctx ) ), - 0, ctx, qpn, NULL ); -} - -static inline int -arbel_cmd_rts2rts_qp ( struct arbel *arbel, unsigned long qpn, - const struct arbelprm_qp_ee_state_transitions *ctx ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_RTS2RTS_QPEE, - 1, sizeof ( *ctx ) ), - 0, ctx, qpn, NULL ); -} - -static inline int -arbel_cmd_2rst_qpee ( struct arbel *arbel, unsigned long qpn ) { - return arbel_cmd ( arbel, - ARBEL_HCR_VOID_CMD ( ARBEL_HCR_2RST_QPEE ), - 0x03, NULL, qpn, NULL ); -} - -static inline int -arbel_cmd_mad_ifc ( struct arbel *arbel, unsigned int port, - union arbelprm_mad *mad ) { - return arbel_cmd ( arbel, - ARBEL_HCR_INOUT_CMD ( ARBEL_HCR_MAD_IFC, - 1, sizeof ( *mad ), - 1, sizeof ( *mad ) ), - 0x03, mad, port, mad ); -} - -static inline int -arbel_cmd_read_mgm ( struct arbel *arbel, unsigned int index, - struct arbelprm_mgm_entry *mgm ) { - return arbel_cmd ( arbel, - ARBEL_HCR_OUT_CMD ( ARBEL_HCR_READ_MGM, - 1, sizeof ( *mgm ) ), - 0, NULL, index, mgm ); -} - -static inline int -arbel_cmd_write_mgm ( struct arbel *arbel, unsigned int index, - const struct arbelprm_mgm_entry *mgm ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_WRITE_MGM, - 1, sizeof ( *mgm ) ), - 0, mgm, index, NULL ); -} - -static inline int -arbel_cmd_mgid_hash ( struct arbel *arbel, const struct ib_gid *gid, - struct arbelprm_mgm_hash *hash ) { - return arbel_cmd ( arbel, - ARBEL_HCR_INOUT_CMD ( ARBEL_HCR_MGID_HASH, - 1, sizeof ( *gid ), - 0, sizeof ( *hash ) ), - 0, gid, 0, hash ); -} - -static inline int -arbel_cmd_run_fw ( struct arbel *arbel ) { - return arbel_cmd ( arbel, - ARBEL_HCR_VOID_CMD ( ARBEL_HCR_RUN_FW ), - 0, NULL, 0, NULL ); -} - -static inline int -arbel_cmd_disable_lam ( struct arbel *arbel ) { - return arbel_cmd ( arbel, - ARBEL_HCR_VOID_CMD ( ARBEL_HCR_DISABLE_LAM ), - 0, NULL, 0, NULL ); -} - -static inline int -arbel_cmd_enable_lam ( struct arbel *arbel, struct arbelprm_access_lam *lam ) { - return arbel_cmd ( arbel, - ARBEL_HCR_OUT_CMD ( ARBEL_HCR_ENABLE_LAM, - 1, sizeof ( *lam ) ), - 1, NULL, 0, lam ); -} - -static inline int -arbel_cmd_unmap_icm ( struct arbel *arbel, unsigned int page_count ) { - return arbel_cmd ( arbel, - ARBEL_HCR_VOID_CMD ( ARBEL_HCR_UNMAP_ICM ), - 0, NULL, page_count, NULL ); -} - -static inline int -arbel_cmd_map_icm ( struct arbel *arbel, - const struct arbelprm_virtual_physical_mapping *map ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_MAP_ICM, - 1, sizeof ( *map ) ), - 0, map, 1, NULL ); -} - -static inline int -arbel_cmd_unmap_icm_aux ( struct arbel *arbel ) { - return arbel_cmd ( arbel, - ARBEL_HCR_VOID_CMD ( ARBEL_HCR_UNMAP_ICM_AUX ), - 0, NULL, 0, NULL ); -} - -static inline int -arbel_cmd_map_icm_aux ( struct arbel *arbel, - const struct arbelprm_virtual_physical_mapping *map ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_MAP_ICM_AUX, - 1, sizeof ( *map ) ), - 0, map, 1, NULL ); -} - -static inline int -arbel_cmd_set_icm_size ( struct arbel *arbel, - const struct arbelprm_scalar_parameter *icm_size, - struct arbelprm_scalar_parameter *icm_aux_size ) { - return arbel_cmd ( arbel, - ARBEL_HCR_INOUT_CMD ( ARBEL_HCR_SET_ICM_SIZE, - 0, sizeof ( *icm_size ), - 0, sizeof ( *icm_aux_size ) ), - 0, icm_size, 0, icm_aux_size ); -} - -static inline int -arbel_cmd_unmap_fa ( struct arbel *arbel ) { - return arbel_cmd ( arbel, - ARBEL_HCR_VOID_CMD ( ARBEL_HCR_UNMAP_FA ), - 0, NULL, 0, NULL ); -} - -static inline int -arbel_cmd_map_fa ( struct arbel *arbel, - const struct arbelprm_virtual_physical_mapping *map ) { - return arbel_cmd ( arbel, - ARBEL_HCR_IN_CMD ( ARBEL_HCR_MAP_FA, - 1, sizeof ( *map ) ), - 0, map, 1, NULL ); -} - -/*************************************************************************** - * - * MAD operations - * - *************************************************************************** - */ - -/** - * Issue management datagram - * - * @v ibdev Infiniband device - * @v mad Management datagram - * @ret rc Return status code - */ -static int arbel_mad ( struct ib_device *ibdev, union ib_mad *mad ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - union arbelprm_mad mad_ifc; - int rc; - - linker_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ), - mad_size_mismatch ); - - /* Copy in request packet */ - memcpy ( &mad_ifc.mad, mad, sizeof ( mad_ifc.mad ) ); - - /* Issue MAD */ - if ( ( rc = arbel_cmd_mad_ifc ( arbel, ibdev->port, - &mad_ifc ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not issue MAD IFC: %s\n", - arbel, strerror ( rc ) ); - return rc; - } - - /* Copy out reply packet */ - memcpy ( mad, &mad_ifc.mad, sizeof ( *mad ) ); - - if ( mad->hdr.status != 0 ) { - DBGC ( arbel, "Arbel %p MAD IFC status %04x\n", - arbel, ntohs ( mad->hdr.status ) ); - return -EIO; - } - return 0; -} - -/*************************************************************************** - * - * Completion queue operations - * - *************************************************************************** - */ - -/** - * Create completion queue - * - * @v ibdev Infiniband device - * @v cq Completion queue - * @ret rc Return status code - */ -static int arbel_create_cq ( struct ib_device *ibdev, - struct ib_completion_queue *cq ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbel_completion_queue *arbel_cq; - struct arbelprm_completion_queue_context cqctx; - struct arbelprm_cq_ci_db_record *ci_db_rec; - struct arbelprm_cq_arm_db_record *arm_db_rec; - int cqn_offset; - unsigned int i; - int rc; - - /* Find a free completion queue number */ - cqn_offset = arbel_alloc_qn_offset ( arbel->cq_inuse, ARBEL_MAX_CQS ); - if ( cqn_offset < 0 ) { - DBGC ( arbel, "Arbel %p out of completion queues\n", arbel ); - rc = cqn_offset; - goto err_cqn_offset; - } - cq->cqn = ( arbel->limits.reserved_cqs + cqn_offset ); - - /* Allocate control structures */ - arbel_cq = zalloc ( sizeof ( *arbel_cq ) ); - if ( ! arbel_cq ) { - rc = -ENOMEM; - goto err_arbel_cq; - } - arbel_cq->ci_doorbell_idx = arbel_cq_ci_doorbell_idx ( cqn_offset ); - arbel_cq->arm_doorbell_idx = arbel_cq_arm_doorbell_idx ( cqn_offset ); - - /* Allocate completion queue itself */ - arbel_cq->cqe_size = ( cq->num_cqes * sizeof ( arbel_cq->cqe[0] ) ); - arbel_cq->cqe = malloc_dma ( arbel_cq->cqe_size, - sizeof ( arbel_cq->cqe[0] ) ); - if ( ! arbel_cq->cqe ) { - rc = -ENOMEM; - goto err_cqe; - } - memset ( arbel_cq->cqe, 0, arbel_cq->cqe_size ); - for ( i = 0 ; i < cq->num_cqes ; i++ ) { - MLX_FILL_1 ( &arbel_cq->cqe[i].normal, 7, owner, 1 ); - } - barrier(); - - /* Initialise doorbell records */ - ci_db_rec = &arbel->db_rec[arbel_cq->ci_doorbell_idx].cq_ci; - MLX_FILL_1 ( ci_db_rec, 0, counter, 0 ); - MLX_FILL_2 ( ci_db_rec, 1, - res, ARBEL_UAR_RES_CQ_CI, - cq_number, cq->cqn ); - arm_db_rec = &arbel->db_rec[arbel_cq->arm_doorbell_idx].cq_arm; - MLX_FILL_1 ( arm_db_rec, 0, counter, 0 ); - MLX_FILL_2 ( arm_db_rec, 1, - res, ARBEL_UAR_RES_CQ_ARM, - cq_number, cq->cqn ); - - /* Hand queue over to hardware */ - memset ( &cqctx, 0, sizeof ( cqctx ) ); - MLX_FILL_1 ( &cqctx, 0, st, 0xa /* "Event fired" */ ); - MLX_FILL_1 ( &cqctx, 2, start_address_l, - virt_to_bus ( arbel_cq->cqe ) ); - MLX_FILL_2 ( &cqctx, 3, - usr_page, arbel->limits.reserved_uars, - log_cq_size, fls ( cq->num_cqes - 1 ) ); - MLX_FILL_1 ( &cqctx, 5, c_eqn, ARBEL_NO_EQ ); - MLX_FILL_1 ( &cqctx, 6, pd, ARBEL_GLOBAL_PD ); - MLX_FILL_1 ( &cqctx, 7, l_key, arbel->reserved_lkey ); - MLX_FILL_1 ( &cqctx, 12, cqn, cq->cqn ); - MLX_FILL_1 ( &cqctx, 13, - cq_ci_db_record, arbel_cq->ci_doorbell_idx ); - MLX_FILL_1 ( &cqctx, 14, - cq_state_db_record, arbel_cq->arm_doorbell_idx ); - if ( ( rc = arbel_cmd_sw2hw_cq ( arbel, cq->cqn, &cqctx ) ) != 0 ) { - DBGC ( arbel, "Arbel %p SW2HW_CQ failed: %s\n", - arbel, strerror ( rc ) ); - goto err_sw2hw_cq; - } - - DBGC ( arbel, "Arbel %p CQN %#lx ring at [%p,%p)\n", - arbel, cq->cqn, arbel_cq->cqe, - ( ( ( void * ) arbel_cq->cqe ) + arbel_cq->cqe_size ) ); - ib_cq_set_drvdata ( cq, arbel_cq ); - return 0; - - err_sw2hw_cq: - MLX_FILL_1 ( ci_db_rec, 1, res, ARBEL_UAR_RES_NONE ); - MLX_FILL_1 ( arm_db_rec, 1, res, ARBEL_UAR_RES_NONE ); - free_dma ( arbel_cq->cqe, arbel_cq->cqe_size ); - err_cqe: - free ( arbel_cq ); - err_arbel_cq: - arbel_free_qn_offset ( arbel->cq_inuse, cqn_offset ); - err_cqn_offset: - return rc; -} - -/** - * Destroy completion queue - * - * @v ibdev Infiniband device - * @v cq Completion queue - */ -static void arbel_destroy_cq ( struct ib_device *ibdev, - struct ib_completion_queue *cq ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbel_completion_queue *arbel_cq = ib_cq_get_drvdata ( cq ); - struct arbelprm_completion_queue_context cqctx; - struct arbelprm_cq_ci_db_record *ci_db_rec; - struct arbelprm_cq_arm_db_record *arm_db_rec; - int cqn_offset; - int rc; - - /* Take ownership back from hardware */ - if ( ( rc = arbel_cmd_hw2sw_cq ( arbel, cq->cqn, &cqctx ) ) != 0 ) { - DBGC ( arbel, "Arbel %p FATAL HW2SW_CQ failed on CQN %#lx: " - "%s\n", arbel, cq->cqn, strerror ( rc ) ); - /* Leak memory and return; at least we avoid corruption */ - return; - } - - /* Clear doorbell records */ - ci_db_rec = &arbel->db_rec[arbel_cq->ci_doorbell_idx].cq_ci; - arm_db_rec = &arbel->db_rec[arbel_cq->arm_doorbell_idx].cq_arm; - MLX_FILL_1 ( ci_db_rec, 1, res, ARBEL_UAR_RES_NONE ); - MLX_FILL_1 ( arm_db_rec, 1, res, ARBEL_UAR_RES_NONE ); - - /* Free memory */ - free_dma ( arbel_cq->cqe, arbel_cq->cqe_size ); - free ( arbel_cq ); - - /* Mark queue number as free */ - cqn_offset = ( cq->cqn - arbel->limits.reserved_cqs ); - arbel_free_qn_offset ( arbel->cq_inuse, cqn_offset ); - - ib_cq_set_drvdata ( cq, NULL ); -} - -/*************************************************************************** - * - * Queue pair operations - * - *************************************************************************** - */ - -/** - * Create send work queue - * - * @v arbel_send_wq Send work queue - * @v num_wqes Number of work queue entries - * @ret rc Return status code - */ -static int arbel_create_send_wq ( struct arbel_send_work_queue *arbel_send_wq, - unsigned int num_wqes ) { - struct arbelprm_ud_send_wqe *wqe; - struct arbelprm_ud_send_wqe *next_wqe; - unsigned int wqe_idx_mask; - unsigned int i; - - /* Allocate work queue */ - arbel_send_wq->wqe_size = ( num_wqes * - sizeof ( arbel_send_wq->wqe[0] ) ); - arbel_send_wq->wqe = malloc_dma ( arbel_send_wq->wqe_size, - sizeof ( arbel_send_wq->wqe[0] ) ); - if ( ! arbel_send_wq->wqe ) - return -ENOMEM; - memset ( arbel_send_wq->wqe, 0, arbel_send_wq->wqe_size ); - - /* Link work queue entries */ - wqe_idx_mask = ( num_wqes - 1 ); - for ( i = 0 ; i < num_wqes ; i++ ) { - wqe = &arbel_send_wq->wqe[i].ud; - next_wqe = &arbel_send_wq->wqe[ ( i + 1 ) & wqe_idx_mask ].ud; - MLX_FILL_1 ( &wqe->next, 0, nda_31_6, - ( virt_to_bus ( next_wqe ) >> 6 ) ); - } - - return 0; -} - -/** - * Create receive work queue - * - * @v arbel_recv_wq Receive work queue - * @v num_wqes Number of work queue entries - * @ret rc Return status code - */ -static int arbel_create_recv_wq ( struct arbel_recv_work_queue *arbel_recv_wq, - unsigned int num_wqes ) { - struct arbelprm_recv_wqe *wqe; - struct arbelprm_recv_wqe *next_wqe; - unsigned int wqe_idx_mask; - size_t nds; - unsigned int i; - unsigned int j; - - /* Allocate work queue */ - arbel_recv_wq->wqe_size = ( num_wqes * - sizeof ( arbel_recv_wq->wqe[0] ) ); - arbel_recv_wq->wqe = malloc_dma ( arbel_recv_wq->wqe_size, - sizeof ( arbel_recv_wq->wqe[0] ) ); - if ( ! arbel_recv_wq->wqe ) - return -ENOMEM; - memset ( arbel_recv_wq->wqe, 0, arbel_recv_wq->wqe_size ); - - /* Link work queue entries */ - wqe_idx_mask = ( num_wqes - 1 ); - nds = ( ( offsetof ( typeof ( *wqe ), data ) + - sizeof ( wqe->data[0] ) ) >> 4 ); - for ( i = 0 ; i < num_wqes ; i++ ) { - wqe = &arbel_recv_wq->wqe[i].recv; - next_wqe = &arbel_recv_wq->wqe[( i + 1 ) & wqe_idx_mask].recv; - MLX_FILL_1 ( &wqe->next, 0, nda_31_6, - ( virt_to_bus ( next_wqe ) >> 6 ) ); - MLX_FILL_1 ( &wqe->next, 1, nds, ( sizeof ( *wqe ) / 16 ) ); - for ( j = 0 ; ( ( ( void * ) &wqe->data[j] ) < - ( ( void * ) ( wqe + 1 ) ) ) ; j++ ) { - MLX_FILL_1 ( &wqe->data[j], 1, - l_key, ARBEL_INVALID_LKEY ); - } - } - - return 0; -} - -/** - * Create queue pair - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @ret rc Return status code - */ -static int arbel_create_qp ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbel_queue_pair *arbel_qp; - struct arbelprm_qp_ee_state_transitions qpctx; - struct arbelprm_qp_db_record *send_db_rec; - struct arbelprm_qp_db_record *recv_db_rec; - int qpn_offset; - int rc; - - /* Find a free queue pair number */ - qpn_offset = arbel_alloc_qn_offset ( arbel->qp_inuse, ARBEL_MAX_QPS ); - if ( qpn_offset < 0 ) { - DBGC ( arbel, "Arbel %p out of queue pairs\n", arbel ); - rc = qpn_offset; - goto err_qpn_offset; - } - qp->qpn = ( ARBEL_QPN_BASE + arbel->limits.reserved_qps + qpn_offset ); - - /* Allocate control structures */ - arbel_qp = zalloc ( sizeof ( *arbel_qp ) ); - if ( ! arbel_qp ) { - rc = -ENOMEM; - goto err_arbel_qp; - } - arbel_qp->send.doorbell_idx = arbel_send_doorbell_idx ( qpn_offset ); - arbel_qp->recv.doorbell_idx = arbel_recv_doorbell_idx ( qpn_offset ); - - /* Create send and receive work queues */ - if ( ( rc = arbel_create_send_wq ( &arbel_qp->send, - qp->send.num_wqes ) ) != 0 ) - goto err_create_send_wq; - if ( ( rc = arbel_create_recv_wq ( &arbel_qp->recv, - qp->recv.num_wqes ) ) != 0 ) - goto err_create_recv_wq; - - /* Initialise doorbell records */ - send_db_rec = &arbel->db_rec[arbel_qp->send.doorbell_idx].qp; - MLX_FILL_1 ( send_db_rec, 0, counter, 0 ); - MLX_FILL_2 ( send_db_rec, 1, - res, ARBEL_UAR_RES_SQ, - qp_number, qp->qpn ); - recv_db_rec = &arbel->db_rec[arbel_qp->recv.doorbell_idx].qp; - MLX_FILL_1 ( recv_db_rec, 0, counter, 0 ); - MLX_FILL_2 ( recv_db_rec, 1, - res, ARBEL_UAR_RES_RQ, - qp_number, qp->qpn ); - - /* Hand queue over to hardware */ - memset ( &qpctx, 0, sizeof ( qpctx ) ); - MLX_FILL_3 ( &qpctx, 2, - qpc_eec_data.de, 1, - qpc_eec_data.pm_state, 0x03 /* Always 0x03 for UD */, - qpc_eec_data.st, ARBEL_ST_UD ); - MLX_FILL_6 ( &qpctx, 4, - qpc_eec_data.mtu, ARBEL_MTU_2048, - qpc_eec_data.msg_max, 11 /* 2^11 = 2048 */, - qpc_eec_data.log_rq_size, fls ( qp->recv.num_wqes - 1 ), - qpc_eec_data.log_rq_stride, - ( fls ( sizeof ( arbel_qp->recv.wqe[0] ) - 1 ) - 4 ), - qpc_eec_data.log_sq_size, fls ( qp->send.num_wqes - 1 ), - qpc_eec_data.log_sq_stride, - ( fls ( sizeof ( arbel_qp->send.wqe[0] ) - 1 ) - 4 ) ); - MLX_FILL_1 ( &qpctx, 5, - qpc_eec_data.usr_page, arbel->limits.reserved_uars ); - MLX_FILL_1 ( &qpctx, 10, qpc_eec_data.primary_address_path.port_number, - ibdev->port ); - MLX_FILL_1 ( &qpctx, 27, qpc_eec_data.pd, ARBEL_GLOBAL_PD ); - MLX_FILL_1 ( &qpctx, 29, qpc_eec_data.wqe_lkey, arbel->reserved_lkey ); - MLX_FILL_1 ( &qpctx, 30, qpc_eec_data.ssc, 1 ); - MLX_FILL_1 ( &qpctx, 33, qpc_eec_data.cqn_snd, qp->send.cq->cqn ); - MLX_FILL_1 ( &qpctx, 34, qpc_eec_data.snd_wqe_base_adr_l, - ( virt_to_bus ( arbel_qp->send.wqe ) >> 6 ) ); - MLX_FILL_1 ( &qpctx, 35, qpc_eec_data.snd_db_record_index, - arbel_qp->send.doorbell_idx ); - MLX_FILL_1 ( &qpctx, 38, qpc_eec_data.rsc, 1 ); - MLX_FILL_1 ( &qpctx, 41, qpc_eec_data.cqn_rcv, qp->recv.cq->cqn ); - MLX_FILL_1 ( &qpctx, 42, qpc_eec_data.rcv_wqe_base_adr_l, - ( virt_to_bus ( arbel_qp->recv.wqe ) >> 6 ) ); - MLX_FILL_1 ( &qpctx, 43, qpc_eec_data.rcv_db_record_index, - arbel_qp->recv.doorbell_idx ); - if ( ( rc = arbel_cmd_rst2init_qpee ( arbel, qp->qpn, &qpctx )) != 0 ){ - DBGC ( arbel, "Arbel %p RST2INIT_QPEE failed: %s\n", - arbel, strerror ( rc ) ); - goto err_rst2init_qpee; - } - memset ( &qpctx, 0, sizeof ( qpctx ) ); - MLX_FILL_2 ( &qpctx, 4, - qpc_eec_data.mtu, ARBEL_MTU_2048, - qpc_eec_data.msg_max, 11 /* 2^11 = 2048 */ ); - if ( ( rc = arbel_cmd_init2rtr_qpee ( arbel, qp->qpn, &qpctx )) != 0 ){ - DBGC ( arbel, "Arbel %p INIT2RTR_QPEE failed: %s\n", - arbel, strerror ( rc ) ); - goto err_init2rtr_qpee; - } - memset ( &qpctx, 0, sizeof ( qpctx ) ); - if ( ( rc = arbel_cmd_rtr2rts_qpee ( arbel, qp->qpn, &qpctx ) ) != 0 ){ - DBGC ( arbel, "Arbel %p RTR2RTS_QPEE failed: %s\n", - arbel, strerror ( rc ) ); - goto err_rtr2rts_qpee; - } - - DBGC ( arbel, "Arbel %p QPN %#lx send ring at [%p,%p)\n", - arbel, qp->qpn, arbel_qp->send.wqe, - ( ( (void *) arbel_qp->send.wqe ) + arbel_qp->send.wqe_size ) ); - DBGC ( arbel, "Arbel %p QPN %#lx receive ring at [%p,%p)\n", - arbel, qp->qpn, arbel_qp->recv.wqe, - ( ( (void *) arbel_qp->recv.wqe ) + arbel_qp->recv.wqe_size ) ); - ib_qp_set_drvdata ( qp, arbel_qp ); - return 0; - - err_rtr2rts_qpee: - err_init2rtr_qpee: - arbel_cmd_2rst_qpee ( arbel, qp->qpn ); - err_rst2init_qpee: - MLX_FILL_1 ( send_db_rec, 1, res, ARBEL_UAR_RES_NONE ); - MLX_FILL_1 ( recv_db_rec, 1, res, ARBEL_UAR_RES_NONE ); - free_dma ( arbel_qp->recv.wqe, arbel_qp->recv.wqe_size ); - err_create_recv_wq: - free_dma ( arbel_qp->send.wqe, arbel_qp->send.wqe_size ); - err_create_send_wq: - free ( arbel_qp ); - err_arbel_qp: - arbel_free_qn_offset ( arbel->qp_inuse, qpn_offset ); - err_qpn_offset: - return rc; -} - -/** - * Modify queue pair - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @ret rc Return status code - */ -static int arbel_modify_qp ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbelprm_qp_ee_state_transitions qpctx; - int rc; - - /* Issue RTS2RTS_QP */ - memset ( &qpctx, 0, sizeof ( qpctx ) ); - MLX_FILL_1 ( &qpctx, 0, opt_param_mask, ARBEL_QPEE_OPT_PARAM_QKEY ); - MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey ); - if ( ( rc = arbel_cmd_rts2rts_qp ( arbel, qp->qpn, &qpctx ) ) != 0 ){ - DBGC ( arbel, "Arbel %p RTS2RTS_QP failed: %s\n", - arbel, strerror ( rc ) ); - return rc; - } - - return 0; -} - -/** - * Destroy queue pair - * - * @v ibdev Infiniband device - * @v qp Queue pair - */ -static void arbel_destroy_qp ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbel_queue_pair *arbel_qp = ib_qp_get_drvdata ( qp ); - struct arbelprm_qp_db_record *send_db_rec; - struct arbelprm_qp_db_record *recv_db_rec; - int qpn_offset; - int rc; - - /* Take ownership back from hardware */ - if ( ( rc = arbel_cmd_2rst_qpee ( arbel, qp->qpn ) ) != 0 ) { - DBGC ( arbel, "Arbel %p FATAL 2RST_QPEE failed on QPN %#lx: " - "%s\n", arbel, qp->qpn, strerror ( rc ) ); - /* Leak memory and return; at least we avoid corruption */ - return; - } - - /* Clear doorbell records */ - send_db_rec = &arbel->db_rec[arbel_qp->send.doorbell_idx].qp; - recv_db_rec = &arbel->db_rec[arbel_qp->recv.doorbell_idx].qp; - MLX_FILL_1 ( send_db_rec, 1, res, ARBEL_UAR_RES_NONE ); - MLX_FILL_1 ( recv_db_rec, 1, res, ARBEL_UAR_RES_NONE ); - - /* Free memory */ - free_dma ( arbel_qp->send.wqe, arbel_qp->send.wqe_size ); - free_dma ( arbel_qp->recv.wqe, arbel_qp->recv.wqe_size ); - free ( arbel_qp ); - - /* Mark queue number as free */ - qpn_offset = ( qp->qpn - ARBEL_QPN_BASE - arbel->limits.reserved_qps ); - arbel_free_qn_offset ( arbel->qp_inuse, qpn_offset ); - - ib_qp_set_drvdata ( qp, NULL ); -} - -/*************************************************************************** - * - * Work request operations - * - *************************************************************************** - */ - -/** - * Ring doorbell register in UAR - * - * @v arbel Arbel device - * @v db_reg Doorbell register structure - * @v offset Address of doorbell - */ -static void arbel_ring_doorbell ( struct arbel *arbel, - union arbelprm_doorbell_register *db_reg, - unsigned int offset ) { - - DBGC2 ( arbel, "Arbel %p ringing doorbell %08x:%08x at %lx\n", - arbel, db_reg->dword[0], db_reg->dword[1], - virt_to_phys ( arbel->uar + offset ) ); - - barrier(); - writel ( db_reg->dword[0], ( arbel->uar + offset + 0 ) ); - barrier(); - writel ( db_reg->dword[1], ( arbel->uar + offset + 4 ) ); -} - -/** GID used for GID-less send work queue entries */ -static const struct ib_gid arbel_no_gid = { - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 } } -}; - -/** - * Post send work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v av Address vector - * @v iobuf I/O buffer - * @ret rc Return status code - */ -static int arbel_post_send ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct ib_address_vector *av, - struct io_buffer *iobuf ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbel_queue_pair *arbel_qp = ib_qp_get_drvdata ( qp ); - struct ib_work_queue *wq = &qp->send; - struct arbel_send_work_queue *arbel_send_wq = &arbel_qp->send; - struct arbelprm_ud_send_wqe *prev_wqe; - struct arbelprm_ud_send_wqe *wqe; - struct arbelprm_qp_db_record *qp_db_rec; - union arbelprm_doorbell_register db_reg; - const struct ib_gid *gid; - unsigned int wqe_idx_mask; - size_t nds; - - /* Allocate work queue entry */ - wqe_idx_mask = ( wq->num_wqes - 1 ); - if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) { - DBGC ( arbel, "Arbel %p send queue full", arbel ); - return -ENOBUFS; - } - wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf; - prev_wqe = &arbel_send_wq->wqe[(wq->next_idx - 1) & wqe_idx_mask].ud; - wqe = &arbel_send_wq->wqe[wq->next_idx & wqe_idx_mask].ud; - - /* Construct work queue entry */ - MLX_FILL_1 ( &wqe->next, 1, always1, 1 ); - memset ( &wqe->ctrl, 0, sizeof ( wqe->ctrl ) ); - MLX_FILL_1 ( &wqe->ctrl, 0, always1, 1 ); - memset ( &wqe->ud, 0, sizeof ( wqe->ud ) ); - MLX_FILL_2 ( &wqe->ud, 0, - ud_address_vector.pd, ARBEL_GLOBAL_PD, - ud_address_vector.port_number, ibdev->port ); - MLX_FILL_2 ( &wqe->ud, 1, - ud_address_vector.rlid, av->lid, - ud_address_vector.g, av->gid_present ); - MLX_FILL_2 ( &wqe->ud, 2, - ud_address_vector.max_stat_rate, - ( ( av->rate >= 3 ) ? 0 : 1 ), - ud_address_vector.msg, 3 ); - MLX_FILL_1 ( &wqe->ud, 3, ud_address_vector.sl, av->sl ); - gid = ( av->gid_present ? &av->gid : &arbel_no_gid ); - memcpy ( &wqe->ud.u.dwords[4], gid, sizeof ( *gid ) ); - MLX_FILL_1 ( &wqe->ud, 8, destination_qp, av->qpn ); - MLX_FILL_1 ( &wqe->ud, 9, q_key, av->qkey ); - MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_len ( iobuf ) ); - MLX_FILL_1 ( &wqe->data[0], 1, l_key, arbel->reserved_lkey ); - MLX_FILL_1 ( &wqe->data[0], 3, - local_address_l, virt_to_bus ( iobuf->data ) ); - - /* Update previous work queue entry's "next" field */ - nds = ( ( offsetof ( typeof ( *wqe ), data ) + - sizeof ( wqe->data[0] ) ) >> 4 ); - MLX_SET ( &prev_wqe->next, nopcode, ARBEL_OPCODE_SEND ); - MLX_FILL_3 ( &prev_wqe->next, 1, - nds, nds, - f, 1, - always1, 1 ); - - /* Update doorbell record */ - barrier(); - qp_db_rec = &arbel->db_rec[arbel_send_wq->doorbell_idx].qp; - MLX_FILL_1 ( qp_db_rec, 0, - counter, ( ( wq->next_idx + 1 ) & 0xffff ) ); - - /* Ring doorbell register */ - MLX_FILL_4 ( &db_reg.send, 0, - nopcode, ARBEL_OPCODE_SEND, - f, 1, - wqe_counter, ( wq->next_idx & 0xffff ), - wqe_cnt, 1 ); - MLX_FILL_2 ( &db_reg.send, 1, - nds, nds, - qpn, qp->qpn ); - arbel_ring_doorbell ( arbel, &db_reg, ARBEL_DB_POST_SND_OFFSET ); - - /* Update work queue's index */ - wq->next_idx++; - - return 0; -} - -/** - * Post receive work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v iobuf I/O buffer - * @ret rc Return status code - */ -static int arbel_post_recv ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct io_buffer *iobuf ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbel_queue_pair *arbel_qp = ib_qp_get_drvdata ( qp ); - struct ib_work_queue *wq = &qp->recv; - struct arbel_recv_work_queue *arbel_recv_wq = &arbel_qp->recv; - struct arbelprm_recv_wqe *wqe; - union arbelprm_doorbell_record *db_rec; - unsigned int wqe_idx_mask; - - /* Allocate work queue entry */ - wqe_idx_mask = ( wq->num_wqes - 1 ); - if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) { - DBGC ( arbel, "Arbel %p receive queue full", arbel ); - return -ENOBUFS; - } - wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf; - wqe = &arbel_recv_wq->wqe[wq->next_idx & wqe_idx_mask].recv; - - /* Construct work queue entry */ - MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_tailroom ( iobuf ) ); - MLX_FILL_1 ( &wqe->data[0], 1, l_key, arbel->reserved_lkey ); - MLX_FILL_1 ( &wqe->data[0], 3, - local_address_l, virt_to_bus ( iobuf->data ) ); - - /* Update doorbell record */ - barrier(); - db_rec = &arbel->db_rec[arbel_recv_wq->doorbell_idx]; - MLX_FILL_1 ( &db_rec->qp, 0, - counter, ( ( wq->next_idx + 1 ) & 0xffff ) ); - - /* Update work queue's index */ - wq->next_idx++; - - return 0; -} - -/** - * Handle completion - * - * @v ibdev Infiniband device - * @v cq Completion queue - * @v cqe Hardware completion queue entry - * @ret rc Return status code - */ -static int arbel_complete ( struct ib_device *ibdev, - struct ib_completion_queue *cq, - union arbelprm_completion_entry *cqe ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct ib_work_queue *wq; - struct ib_queue_pair *qp; - struct arbel_queue_pair *arbel_qp; - struct arbel_send_work_queue *arbel_send_wq; - struct arbel_recv_work_queue *arbel_recv_wq; - struct arbelprm_recv_wqe *recv_wqe; - struct io_buffer *iobuf; - struct ib_address_vector av; - struct ib_global_route_header *grh; - unsigned int opcode; - unsigned long qpn; - int is_send; - unsigned long wqe_adr; - unsigned int wqe_idx; - size_t len; - int rc = 0; - - /* Parse completion */ - qpn = MLX_GET ( &cqe->normal, my_qpn ); - is_send = MLX_GET ( &cqe->normal, s ); - wqe_adr = ( MLX_GET ( &cqe->normal, wqe_adr ) << 6 ); - opcode = MLX_GET ( &cqe->normal, opcode ); - if ( opcode >= ARBEL_OPCODE_RECV_ERROR ) { - /* "s" field is not valid for error opcodes */ - is_send = ( opcode == ARBEL_OPCODE_SEND_ERROR ); - DBGC ( arbel, "Arbel %p CPN %lx syndrome %x vendor %x\n", - arbel, cq->cqn, MLX_GET ( &cqe->error, syndrome ), - MLX_GET ( &cqe->error, vendor_code ) ); - rc = -EIO; - /* Don't return immediately; propagate error to completer */ - } - - /* Identify work queue */ - wq = ib_find_wq ( cq, qpn, is_send ); - if ( ! wq ) { - DBGC ( arbel, "Arbel %p CQN %lx unknown %s QPN %lx\n", - arbel, cq->cqn, ( is_send ? "send" : "recv" ), qpn ); - return -EIO; - } - qp = wq->qp; - arbel_qp = ib_qp_get_drvdata ( qp ); - arbel_send_wq = &arbel_qp->send; - arbel_recv_wq = &arbel_qp->recv; - - /* Identify work queue entry index */ - if ( is_send ) { - wqe_idx = ( ( wqe_adr - virt_to_bus ( arbel_send_wq->wqe ) ) / - sizeof ( arbel_send_wq->wqe[0] ) ); - assert ( wqe_idx < qp->send.num_wqes ); - } else { - wqe_idx = ( ( wqe_adr - virt_to_bus ( arbel_recv_wq->wqe ) ) / - sizeof ( arbel_recv_wq->wqe[0] ) ); - assert ( wqe_idx < qp->recv.num_wqes ); - } - - /* Identify I/O buffer */ - iobuf = wq->iobufs[wqe_idx]; - if ( ! iobuf ) { - DBGC ( arbel, "Arbel %p CQN %lx QPN %lx empty WQE %x\n", - arbel, cq->cqn, qpn, wqe_idx ); - return -EIO; - } - wq->iobufs[wqe_idx] = NULL; - - if ( is_send ) { - /* Hand off to completion handler */ - ib_complete_send ( ibdev, qp, iobuf, rc ); - } else { - /* Set received length */ - len = MLX_GET ( &cqe->normal, byte_cnt ); - recv_wqe = &arbel_recv_wq->wqe[wqe_idx].recv; - assert ( MLX_GET ( &recv_wqe->data[0], local_address_l ) == - virt_to_bus ( iobuf->data ) ); - assert ( MLX_GET ( &recv_wqe->data[0], byte_count ) == - iob_tailroom ( iobuf ) ); - MLX_FILL_1 ( &recv_wqe->data[0], 0, byte_count, 0 ); - MLX_FILL_1 ( &recv_wqe->data[0], 1, - l_key, ARBEL_INVALID_LKEY ); - assert ( len <= iob_tailroom ( iobuf ) ); - iob_put ( iobuf, len ); - assert ( iob_len ( iobuf ) >= sizeof ( *grh ) ); - grh = iobuf->data; - iob_pull ( iobuf, sizeof ( *grh ) ); - /* Construct address vector */ - memset ( &av, 0, sizeof ( av ) ); - av.qpn = MLX_GET ( &cqe->normal, rqpn ); - av.lid = MLX_GET ( &cqe->normal, rlid ); - av.sl = MLX_GET ( &cqe->normal, sl ); - av.gid_present = MLX_GET ( &cqe->normal, g ); - memcpy ( &av.gid, &grh->sgid, sizeof ( av.gid ) ); - /* Hand off to completion handler */ - ib_complete_recv ( ibdev, qp, &av, iobuf, rc ); - } - - return rc; -} - -/** - * Poll completion queue - * - * @v ibdev Infiniband device - * @v cq Completion queue - */ -static void arbel_poll_cq ( struct ib_device *ibdev, - struct ib_completion_queue *cq ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbel_completion_queue *arbel_cq = ib_cq_get_drvdata ( cq ); - struct arbelprm_cq_ci_db_record *ci_db_rec; - union arbelprm_completion_entry *cqe; - unsigned int cqe_idx_mask; - int rc; - - while ( 1 ) { - /* Look for completion entry */ - cqe_idx_mask = ( cq->num_cqes - 1 ); - cqe = &arbel_cq->cqe[cq->next_idx & cqe_idx_mask]; - if ( MLX_GET ( &cqe->normal, owner ) != 0 ) { - /* Entry still owned by hardware; end of poll */ - break; - } - - /* Handle completion */ - if ( ( rc = arbel_complete ( ibdev, cq, cqe ) ) != 0 ) { - DBGC ( arbel, "Arbel %p failed to complete: %s\n", - arbel, strerror ( rc ) ); - DBGC_HD ( arbel, cqe, sizeof ( *cqe ) ); - } - - /* Return ownership to hardware */ - MLX_FILL_1 ( &cqe->normal, 7, owner, 1 ); - barrier(); - /* Update completion queue's index */ - cq->next_idx++; - /* Update doorbell record */ - ci_db_rec = &arbel->db_rec[arbel_cq->ci_doorbell_idx].cq_ci; - MLX_FILL_1 ( ci_db_rec, 0, - counter, ( cq->next_idx & 0xffffffffUL ) ); - } -} - -/*************************************************************************** - * - * Event queues - * - *************************************************************************** - */ - -/** - * Create event queue - * - * @v arbel Arbel device - * @ret rc Return status code - */ -static int arbel_create_eq ( struct arbel *arbel ) { - struct arbel_event_queue *arbel_eq = &arbel->eq; - struct arbelprm_eqc eqctx; - struct arbelprm_event_mask mask; - unsigned int i; - int rc; - - /* Select event queue number */ - arbel_eq->eqn = arbel->limits.reserved_eqs; - - /* Calculate doorbell address */ - arbel_eq->doorbell = ( arbel->eq_ci_doorbells + - ARBEL_DB_EQ_OFFSET ( arbel_eq->eqn ) ); - - /* Allocate event queue itself */ - arbel_eq->eqe_size = - ( ARBEL_NUM_EQES * sizeof ( arbel_eq->eqe[0] ) ); - arbel_eq->eqe = malloc_dma ( arbel_eq->eqe_size, - sizeof ( arbel_eq->eqe[0] ) ); - if ( ! arbel_eq->eqe ) { - rc = -ENOMEM; - goto err_eqe; - } - memset ( arbel_eq->eqe, 0, arbel_eq->eqe_size ); - for ( i = 0 ; i < ARBEL_NUM_EQES ; i++ ) { - MLX_FILL_1 ( &arbel_eq->eqe[i].generic, 7, owner, 1 ); - } - barrier(); - - /* Hand queue over to hardware */ - memset ( &eqctx, 0, sizeof ( eqctx ) ); - MLX_FILL_1 ( &eqctx, 0, st, 0xa /* "Fired" */ ); - MLX_FILL_1 ( &eqctx, 2, - start_address_l, virt_to_phys ( arbel_eq->eqe ) ); - MLX_FILL_1 ( &eqctx, 3, log_eq_size, fls ( ARBEL_NUM_EQES - 1 ) ); - MLX_FILL_1 ( &eqctx, 6, pd, ARBEL_GLOBAL_PD ); - MLX_FILL_1 ( &eqctx, 7, lkey, arbel->reserved_lkey ); - if ( ( rc = arbel_cmd_sw2hw_eq ( arbel, arbel_eq->eqn, - &eqctx ) ) != 0 ) { - DBGC ( arbel, "Arbel %p SW2HW_EQ failed: %s\n", - arbel, strerror ( rc ) ); - goto err_sw2hw_eq; - } - - /* Map events to this event queue */ - memset ( &mask, 0, sizeof ( mask ) ); - MLX_FILL_1 ( &mask, 1, port_state_change, 1 ); - if ( ( rc = arbel_cmd_map_eq ( arbel, - ( ARBEL_MAP_EQ | arbel_eq->eqn ), - &mask ) ) != 0 ) { - DBGC ( arbel, "Arbel %p MAP_EQ failed: %s\n", - arbel, strerror ( rc ) ); - goto err_map_eq; - } - - DBGC ( arbel, "Arbel %p EQN %#lx ring at [%p,%p])\n", - arbel, arbel_eq->eqn, arbel_eq->eqe, - ( ( ( void * ) arbel_eq->eqe ) + arbel_eq->eqe_size ) ); - return 0; - - err_map_eq: - arbel_cmd_hw2sw_eq ( arbel, arbel_eq->eqn, &eqctx ); - err_sw2hw_eq: - free_dma ( arbel_eq->eqe, arbel_eq->eqe_size ); - err_eqe: - memset ( arbel_eq, 0, sizeof ( *arbel_eq ) ); - return rc; -} - -/** - * Destroy event queue - * - * @v arbel Arbel device - */ -static void arbel_destroy_eq ( struct arbel *arbel ) { - struct arbel_event_queue *arbel_eq = &arbel->eq; - struct arbelprm_eqc eqctx; - struct arbelprm_event_mask mask; - int rc; - - /* Unmap events from event queue */ - memset ( &mask, 0, sizeof ( mask ) ); - MLX_FILL_1 ( &mask, 1, port_state_change, 1 ); - if ( ( rc = arbel_cmd_map_eq ( arbel, - ( ARBEL_UNMAP_EQ | arbel_eq->eqn ), - &mask ) ) != 0 ) { - DBGC ( arbel, "Arbel %p FATAL MAP_EQ failed to unmap: %s\n", - arbel, strerror ( rc ) ); - /* Continue; HCA may die but system should survive */ - } - - /* Take ownership back from hardware */ - if ( ( rc = arbel_cmd_hw2sw_eq ( arbel, arbel_eq->eqn, - &eqctx ) ) != 0 ) { - DBGC ( arbel, "Arbel %p FATAL HW2SW_EQ failed: %s\n", - arbel, strerror ( rc ) ); - /* Leak memory and return; at least we avoid corruption */ - return; - } - - /* Free memory */ - free_dma ( arbel_eq->eqe, arbel_eq->eqe_size ); - memset ( arbel_eq, 0, sizeof ( *arbel_eq ) ); -} - -/** - * Handle port state event - * - * @v arbel Arbel device - * @v eqe Port state change event queue entry - */ -static void arbel_event_port_state_change ( struct arbel *arbel, - union arbelprm_event_entry *eqe){ - unsigned int port; - int link_up; - - /* Get port and link status */ - port = ( MLX_GET ( &eqe->port_state_change, data.p ) - 1 ); - link_up = ( MLX_GET ( &eqe->generic, event_sub_type ) & 0x04 ); - DBGC ( arbel, "Arbel %p port %d link %s\n", arbel, ( port + 1 ), - ( link_up ? "up" : "down" ) ); - - /* Sanity check */ - if ( port >= ARBEL_NUM_PORTS ) { - DBGC ( arbel, "Arbel %p port %d does not exist!\n", - arbel, ( port + 1 ) ); - return; - } - - /* Update MAD parameters */ - ib_smc_update ( arbel->ibdev[port], arbel_mad ); - - /* Notify Infiniband core of link state change */ - ib_link_state_changed ( arbel->ibdev[port] ); -} - -/** - * Poll event queue - * - * @v ibdev Infiniband device - */ -static void arbel_poll_eq ( struct ib_device *ibdev ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbel_event_queue *arbel_eq = &arbel->eq; - union arbelprm_event_entry *eqe; - union arbelprm_eq_doorbell_register db_reg; - unsigned int eqe_idx_mask; - unsigned int event_type; - - while ( 1 ) { - /* Look for event entry */ - eqe_idx_mask = ( ARBEL_NUM_EQES - 1 ); - eqe = &arbel_eq->eqe[arbel_eq->next_idx & eqe_idx_mask]; - if ( MLX_GET ( &eqe->generic, owner ) != 0 ) { - /* Entry still owned by hardware; end of poll */ - break; - } - DBGCP ( arbel, "Arbel %p event:\n", arbel ); - DBGCP_HD ( arbel, eqe, sizeof ( *eqe ) ); - - /* Handle event */ - event_type = MLX_GET ( &eqe->generic, event_type ); - switch ( event_type ) { - case ARBEL_EV_PORT_STATE_CHANGE: - arbel_event_port_state_change ( arbel, eqe ); - break; - default: - DBGC ( arbel, "Arbel %p unrecognised event type " - "%#x:\n", arbel, event_type ); - DBGC_HD ( arbel, eqe, sizeof ( *eqe ) ); - break; - } - - /* Return ownership to hardware */ - MLX_FILL_1 ( &eqe->generic, 7, owner, 1 ); - barrier(); - - /* Update event queue's index */ - arbel_eq->next_idx++; - - /* Ring doorbell */ - MLX_FILL_1 ( &db_reg.ci, 0, ci, arbel_eq->next_idx ); - DBGCP ( arbel, "Ringing doorbell %08lx with %08x\n", - virt_to_phys ( arbel_eq->doorbell ), - db_reg.dword[0] ); - writel ( db_reg.dword[0], arbel_eq->doorbell ); - } -} - -/*************************************************************************** - * - * Infiniband link-layer operations - * - *************************************************************************** - */ - -/** - * Initialise Infiniband link - * - * @v ibdev Infiniband device - * @ret rc Return status code - */ -static int arbel_open ( struct ib_device *ibdev ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbelprm_init_ib init_ib; - int rc; - - memset ( &init_ib, 0, sizeof ( init_ib ) ); - MLX_FILL_3 ( &init_ib, 0, - mtu_cap, ARBEL_MTU_2048, - port_width_cap, 3, - vl_cap, 1 ); - MLX_FILL_1 ( &init_ib, 1, max_gid, 1 ); - MLX_FILL_1 ( &init_ib, 2, max_pkey, 64 ); - if ( ( rc = arbel_cmd_init_ib ( arbel, ibdev->port, - &init_ib ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not intialise IB: %s\n", - arbel, strerror ( rc ) ); - return rc; - } - - /* Update MAD parameters */ - ib_smc_update ( ibdev, arbel_mad ); - - return 0; -} - -/** - * Close Infiniband link - * - * @v ibdev Infiniband device - */ -static void arbel_close ( struct ib_device *ibdev ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - int rc; - - if ( ( rc = arbel_cmd_close_ib ( arbel, ibdev->port ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not close IB: %s\n", - arbel, strerror ( rc ) ); - /* Nothing we can do about this */ - } -} - -/*************************************************************************** - * - * Multicast group operations - * - *************************************************************************** - */ - -/** - * Attach to multicast group - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v gid Multicast GID - * @ret rc Return status code - */ -static int arbel_mcast_attach ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct ib_gid *gid ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbelprm_mgm_hash hash; - struct arbelprm_mgm_entry mgm; - unsigned int index; - int rc; - - /* Generate hash table index */ - if ( ( rc = arbel_cmd_mgid_hash ( arbel, gid, &hash ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not hash GID: %s\n", - arbel, strerror ( rc ) ); - return rc; - } - index = MLX_GET ( &hash, hash ); - - /* Check for existing hash table entry */ - if ( ( rc = arbel_cmd_read_mgm ( arbel, index, &mgm ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not read MGM %#x: %s\n", - arbel, index, strerror ( rc ) ); - return rc; - } - if ( MLX_GET ( &mgm, mgmqp_0.qi ) != 0 ) { - /* FIXME: this implementation allows only a single QP - * per multicast group, and doesn't handle hash - * collisions. Sufficient for IPoIB but may need to - * be extended in future. - */ - DBGC ( arbel, "Arbel %p MGID index %#x already in use\n", - arbel, index ); - return -EBUSY; - } - - /* Update hash table entry */ - MLX_FILL_2 ( &mgm, 8, - mgmqp_0.qpn_i, qp->qpn, - mgmqp_0.qi, 1 ); - memcpy ( &mgm.u.dwords[4], gid, sizeof ( *gid ) ); - if ( ( rc = arbel_cmd_write_mgm ( arbel, index, &mgm ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not write MGM %#x: %s\n", - arbel, index, strerror ( rc ) ); - return rc; - } - - return 0; -} - -/** - * Detach from multicast group - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v gid Multicast GID - */ -static void arbel_mcast_detach ( struct ib_device *ibdev, - struct ib_queue_pair *qp __unused, - struct ib_gid *gid ) { - struct arbel *arbel = ib_get_drvdata ( ibdev ); - struct arbelprm_mgm_hash hash; - struct arbelprm_mgm_entry mgm; - unsigned int index; - int rc; - - /* Generate hash table index */ - if ( ( rc = arbel_cmd_mgid_hash ( arbel, gid, &hash ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not hash GID: %s\n", - arbel, strerror ( rc ) ); - return; - } - index = MLX_GET ( &hash, hash ); - - /* Clear hash table entry */ - memset ( &mgm, 0, sizeof ( mgm ) ); - if ( ( rc = arbel_cmd_write_mgm ( arbel, index, &mgm ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not write MGM %#x: %s\n", - arbel, index, strerror ( rc ) ); - return; - } -} - -/** Arbel Infiniband operations */ -static struct ib_device_operations arbel_ib_operations = { - .create_cq = arbel_create_cq, - .destroy_cq = arbel_destroy_cq, - .create_qp = arbel_create_qp, - .modify_qp = arbel_modify_qp, - .destroy_qp = arbel_destroy_qp, - .post_send = arbel_post_send, - .post_recv = arbel_post_recv, - .poll_cq = arbel_poll_cq, - .poll_eq = arbel_poll_eq, - .open = arbel_open, - .close = arbel_close, - .mcast_attach = arbel_mcast_attach, - .mcast_detach = arbel_mcast_detach, -}; - -/*************************************************************************** - * - * Firmware control - * - *************************************************************************** - */ - -/** - * Start firmware running - * - * @v arbel Arbel device - * @ret rc Return status code - */ -static int arbel_start_firmware ( struct arbel *arbel ) { - struct arbelprm_query_fw fw; - struct arbelprm_access_lam lam; - struct arbelprm_virtual_physical_mapping map_fa; - unsigned int fw_pages; - unsigned int log2_fw_pages; - size_t fw_size; - physaddr_t fw_base; - uint64_t eq_set_ci_base_addr; - int rc; - - /* Get firmware parameters */ - if ( ( rc = arbel_cmd_query_fw ( arbel, &fw ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not query firmware: %s\n", - arbel, strerror ( rc ) ); - goto err_query_fw; - } - DBGC ( arbel, "Arbel %p firmware version %d.%d.%d\n", arbel, - MLX_GET ( &fw, fw_rev_major ), MLX_GET ( &fw, fw_rev_minor ), - MLX_GET ( &fw, fw_rev_subminor ) ); - fw_pages = MLX_GET ( &fw, fw_pages ); - log2_fw_pages = fls ( fw_pages - 1 ); - fw_pages = ( 1 << log2_fw_pages ); - DBGC ( arbel, "Arbel %p requires %d kB for firmware\n", - arbel, ( fw_pages * 4 ) ); - eq_set_ci_base_addr = - ( ( (uint64_t) MLX_GET ( &fw, eq_set_ci_base_addr_h ) << 32 ) | - ( (uint64_t) MLX_GET ( &fw, eq_set_ci_base_addr_l ) ) ); - arbel->eq_ci_doorbells = ioremap ( eq_set_ci_base_addr, 0x200 ); - - /* Enable locally-attached memory. Ignore failure; there may - * be no attached memory. - */ - arbel_cmd_enable_lam ( arbel, &lam ); - - /* Allocate firmware pages and map firmware area */ - fw_size = ( fw_pages * 4096 ); - arbel->firmware_area = umalloc ( fw_size * 2 ); - if ( ! arbel->firmware_area ) { - rc = -ENOMEM; - goto err_alloc_fa; - } - fw_base = ( user_to_phys ( arbel->firmware_area, fw_size ) & - ~( fw_size - 1 ) ); - DBGC ( arbel, "Arbel %p firmware area at physical [%lx,%lx)\n", - arbel, fw_base, ( fw_base + fw_size ) ); - memset ( &map_fa, 0, sizeof ( map_fa ) ); - MLX_FILL_2 ( &map_fa, 3, - log2size, log2_fw_pages, - pa_l, ( fw_base >> 12 ) ); - if ( ( rc = arbel_cmd_map_fa ( arbel, &map_fa ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not map firmware: %s\n", - arbel, strerror ( rc ) ); - goto err_map_fa; - } - - /* Start firmware */ - if ( ( rc = arbel_cmd_run_fw ( arbel ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not run firmware: %s\n", - arbel, strerror ( rc ) ); - goto err_run_fw; - } - - DBGC ( arbel, "Arbel %p firmware started\n", arbel ); - return 0; - - err_run_fw: - arbel_cmd_unmap_fa ( arbel ); - err_map_fa: - ufree ( arbel->firmware_area ); - arbel->firmware_area = UNULL; - err_alloc_fa: - err_query_fw: - return rc; -} - -/** - * Stop firmware running - * - * @v arbel Arbel device - */ -static void arbel_stop_firmware ( struct arbel *arbel ) { - int rc; - - if ( ( rc = arbel_cmd_unmap_fa ( arbel ) ) != 0 ) { - DBGC ( arbel, "Arbel %p FATAL could not stop firmware: %s\n", - arbel, strerror ( rc ) ); - /* Leak memory and return; at least we avoid corruption */ - return; - } - ufree ( arbel->firmware_area ); - arbel->firmware_area = UNULL; -} - -/*************************************************************************** - * - * Infinihost Context Memory management - * - *************************************************************************** - */ - -/** - * Get device limits - * - * @v arbel Arbel device - * @ret rc Return status code - */ -static int arbel_get_limits ( struct arbel *arbel ) { - struct arbelprm_query_dev_lim dev_lim; - int rc; - - if ( ( rc = arbel_cmd_query_dev_lim ( arbel, &dev_lim ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not get device limits: %s\n", - arbel, strerror ( rc ) ); - return rc; - } - - arbel->limits.reserved_qps = - ( 1 << MLX_GET ( &dev_lim, log2_rsvd_qps ) ); - arbel->limits.qpc_entry_size = MLX_GET ( &dev_lim, qpc_entry_sz ); - arbel->limits.eqpc_entry_size = MLX_GET ( &dev_lim, eqpc_entry_sz ); - arbel->limits.reserved_srqs = - ( 1 << MLX_GET ( &dev_lim, log2_rsvd_srqs ) ); - arbel->limits.srqc_entry_size = MLX_GET ( &dev_lim, srq_entry_sz ); - arbel->limits.reserved_ees = - ( 1 << MLX_GET ( &dev_lim, log2_rsvd_ees ) ); - arbel->limits.eec_entry_size = MLX_GET ( &dev_lim, eec_entry_sz ); - arbel->limits.eeec_entry_size = MLX_GET ( &dev_lim, eeec_entry_sz ); - arbel->limits.reserved_cqs = - ( 1 << MLX_GET ( &dev_lim, log2_rsvd_cqs ) ); - arbel->limits.cqc_entry_size = MLX_GET ( &dev_lim, cqc_entry_sz ); - arbel->limits.reserved_eqs = MLX_GET ( &dev_lim, num_rsvd_eqs ); - arbel->limits.reserved_mtts = - ( 1 << MLX_GET ( &dev_lim, log2_rsvd_mtts ) ); - arbel->limits.mtt_entry_size = MLX_GET ( &dev_lim, mtt_entry_sz ); - arbel->limits.reserved_mrws = - ( 1 << MLX_GET ( &dev_lim, log2_rsvd_mrws ) ); - arbel->limits.mpt_entry_size = MLX_GET ( &dev_lim, mpt_entry_sz ); - arbel->limits.reserved_rdbs = - ( 1 << MLX_GET ( &dev_lim, log2_rsvd_rdbs ) ); - arbel->limits.eqc_entry_size = MLX_GET ( &dev_lim, eqc_entry_sz ); - arbel->limits.reserved_uars = MLX_GET ( &dev_lim, num_rsvd_uars ); - - return 0; -} - -/** - * Get ICM usage - * - * @v log_num_entries Log2 of the number of entries - * @v entry_size Entry size - * @ret usage Usage size in ICM - */ -static size_t icm_usage ( unsigned int log_num_entries, size_t entry_size ) { - size_t usage; - - usage = ( ( 1 << log_num_entries ) * entry_size ); - usage = ( ( usage + 4095 ) & ~4095 ); - return usage; -} - -/** - * Allocate ICM - * - * @v arbel Arbel device - * @v init_hca INIT_HCA structure to fill in - * @ret rc Return status code - */ -static int arbel_alloc_icm ( struct arbel *arbel, - struct arbelprm_init_hca *init_hca ) { - struct arbelprm_scalar_parameter icm_size; - struct arbelprm_scalar_parameter icm_aux_size; - struct arbelprm_virtual_physical_mapping map_icm_aux; - struct arbelprm_virtual_physical_mapping map_icm; - union arbelprm_doorbell_record *db_rec; - size_t icm_offset = 0; - unsigned int log_num_qps, log_num_srqs, log_num_ees, log_num_cqs; - unsigned int log_num_mtts, log_num_mpts, log_num_rdbs, log_num_eqs; - int rc; - - icm_offset = ( ( arbel->limits.reserved_uars + 1 ) << 12 ); - - /* Queue pair contexts */ - log_num_qps = fls ( arbel->limits.reserved_qps + ARBEL_MAX_QPS - 1 ); - MLX_FILL_2 ( init_hca, 13, - qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_l, - ( icm_offset >> 7 ), - qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp, - log_num_qps ); - DBGC ( arbel, "Arbel %p ICM QPC base = %zx\n", arbel, icm_offset ); - icm_offset += icm_usage ( log_num_qps, arbel->limits.qpc_entry_size ); - - /* Extended queue pair contexts */ - MLX_FILL_1 ( init_hca, 25, - qpc_eec_cqc_eqc_rdb_parameters.eqpc_base_addr_l, - icm_offset ); - DBGC ( arbel, "Arbel %p ICM EQPC base = %zx\n", arbel, icm_offset ); - // icm_offset += icm_usage ( log_num_qps, arbel->limits.eqpc_entry_size ); - icm_offset += icm_usage ( log_num_qps, arbel->limits.qpc_entry_size ); - - /* Shared receive queue contexts */ - log_num_srqs = fls ( arbel->limits.reserved_srqs - 1 ); - MLX_FILL_2 ( init_hca, 19, - qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_l, - ( icm_offset >> 5 ), - qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq, - log_num_srqs ); - DBGC ( arbel, "Arbel %p ICM SRQC base = %zx\n", arbel, icm_offset ); - icm_offset += icm_usage ( log_num_srqs, arbel->limits.srqc_entry_size ); - - /* End-to-end contexts */ - log_num_ees = fls ( arbel->limits.reserved_ees - 1 ); - MLX_FILL_2 ( init_hca, 17, - qpc_eec_cqc_eqc_rdb_parameters.eec_base_addr_l, - ( icm_offset >> 7 ), - qpc_eec_cqc_eqc_rdb_parameters.log_num_of_ee, - log_num_ees ); - DBGC ( arbel, "Arbel %p ICM EEC base = %zx\n", arbel, icm_offset ); - icm_offset += icm_usage ( log_num_ees, arbel->limits.eec_entry_size ); - - /* Extended end-to-end contexts */ - MLX_FILL_1 ( init_hca, 29, - qpc_eec_cqc_eqc_rdb_parameters.eeec_base_addr_l, - icm_offset ); - DBGC ( arbel, "Arbel %p ICM EEEC base = %zx\n", arbel, icm_offset ); - icm_offset += icm_usage ( log_num_ees, arbel->limits.eeec_entry_size ); - - /* Completion queue contexts */ - log_num_cqs = fls ( arbel->limits.reserved_cqs + ARBEL_MAX_CQS - 1 ); - MLX_FILL_2 ( init_hca, 21, - qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_l, - ( icm_offset >> 6 ), - qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq, - log_num_cqs ); - DBGC ( arbel, "Arbel %p ICM CQC base = %zx\n", arbel, icm_offset ); - icm_offset += icm_usage ( log_num_cqs, arbel->limits.cqc_entry_size ); - - /* Memory translation table */ - log_num_mtts = fls ( arbel->limits.reserved_mtts - 1 ); - MLX_FILL_1 ( init_hca, 65, - tpt_parameters.mtt_base_addr_l, icm_offset ); - DBGC ( arbel, "Arbel %p ICM MTT base = %zx\n", arbel, icm_offset ); - icm_offset += icm_usage ( log_num_mtts, arbel->limits.mtt_entry_size ); - - /* Memory protection table */ - log_num_mpts = fls ( arbel->limits.reserved_mrws + 1 - 1 ); - MLX_FILL_1 ( init_hca, 61, - tpt_parameters.mpt_base_adr_l, icm_offset ); - MLX_FILL_1 ( init_hca, 62, - tpt_parameters.log_mpt_sz, log_num_mpts ); - DBGC ( arbel, "Arbel %p ICM MTT base = %zx\n", arbel, icm_offset ); - icm_offset += icm_usage ( log_num_mpts, arbel->limits.mpt_entry_size ); - - /* RDMA something or other */ - log_num_rdbs = fls ( arbel->limits.reserved_rdbs - 1 ); - MLX_FILL_1 ( init_hca, 37, - qpc_eec_cqc_eqc_rdb_parameters.rdb_base_addr_l, - icm_offset ); - DBGC ( arbel, "Arbel %p ICM RDB base = %zx\n", arbel, icm_offset ); - icm_offset += icm_usage ( log_num_rdbs, 32 ); - - /* Event queue contexts */ - log_num_eqs = fls ( arbel->limits.reserved_eqs + ARBEL_MAX_EQS - 1 ); - MLX_FILL_2 ( init_hca, 33, - qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_l, - ( icm_offset >> 6 ), - qpc_eec_cqc_eqc_rdb_parameters.log_num_eq, - log_num_eqs ); - DBGC ( arbel, "Arbel %p ICM EQ base = %zx\n", arbel, icm_offset ); - icm_offset += ( ( 1 << log_num_eqs ) * arbel->limits.eqc_entry_size ); - - /* Multicast table */ - MLX_FILL_1 ( init_hca, 49, - multicast_parameters.mc_base_addr_l, icm_offset ); - MLX_FILL_1 ( init_hca, 52, - multicast_parameters.log_mc_table_entry_sz, - fls ( sizeof ( struct arbelprm_mgm_entry ) - 1 ) ); - MLX_FILL_1 ( init_hca, 53, - multicast_parameters.mc_table_hash_sz, 8 ); - MLX_FILL_1 ( init_hca, 54, - multicast_parameters.log_mc_table_sz, 3 ); - DBGC ( arbel, "Arbel %p ICM MC base = %zx\n", arbel, icm_offset ); - icm_offset += ( 8 * sizeof ( struct arbelprm_mgm_entry ) ); - - arbel->icm_len = icm_offset; - arbel->icm_len = ( ( arbel->icm_len + 4095 ) & ~4095 ); - - /* Get ICM auxiliary area size */ - memset ( &icm_size, 0, sizeof ( icm_size ) ); - MLX_FILL_1 ( &icm_size, 1, value, arbel->icm_len ); - if ( ( rc = arbel_cmd_set_icm_size ( arbel, &icm_size, - &icm_aux_size ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not set ICM size: %s\n", - arbel, strerror ( rc ) ); - goto err_set_icm_size; - } - arbel->icm_aux_len = ( MLX_GET ( &icm_aux_size, value ) * 4096 ); - - /* Allocate ICM data and auxiliary area */ - DBGC ( arbel, "Arbel %p requires %zd kB ICM and %zd kB AUX ICM\n", - arbel, ( arbel->icm_len / 1024 ), - ( arbel->icm_aux_len / 1024 ) ); - arbel->icm = umalloc ( arbel->icm_len + arbel->icm_aux_len ); - if ( ! arbel->icm ) { - rc = -ENOMEM; - goto err_alloc; - } - - /* Map ICM auxiliary area */ - memset ( &map_icm_aux, 0, sizeof ( map_icm_aux ) ); - MLX_FILL_2 ( &map_icm_aux, 3, - log2size, fls ( ( arbel->icm_aux_len / 4096 ) - 1 ), - pa_l, - ( user_to_phys ( arbel->icm, arbel->icm_len ) >> 12 ) ); - if ( ( rc = arbel_cmd_map_icm_aux ( arbel, &map_icm_aux ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not map AUX ICM: %s\n", - arbel, strerror ( rc ) ); - goto err_map_icm_aux; - } - - /* MAP ICM area */ - memset ( &map_icm, 0, sizeof ( map_icm ) ); - MLX_FILL_2 ( &map_icm, 3, - log2size, fls ( ( arbel->icm_len / 4096 ) - 1 ), - pa_l, ( user_to_phys ( arbel->icm, 0 ) >> 12 ) ); - if ( ( rc = arbel_cmd_map_icm ( arbel, &map_icm ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not map ICM: %s\n", - arbel, strerror ( rc ) ); - goto err_map_icm; - } - - /* Initialise UAR context */ - arbel->db_rec = phys_to_virt ( user_to_phys ( arbel->icm, 0 ) + - ( arbel->limits.reserved_uars * - ARBEL_PAGE_SIZE ) ); - memset ( arbel->db_rec, 0, ARBEL_PAGE_SIZE ); - db_rec = &arbel->db_rec[ARBEL_GROUP_SEPARATOR_DOORBELL]; - MLX_FILL_1 ( &db_rec->qp, 1, res, ARBEL_UAR_RES_GROUP_SEP ); - - return 0; - - arbel_cmd_unmap_icm ( arbel, ( arbel->icm_len / 4096 ) ); - err_map_icm: - arbel_cmd_unmap_icm_aux ( arbel ); - err_map_icm_aux: - ufree ( arbel->icm ); - arbel->icm = UNULL; - err_alloc: - err_set_icm_size: - return rc; -} - -/** - * Free ICM - * - * @v arbel Arbel device - */ -static void arbel_free_icm ( struct arbel *arbel ) { - arbel_cmd_unmap_icm ( arbel, ( arbel->icm_len / 4096 ) ); - arbel_cmd_unmap_icm_aux ( arbel ); - ufree ( arbel->icm ); - arbel->icm = UNULL; -} - -/*************************************************************************** - * - * PCI interface - * - *************************************************************************** - */ - -/** - * Set up memory protection table - * - * @v arbel Arbel device - * @ret rc Return status code - */ -static int arbel_setup_mpt ( struct arbel *arbel ) { - struct arbelprm_mpt mpt; - uint32_t key; - int rc; - - /* Derive key */ - key = ( arbel->limits.reserved_mrws | ARBEL_MKEY_PREFIX ); - arbel->reserved_lkey = ( ( key << 8 ) | ( key >> 24 ) ); - - /* Initialise memory protection table */ - memset ( &mpt, 0, sizeof ( mpt ) ); - MLX_FILL_4 ( &mpt, 0, - r_w, 1, - pa, 1, - lr, 1, - lw, 1 ); - MLX_FILL_1 ( &mpt, 2, mem_key, key ); - MLX_FILL_1 ( &mpt, 3, pd, ARBEL_GLOBAL_PD ); - MLX_FILL_1 ( &mpt, 6, reg_wnd_len_h, 0xffffffffUL ); - MLX_FILL_1 ( &mpt, 7, reg_wnd_len_l, 0xffffffffUL ); - if ( ( rc = arbel_cmd_sw2hw_mpt ( arbel, arbel->limits.reserved_mrws, - &mpt ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not set up MPT: %s\n", - arbel, strerror ( rc ) ); - return rc; - } - - return 0; -} - -/** - * Probe PCI device - * - * @v pci PCI device - * @v id PCI ID - * @ret rc Return status code - */ -static int arbel_probe ( struct pci_device *pci, - const struct pci_device_id *id __unused ) { - struct arbel *arbel; - struct ib_device *ibdev; - struct arbelprm_init_hca init_hca; - int i; - int rc; - - /* Allocate Arbel device */ - arbel = zalloc ( sizeof ( *arbel ) ); - if ( ! arbel ) { - rc = -ENOMEM; - goto err_alloc_arbel; - } - pci_set_drvdata ( pci, arbel ); - - /* Allocate Infiniband devices */ - for ( i = 0 ; i < ARBEL_NUM_PORTS ; i++ ) { - ibdev = alloc_ibdev ( 0 ); - if ( ! ibdev ) { - rc = -ENOMEM; - goto err_alloc_ibdev; - } - arbel->ibdev[i] = ibdev; - ibdev->op = &arbel_ib_operations; - ibdev->dev = &pci->dev; - ibdev->port = ( ARBEL_PORT_BASE + i ); - ib_set_drvdata ( ibdev, arbel ); - } - - /* Fix up PCI device */ - adjust_pci_device ( pci ); - - /* Get PCI BARs */ - arbel->config = ioremap ( pci_bar_start ( pci, ARBEL_PCI_CONFIG_BAR ), - ARBEL_PCI_CONFIG_BAR_SIZE ); - arbel->uar = ioremap ( ( pci_bar_start ( pci, ARBEL_PCI_UAR_BAR ) + - ARBEL_PCI_UAR_IDX * ARBEL_PCI_UAR_SIZE ), - ARBEL_PCI_UAR_SIZE ); - - /* Allocate space for mailboxes */ - arbel->mailbox_in = malloc_dma ( ARBEL_MBOX_SIZE, ARBEL_MBOX_ALIGN ); - if ( ! arbel->mailbox_in ) { - rc = -ENOMEM; - goto err_mailbox_in; - } - arbel->mailbox_out = malloc_dma ( ARBEL_MBOX_SIZE, ARBEL_MBOX_ALIGN ); - if ( ! arbel->mailbox_out ) { - rc = -ENOMEM; - goto err_mailbox_out; - } - - /* Start firmware */ - if ( ( rc = arbel_start_firmware ( arbel ) ) != 0 ) - goto err_start_firmware; - - /* Get device limits */ - if ( ( rc = arbel_get_limits ( arbel ) ) != 0 ) - goto err_get_limits; - - /* Allocate ICM */ - memset ( &init_hca, 0, sizeof ( init_hca ) ); - if ( ( rc = arbel_alloc_icm ( arbel, &init_hca ) ) != 0 ) - goto err_alloc_icm; - - /* Initialise HCA */ - MLX_FILL_1 ( &init_hca, 74, uar_parameters.log_max_uars, 1 ); - if ( ( rc = arbel_cmd_init_hca ( arbel, &init_hca ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not initialise HCA: %s\n", - arbel, strerror ( rc ) ); - goto err_init_hca; - } - - /* Set up memory protection */ - if ( ( rc = arbel_setup_mpt ( arbel ) ) != 0 ) - goto err_setup_mpt; - - /* Set up event queue */ - if ( ( rc = arbel_create_eq ( arbel ) ) != 0 ) - goto err_create_eq; - - /* Update MAD parameters */ - for ( i = 0 ; i < ARBEL_NUM_PORTS ; i++ ) - ib_smc_update ( arbel->ibdev[i], arbel_mad ); - - /* Register Infiniband devices */ - for ( i = 0 ; i < ARBEL_NUM_PORTS ; i++ ) { - if ( ( rc = register_ibdev ( arbel->ibdev[i] ) ) != 0 ) { - DBGC ( arbel, "Arbel %p could not register IB " - "device: %s\n", arbel, strerror ( rc ) ); - goto err_register_ibdev; - } - } - - return 0; - - i = ARBEL_NUM_PORTS; - err_register_ibdev: - for ( i-- ; i >= 0 ; i-- ) - unregister_ibdev ( arbel->ibdev[i] ); - arbel_destroy_eq ( arbel ); - err_create_eq: - err_setup_mpt: - arbel_cmd_close_hca ( arbel ); - err_init_hca: - arbel_free_icm ( arbel ); - err_alloc_icm: - err_get_limits: - arbel_stop_firmware ( arbel ); - err_start_firmware: - free_dma ( arbel->mailbox_out, ARBEL_MBOX_SIZE ); - err_mailbox_out: - free_dma ( arbel->mailbox_in, ARBEL_MBOX_SIZE ); - err_mailbox_in: - i = ARBEL_NUM_PORTS; - err_alloc_ibdev: - for ( i-- ; i >= 0 ; i-- ) - ibdev_put ( arbel->ibdev[i] ); - free ( arbel ); - err_alloc_arbel: - return rc; -} - -/** - * Remove PCI device - * - * @v pci PCI device - */ -static void arbel_remove ( struct pci_device *pci ) { - struct arbel *arbel = pci_get_drvdata ( pci ); - int i; - - for ( i = ( ARBEL_NUM_PORTS - 1 ) ; i >= 0 ; i-- ) - unregister_ibdev ( arbel->ibdev[i] ); - arbel_destroy_eq ( arbel ); - arbel_cmd_close_hca ( arbel ); - arbel_free_icm ( arbel ); - arbel_stop_firmware ( arbel ); - arbel_stop_firmware ( arbel ); - free_dma ( arbel->mailbox_out, ARBEL_MBOX_SIZE ); - free_dma ( arbel->mailbox_in, ARBEL_MBOX_SIZE ); - for ( i = ( ARBEL_NUM_PORTS - 1 ) ; i >= 0 ; i-- ) - ibdev_put ( arbel->ibdev[i] ); - free ( arbel ); -} - -static struct pci_device_id arbel_nics[] = { - PCI_ROM ( 0x15b3, 0x6282, "mt25218", "MT25218 HCA driver", 0 ), - PCI_ROM ( 0x15b3, 0x6274, "mt25204", "MT25204 HCA driver", 0 ), -}; - -struct pci_driver arbel_driver __pci_driver = { - .ids = arbel_nics, - .id_count = ( sizeof ( arbel_nics ) / sizeof ( arbel_nics[0] ) ), - .probe = arbel_probe, - .remove = arbel_remove, -}; diff --git a/gpxe/src/drivers/infiniband/arbel.h b/gpxe/src/drivers/infiniband/arbel.h deleted file mode 100644 index 87f5933d..00000000 --- a/gpxe/src/drivers/infiniband/arbel.h +++ /dev/null @@ -1,544 +0,0 @@ -#ifndef _ARBEL_H -#define _ARBEL_H - -/** @file - * - * Mellanox Arbel Infiniband HCA driver - * - */ - -FILE_LICENCE ( GPL2_OR_LATER ); - -#include <stdint.h> -#include <gpxe/uaccess.h> -#include "mlx_bitops.h" -#include "MT25218_PRM.h" - -/* - * Hardware constants - * - */ - -/* Ports in existence */ -#define ARBEL_NUM_PORTS 2 -#define ARBEL_PORT_BASE 1 - -/* PCI BARs */ -#define ARBEL_PCI_CONFIG_BAR PCI_BASE_ADDRESS_0 -#define ARBEL_PCI_CONFIG_BAR_SIZE 0x100000 -#define ARBEL_PCI_UAR_BAR PCI_BASE_ADDRESS_2 -#define ARBEL_PCI_UAR_IDX 1 -#define ARBEL_PCI_UAR_SIZE 0x1000 - -/* UAR context table (UCE) resource types */ -#define ARBEL_UAR_RES_NONE 0x00 -#define ARBEL_UAR_RES_CQ_CI 0x01 -#define ARBEL_UAR_RES_CQ_ARM 0x02 -#define ARBEL_UAR_RES_SQ 0x03 -#define ARBEL_UAR_RES_RQ 0x04 -#define ARBEL_UAR_RES_GROUP_SEP 0x07 - -/* Work queue entry and completion queue entry opcodes */ -#define ARBEL_OPCODE_SEND 0x0a -#define ARBEL_OPCODE_RECV_ERROR 0xfe -#define ARBEL_OPCODE_SEND_ERROR 0xff - -/* HCA command register opcodes */ -#define ARBEL_HCR_QUERY_DEV_LIM 0x0003 -#define ARBEL_HCR_QUERY_FW 0x0004 -#define ARBEL_HCR_INIT_HCA 0x0007 -#define ARBEL_HCR_CLOSE_HCA 0x0008 -#define ARBEL_HCR_INIT_IB 0x0009 -#define ARBEL_HCR_CLOSE_IB 0x000a -#define ARBEL_HCR_SW2HW_MPT 0x000d -#define ARBEL_HCR_MAP_EQ 0x0012 -#define ARBEL_HCR_SW2HW_EQ 0x0013 -#define ARBEL_HCR_HW2SW_EQ 0x0014 -#define ARBEL_HCR_SW2HW_CQ 0x0016 -#define ARBEL_HCR_HW2SW_CQ 0x0017 -#define ARBEL_HCR_RST2INIT_QPEE 0x0019 -#define ARBEL_HCR_INIT2RTR_QPEE 0x001a -#define ARBEL_HCR_RTR2RTS_QPEE 0x001b -#define ARBEL_HCR_RTS2RTS_QPEE 0x001c -#define ARBEL_HCR_2RST_QPEE 0x0021 -#define ARBEL_HCR_MAD_IFC 0x0024 -#define ARBEL_HCR_READ_MGM 0x0025 -#define ARBEL_HCR_WRITE_MGM 0x0026 -#define ARBEL_HCR_MGID_HASH 0x0027 -#define ARBEL_HCR_RUN_FW 0x0ff6 -#define ARBEL_HCR_DISABLE_LAM 0x0ff7 -#define ARBEL_HCR_ENABLE_LAM 0x0ff8 -#define ARBEL_HCR_UNMAP_ICM 0x0ff9 -#define ARBEL_HCR_MAP_ICM 0x0ffa -#define ARBEL_HCR_UNMAP_ICM_AUX 0x0ffb -#define ARBEL_HCR_MAP_ICM_AUX 0x0ffc -#define ARBEL_HCR_SET_ICM_SIZE 0x0ffd -#define ARBEL_HCR_UNMAP_FA 0x0ffe -#define ARBEL_HCR_MAP_FA 0x0fff - -/* Service types */ -#define ARBEL_ST_UD 0x03 - -/* MTUs */ -#define ARBEL_MTU_2048 0x04 - -#define ARBEL_NO_EQ 64 - -#define ARBEL_INVALID_LKEY 0x00000100UL - -#define ARBEL_PAGE_SIZE 4096 - -#define ARBEL_DB_POST_SND_OFFSET 0x10 -#define ARBEL_DB_EQ_OFFSET(_eqn) ( 0x08 * (_eqn) ) - -#define ARBEL_QPEE_OPT_PARAM_QKEY 0x00000020UL - -#define ARBEL_MAP_EQ ( 0UL << 31 ) -#define ARBEL_UNMAP_EQ ( 1UL << 31 ) - -#define ARBEL_EV_PORT_STATE_CHANGE 0x09 - -/* - * Datatypes that seem to be missing from the autogenerated documentation - * - */ -struct arbelprm_mgm_hash_st { - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t hash[0x00010]; - pseudo_bit_t reserved1[0x00010]; -} __attribute__ (( packed )); - -struct arbelprm_scalar_parameter_st { - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t value[0x00020]; -} __attribute__ (( packed )); - -struct arbelprm_event_mask_st { - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t completion[0x00001]; - pseudo_bit_t reserved1[0x0008]; - pseudo_bit_t port_state_change[0x00001]; - pseudo_bit_t reserved2[0x00016]; -} __attribute__ (( packed )); - -struct arbelprm_eq_set_ci_st { - pseudo_bit_t ci[0x00020]; -} __attribute__ (( packed )); - -struct arbelprm_port_state_change_event_st { - pseudo_bit_t reserved[0x00020]; - struct arbelprm_port_state_change_st data; -} __attribute__ (( packed )); - -/* - * Wrapper structures for hardware datatypes - * - */ - -struct MLX_DECLARE_STRUCT ( arbelprm_access_lam ); -struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_context ); -struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_entry ); -struct MLX_DECLARE_STRUCT ( arbelprm_completion_with_error ); -struct MLX_DECLARE_STRUCT ( arbelprm_cq_arm_db_record ); -struct MLX_DECLARE_STRUCT ( arbelprm_cq_ci_db_record ); -struct MLX_DECLARE_STRUCT ( arbelprm_event_mask ); -struct MLX_DECLARE_STRUCT ( arbelprm_event_queue_entry ); -struct MLX_DECLARE_STRUCT ( arbelprm_eq_set_ci ); -struct MLX_DECLARE_STRUCT ( arbelprm_eqc ); -struct MLX_DECLARE_STRUCT ( arbelprm_hca_command_register ); -struct MLX_DECLARE_STRUCT ( arbelprm_init_hca ); -struct MLX_DECLARE_STRUCT ( arbelprm_init_ib ); -struct MLX_DECLARE_STRUCT ( arbelprm_mad_ifc ); -struct MLX_DECLARE_STRUCT ( arbelprm_mgm_entry ); -struct MLX_DECLARE_STRUCT ( arbelprm_mgm_hash ); -struct MLX_DECLARE_STRUCT ( arbelprm_mpt ); -struct MLX_DECLARE_STRUCT ( arbelprm_port_state_change_event ); -struct MLX_DECLARE_STRUCT ( arbelprm_qp_db_record ); -struct MLX_DECLARE_STRUCT ( arbelprm_qp_ee_state_transitions ); -struct MLX_DECLARE_STRUCT ( arbelprm_query_dev_lim ); -struct MLX_DECLARE_STRUCT ( arbelprm_query_fw ); -struct MLX_DECLARE_STRUCT ( arbelprm_queue_pair_ee_context_entry ); -struct MLX_DECLARE_STRUCT ( arbelprm_recv_wqe_segment_next ); -struct MLX_DECLARE_STRUCT ( arbelprm_scalar_parameter ); -struct MLX_DECLARE_STRUCT ( arbelprm_send_doorbell ); -struct MLX_DECLARE_STRUCT ( arbelprm_ud_address_vector ); -struct MLX_DECLARE_STRUCT ( arbelprm_virtual_physical_mapping ); -struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ctrl_send ); -struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_data_ptr ); -struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_next ); -struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ud ); - -/* - * Composite hardware datatypes - * - */ - -#define ARBEL_MAX_GATHER 1 - -struct arbelprm_ud_send_wqe { - struct arbelprm_wqe_segment_next next; - struct arbelprm_wqe_segment_ctrl_send ctrl; - struct arbelprm_wqe_segment_ud ud; - struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_GATHER]; -} __attribute__ (( packed )); - -#define ARBEL_MAX_SCATTER 1 - -struct arbelprm_recv_wqe { - /* The autogenerated header is inconsistent between send and - * receive WQEs. The "ctrl" structure for receive WQEs is - * defined to include the "next" structure. Since the "ctrl" - * part of the "ctrl" structure contains only "reserved, must - * be zero" bits, we ignore its definition and provide - * something more usable. - */ - struct arbelprm_recv_wqe_segment_next next; - uint32_t ctrl[2]; /* All "reserved, must be zero" */ - struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_SCATTER]; -} __attribute__ (( packed )); - -union arbelprm_completion_entry { - struct arbelprm_completion_queue_entry normal; - struct arbelprm_completion_with_error error; -} __attribute__ (( packed )); - -union arbelprm_event_entry { - struct arbelprm_event_queue_entry generic; - struct arbelprm_port_state_change_event port_state_change; -} __attribute__ (( packed )); - -union arbelprm_doorbell_record { - struct arbelprm_cq_arm_db_record cq_arm; - struct arbelprm_cq_ci_db_record cq_ci; - struct arbelprm_qp_db_record qp; -} __attribute__ (( packed )); - -union arbelprm_doorbell_register { - struct arbelprm_send_doorbell send; - uint32_t dword[2]; -} __attribute__ (( packed )); - -union arbelprm_eq_doorbell_register { - struct arbelprm_eq_set_ci ci; - uint32_t dword[1]; -} __attribute__ (( packed )); - -union arbelprm_mad { - struct arbelprm_mad_ifc ifc; - union ib_mad mad; -} __attribute__ (( packed )); - -/* - * gPXE-specific definitions - * - */ - -/** Arbel device limits */ -struct arbel_dev_limits { - /** Number of reserved QPs */ - unsigned int reserved_qps; - /** QP context entry size */ - size_t qpc_entry_size; - /** Extended QP context entry size */ - size_t eqpc_entry_size; - /** Number of reserved SRQs */ - unsigned int reserved_srqs; - /** SRQ context entry size */ - size_t srqc_entry_size; - /** Number of reserved EEs */ - unsigned int reserved_ees; - /** EE context entry size */ - size_t eec_entry_size; - /** Extended EE context entry size */ - size_t eeec_entry_size; - /** Number of reserved CQs */ - unsigned int reserved_cqs; - /** CQ context entry size */ - size_t cqc_entry_size; - /** Number of reserved EQs */ - unsigned int reserved_eqs; - /** Number of reserved MTTs */ - unsigned int reserved_mtts; - /** MTT entry size */ - size_t mtt_entry_size; - /** Number of reserved MRWs */ - unsigned int reserved_mrws; - /** MPT entry size */ - size_t mpt_entry_size; - /** Number of reserved RDBs */ - unsigned int reserved_rdbs; - /** EQ context entry size */ - size_t eqc_entry_size; - /** Number of reserved UARs */ - unsigned int reserved_uars; -}; - -/** Alignment of Arbel send work queue entries */ -#define ARBEL_SEND_WQE_ALIGN 128 - -/** An Arbel send work queue entry */ -union arbel_send_wqe { - struct arbelprm_ud_send_wqe ud; - uint8_t force_align[ARBEL_SEND_WQE_ALIGN]; -} __attribute__ (( packed )); - -/** An Arbel send work queue */ -struct arbel_send_work_queue { - /** Doorbell record number */ - unsigned int doorbell_idx; - /** Work queue entries */ - union arbel_send_wqe *wqe; - /** Size of work queue */ - size_t wqe_size; -}; - -/** Alignment of Arbel receive work queue entries */ -#define ARBEL_RECV_WQE_ALIGN 64 - -/** An Arbel receive work queue entry */ -union arbel_recv_wqe { - struct arbelprm_recv_wqe recv; - uint8_t force_align[ARBEL_RECV_WQE_ALIGN]; -} __attribute__ (( packed )); - -/** An Arbel receive work queue */ -struct arbel_recv_work_queue { - /** Doorbell record number */ - unsigned int doorbell_idx; - /** Work queue entries */ - union arbel_recv_wqe *wqe; - /** Size of work queue */ - size_t wqe_size; -}; - -/** Maximum number of allocatable queue pairs - * - * This is a policy decision, not a device limit. - */ -#define ARBEL_MAX_QPS 8 - -/** Base queue pair number */ -#define ARBEL_QPN_BASE 0x550000 - -/** An Arbel queue pair */ -struct arbel_queue_pair { - /** Send work queue */ - struct arbel_send_work_queue send; - /** Receive work queue */ - struct arbel_recv_work_queue recv; -}; - -/** Maximum number of allocatable completion queues - * - * This is a policy decision, not a device limit. - */ -#define ARBEL_MAX_CQS 8 - -/** An Arbel completion queue */ -struct arbel_completion_queue { - /** Consumer counter doorbell record number */ - unsigned int ci_doorbell_idx; - /** Arm queue doorbell record number */ - unsigned int arm_doorbell_idx; - /** Completion queue entries */ - union arbelprm_completion_entry *cqe; - /** Size of completion queue */ - size_t cqe_size; -}; - -/** Maximum number of allocatable event queues - * - * This is a policy decision, not a device limit. - */ -#define ARBEL_MAX_EQS 64 - -/** A Arbel event queue */ -struct arbel_event_queue { - /** Event queue entries */ - union arbelprm_event_entry *eqe; - /** Size of event queue */ - size_t eqe_size; - /** Event queue number */ - unsigned long eqn; - /** Next event queue entry index */ - unsigned long next_idx; - /** Doorbell register */ - void *doorbell; -}; - -/** Number of event queue entries - * - * This is a policy decision. - */ -#define ARBEL_NUM_EQES 4 - - -/** An Arbel resource bitmask */ -typedef uint32_t arbel_bitmask_t; - -/** Size of an Arbel resource bitmask */ -#define ARBEL_BITMASK_SIZE(max_entries) \ - ( ( (max_entries) + ( 8 * sizeof ( arbel_bitmask_t ) ) - 1 ) / \ - ( 8 * sizeof ( arbel_bitmask_t ) ) ) - -/** An Arbel device */ -struct arbel { - /** PCI configuration registers */ - void *config; - /** PCI user Access Region */ - void *uar; - /** Event queue consumer index doorbells */ - void *eq_ci_doorbells; - - /** Command input mailbox */ - void *mailbox_in; - /** Command output mailbox */ - void *mailbox_out; - - /** Firmware area in external memory */ - userptr_t firmware_area; - /** ICM size */ - size_t icm_len; - /** ICM AUX size */ - size_t icm_aux_len; - /** ICM area */ - userptr_t icm; - - /** Event queue */ - struct arbel_event_queue eq; - /** Doorbell records */ - union arbelprm_doorbell_record *db_rec; - /** Reserved LKey - * - * Used to get unrestricted memory access. - */ - unsigned long reserved_lkey; - - /** Completion queue in-use bitmask */ - arbel_bitmask_t cq_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_CQS ) ]; - /** Queue pair in-use bitmask */ - arbel_bitmask_t qp_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_QPS ) ]; - - /** Device limits */ - struct arbel_dev_limits limits; - - /** Infiniband devices */ - struct ib_device *ibdev[ARBEL_NUM_PORTS]; -}; - -/** Global protection domain */ -#define ARBEL_GLOBAL_PD 0x123456 - -/** Memory key prefix */ -#define ARBEL_MKEY_PREFIX 0x77000000UL - -/* - * HCA commands - * - */ - -#define ARBEL_HCR_BASE 0x80680 -#define ARBEL_HCR_REG(x) ( ARBEL_HCR_BASE + 4 * (x) ) -#define ARBEL_HCR_MAX_WAIT_MS 2000 -#define ARBEL_MBOX_ALIGN 4096 -#define ARBEL_MBOX_SIZE 512 - -/* HCA command is split into - * - * bits 11:0 Opcode - * bit 12 Input uses mailbox - * bit 13 Output uses mailbox - * bits 22:14 Input parameter length (in dwords) - * bits 31:23 Output parameter length (in dwords) - * - * Encoding the information in this way allows us to cut out several - * parameters to the arbel_command() call. - */ -#define ARBEL_HCR_IN_MBOX 0x00001000UL -#define ARBEL_HCR_OUT_MBOX 0x00002000UL -#define ARBEL_HCR_OPCODE( _command ) ( (_command) & 0xfff ) -#define ARBEL_HCR_IN_LEN( _command ) ( ( (_command) >> 12 ) & 0x7fc ) -#define ARBEL_HCR_OUT_LEN( _command ) ( ( (_command) >> 21 ) & 0x7fc ) - -/** Build HCR command from component parts */ -#define ARBEL_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len, \ - _out_mbox, _out_len ) \ - ( (_opcode) | \ - ( (_in_mbox) ? ARBEL_HCR_IN_MBOX : 0 ) | \ - ( ( (_in_len) / 4 ) << 14 ) | \ - ( (_out_mbox) ? ARBEL_HCR_OUT_MBOX : 0 ) | \ - ( ( (_out_len) / 4 ) << 23 ) ) - -#define ARBEL_HCR_IN_CMD( _opcode, _in_mbox, _in_len ) \ - ARBEL_HCR_INOUT_CMD ( _opcode, _in_mbox, _in_len, 0, 0 ) - -#define ARBEL_HCR_OUT_CMD( _opcode, _out_mbox, _out_len ) \ - ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, _out_mbox, _out_len ) - -#define ARBEL_HCR_VOID_CMD( _opcode ) \ - ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, 0, 0 ) - -/* - * Doorbell record allocation - * - * The doorbell record map looks like: - * - * ARBEL_MAX_CQS * Arm completion queue doorbell - * ARBEL_MAX_QPS * Send work request doorbell - * Group separator - * ...(empty space)... - * ARBEL_MAX_QPS * Receive work request doorbell - * ARBEL_MAX_CQS * Completion queue consumer counter update doorbell - */ - -#define ARBEL_MAX_DOORBELL_RECORDS 512 -#define ARBEL_GROUP_SEPARATOR_DOORBELL ( ARBEL_MAX_CQS + ARBEL_MAX_QPS ) - -/** - * Get arm completion queue doorbell index - * - * @v cqn_offset Completion queue number offset - * @ret doorbell_idx Doorbell index - */ -static inline unsigned int -arbel_cq_arm_doorbell_idx ( unsigned int cqn_offset ) { - return cqn_offset; -} - -/** - * Get send work request doorbell index - * - * @v qpn_offset Queue pair number offset - * @ret doorbell_idx Doorbell index - */ -static inline unsigned int -arbel_send_doorbell_idx ( unsigned int qpn_offset ) { - return ( ARBEL_MAX_CQS + qpn_offset ); -} - -/** - * Get receive work request doorbell index - * - * @v qpn_offset Queue pair number offset - * @ret doorbell_idx Doorbell index - */ -static inline unsigned int -arbel_recv_doorbell_idx ( unsigned int qpn_offset ) { - return ( ARBEL_MAX_DOORBELL_RECORDS - ARBEL_MAX_CQS - qpn_offset - 1 ); -} - -/** - * Get completion queue consumer counter doorbell index - * - * @v cqn_offset Completion queue number offset - * @ret doorbell_idx Doorbell index - */ -static inline unsigned int -arbel_cq_ci_doorbell_idx ( unsigned int cqn_offset ) { - return ( ARBEL_MAX_DOORBELL_RECORDS - cqn_offset - 1 ); -} - -#endif /* _ARBEL_H */ diff --git a/gpxe/src/drivers/infiniband/hermon.c b/gpxe/src/drivers/infiniband/hermon.c deleted file mode 100644 index b9c97f94..00000000 --- a/gpxe/src/drivers/infiniband/hermon.c +++ /dev/null @@ -1,2752 +0,0 @@ -/* - * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>. - * Copyright (C) 2008 Mellanox Technologies Ltd. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -FILE_LICENCE ( GPL2_OR_LATER ); - -#include <stdint.h> -#include <stdlib.h> -#include <stdio.h> -#include <string.h> -#include <strings.h> -#include <unistd.h> -#include <errno.h> -#include <byteswap.h> -#include <gpxe/io.h> -#include <gpxe/pci.h> -#include <gpxe/pcibackup.h> -#include <gpxe/malloc.h> -#include <gpxe/umalloc.h> -#include <gpxe/iobuf.h> -#include <gpxe/netdevice.h> -#include <gpxe/infiniband.h> -#include <gpxe/ib_smc.h> -#include "hermon.h" - -/** - * @file - * - * Mellanox Hermon Infiniband HCA - * - */ - -/*************************************************************************** - * - * Queue number allocation - * - *************************************************************************** - */ - -/** - * Allocate offsets within usage bitmask - * - * @v bits Usage bitmask - * @v bits_len Length of usage bitmask - * @v num_bits Number of contiguous bits to allocate within bitmask - * @ret bit First free bit within bitmask, or negative error - */ -static int hermon_bitmask_alloc ( hermon_bitmask_t *bits, - unsigned int bits_len, - unsigned int num_bits ) { - unsigned int bit = 0; - hermon_bitmask_t mask = 1; - unsigned int found = 0; - - /* Search bits for num_bits contiguous free bits */ - while ( bit < bits_len ) { - if ( ( mask & *bits ) == 0 ) { - if ( ++found == num_bits ) - goto found; - } else { - found = 0; - } - bit++; - mask = ( mask << 1 ) | ( mask >> ( 8 * sizeof ( mask ) - 1 ) ); - if ( mask == 1 ) - bits++; - } - return -ENFILE; - - found: - /* Mark bits as in-use */ - do { - *bits |= mask; - if ( mask == 1 ) - bits--; - mask = ( mask >> 1 ) | ( mask << ( 8 * sizeof ( mask ) - 1 ) ); - } while ( --found ); - - return ( bit - num_bits + 1 ); -} - -/** - * Free offsets within usage bitmask - * - * @v bits Usage bitmask - * @v bit Starting bit within bitmask - * @v num_bits Number of contiguous bits to free within bitmask - */ -static void hermon_bitmask_free ( hermon_bitmask_t *bits, - int bit, unsigned int num_bits ) { - hermon_bitmask_t mask; - - for ( ; num_bits ; bit++, num_bits-- ) { - mask = ( 1 << ( bit % ( 8 * sizeof ( mask ) ) ) ); - bits[ ( bit / ( 8 * sizeof ( mask ) ) ) ] &= ~mask; - } -} - -/*************************************************************************** - * - * HCA commands - * - *************************************************************************** - */ - -/** - * Wait for Hermon command completion - * - * @v hermon Hermon device - * @v hcr HCA command registers - * @ret rc Return status code - */ -static int hermon_cmd_wait ( struct hermon *hermon, - struct hermonprm_hca_command_register *hcr ) { - unsigned int wait; - - for ( wait = HERMON_HCR_MAX_WAIT_MS ; wait ; wait-- ) { - hcr->u.dwords[6] = - readl ( hermon->config + HERMON_HCR_REG ( 6 ) ); - if ( ( MLX_GET ( hcr, go ) == 0 ) && - ( MLX_GET ( hcr, t ) == hermon->toggle ) ) - return 0; - mdelay ( 1 ); - } - return -EBUSY; -} - -/** - * Issue HCA command - * - * @v hermon Hermon device - * @v command Command opcode, flags and input/output lengths - * @v op_mod Opcode modifier (0 if no modifier applicable) - * @v in Input parameters - * @v in_mod Input modifier (0 if no modifier applicable) - * @v out Output parameters - * @ret rc Return status code - */ -static int hermon_cmd ( struct hermon *hermon, unsigned long command, - unsigned int op_mod, const void *in, - unsigned int in_mod, void *out ) { - struct hermonprm_hca_command_register hcr; - unsigned int opcode = HERMON_HCR_OPCODE ( command ); - size_t in_len = HERMON_HCR_IN_LEN ( command ); - size_t out_len = HERMON_HCR_OUT_LEN ( command ); - void *in_buffer; - void *out_buffer; - unsigned int status; - unsigned int i; - int rc; - - assert ( in_len <= HERMON_MBOX_SIZE ); - assert ( out_len <= HERMON_MBOX_SIZE ); - - DBGC2 ( hermon, "Hermon %p command %02x in %zx%s out %zx%s\n", - hermon, opcode, in_len, - ( ( command & HERMON_HCR_IN_MBOX ) ? "(mbox)" : "" ), out_len, - ( ( command & HERMON_HCR_OUT_MBOX ) ? "(mbox)" : "" ) ); - - /* Check that HCR is free */ - if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) { - DBGC ( hermon, "Hermon %p command interface locked\n", - hermon ); - return rc; - } - - /* Flip HCR toggle */ - hermon->toggle = ( 1 - hermon->toggle ); - - /* Prepare HCR */ - memset ( &hcr, 0, sizeof ( hcr ) ); - in_buffer = &hcr.u.dwords[0]; - if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) { - in_buffer = hermon->mailbox_in; - MLX_FILL_1 ( &hcr, 1, in_param_l, virt_to_bus ( in_buffer ) ); - } - memcpy ( in_buffer, in, in_len ); - MLX_FILL_1 ( &hcr, 2, input_modifier, in_mod ); - out_buffer = &hcr.u.dwords[3]; - if ( out_len && ( command & HERMON_HCR_OUT_MBOX ) ) { - out_buffer = hermon->mailbox_out; - MLX_FILL_1 ( &hcr, 4, out_param_l, - virt_to_bus ( out_buffer ) ); - } - MLX_FILL_4 ( &hcr, 6, - opcode, opcode, - opcode_modifier, op_mod, - go, 1, - t, hermon->toggle ); - DBGC ( hermon, "Hermon %p issuing command %04x\n", - hermon, opcode ); - DBGC2_HDA ( hermon, virt_to_phys ( hermon->config + HERMON_HCR_BASE ), - &hcr, sizeof ( hcr ) ); - if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) { - DBGC2 ( hermon, "Input mailbox:\n" ); - DBGC2_HDA ( hermon, virt_to_phys ( in_buffer ), in_buffer, - ( ( in_len < 512 ) ? in_len : 512 ) ); - } - - /* Issue command */ - for ( i = 0 ; i < ( sizeof ( hcr ) / sizeof ( hcr.u.dwords[0] ) ) ; - i++ ) { - writel ( hcr.u.dwords[i], - hermon->config + HERMON_HCR_REG ( i ) ); - barrier(); - } - - /* Wait for command completion */ - if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) { - DBGC ( hermon, "Hermon %p timed out waiting for command:\n", - hermon ); - DBGC_HDA ( hermon, - virt_to_phys ( hermon->config + HERMON_HCR_BASE ), - &hcr, sizeof ( hcr ) ); - return rc; - } - - /* Check command status */ - status = MLX_GET ( &hcr, status ); - if ( status != 0 ) { - DBGC ( hermon, "Hermon %p command failed with status %02x:\n", - hermon, status ); - DBGC_HDA ( hermon, - virt_to_phys ( hermon->config + HERMON_HCR_BASE ), - &hcr, sizeof ( hcr ) ); - return -EIO; - } - - /* Read output parameters, if any */ - hcr.u.dwords[3] = readl ( hermon->config + HERMON_HCR_REG ( 3 ) ); - hcr.u.dwords[4] = readl ( hermon->config + HERMON_HCR_REG ( 4 ) ); - memcpy ( out, out_buffer, out_len ); - if ( out_len ) { - DBGC2 ( hermon, "Output%s:\n", - ( command & HERMON_HCR_OUT_MBOX ) ? " mailbox" : "" ); - DBGC2_HDA ( hermon, virt_to_phys ( out_buffer ), out_buffer, - ( ( out_len < 512 ) ? out_len : 512 ) ); - } - - return 0; -} - -static inline int -hermon_cmd_query_dev_cap ( struct hermon *hermon, - struct hermonprm_query_dev_cap *dev_cap ) { - return hermon_cmd ( hermon, - HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_DEV_CAP, - 1, sizeof ( *dev_cap ) ), - 0, NULL, 0, dev_cap ); -} - -static inline int -hermon_cmd_query_fw ( struct hermon *hermon, struct hermonprm_query_fw *fw ) { - return hermon_cmd ( hermon, - HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_FW, - 1, sizeof ( *fw ) ), - 0, NULL, 0, fw ); -} - -static inline int -hermon_cmd_init_hca ( struct hermon *hermon, - const struct hermonprm_init_hca *init_hca ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_HCA, - 1, sizeof ( *init_hca ) ), - 0, init_hca, 0, NULL ); -} - -static inline int -hermon_cmd_close_hca ( struct hermon *hermon ) { - return hermon_cmd ( hermon, - HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_HCA ), - 0, NULL, 0, NULL ); -} - -static inline int -hermon_cmd_init_port ( struct hermon *hermon, unsigned int port, - const struct hermonprm_init_port *init_port ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_PORT, - 1, sizeof ( *init_port ) ), - 0, init_port, port, NULL ); -} - -static inline int -hermon_cmd_close_port ( struct hermon *hermon, unsigned int port ) { - return hermon_cmd ( hermon, - HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_PORT ), - 0, NULL, port, NULL ); -} - -static inline int -hermon_cmd_sw2hw_mpt ( struct hermon *hermon, unsigned int index, - const struct hermonprm_mpt *mpt ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_MPT, - 1, sizeof ( *mpt ) ), - 0, mpt, index, NULL ); -} - -static inline int -hermon_cmd_write_mtt ( struct hermon *hermon, - const struct hermonprm_write_mtt *write_mtt ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MTT, - 1, sizeof ( *write_mtt ) ), - 0, write_mtt, 1, NULL ); -} - -static inline int -hermon_cmd_map_eq ( struct hermon *hermon, unsigned long index_map, - const struct hermonprm_event_mask *mask ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_EQ, - 0, sizeof ( *mask ) ), - 0, mask, index_map, NULL ); -} - -static inline int -hermon_cmd_sw2hw_eq ( struct hermon *hermon, unsigned int index, - const struct hermonprm_eqc *eqctx ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_EQ, - 1, sizeof ( *eqctx ) ), - 0, eqctx, index, NULL ); -} - -static inline int -hermon_cmd_hw2sw_eq ( struct hermon *hermon, unsigned int index, - struct hermonprm_eqc *eqctx ) { - return hermon_cmd ( hermon, - HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_EQ, - 1, sizeof ( *eqctx ) ), - 1, NULL, index, eqctx ); -} - -static inline int -hermon_cmd_query_eq ( struct hermon *hermon, unsigned int index, - struct hermonprm_eqc *eqctx ) { - return hermon_cmd ( hermon, - HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_EQ, - 1, sizeof ( *eqctx ) ), - 0, NULL, index, eqctx ); -} - -static inline int -hermon_cmd_sw2hw_cq ( struct hermon *hermon, unsigned long cqn, - const struct hermonprm_completion_queue_context *cqctx ){ - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_CQ, - 1, sizeof ( *cqctx ) ), - 0, cqctx, cqn, NULL ); -} - -static inline int -hermon_cmd_hw2sw_cq ( struct hermon *hermon, unsigned long cqn, - struct hermonprm_completion_queue_context *cqctx) { - return hermon_cmd ( hermon, - HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_CQ, - 1, sizeof ( *cqctx ) ), - 0, NULL, cqn, cqctx ); -} - -static inline int -hermon_cmd_rst2init_qp ( struct hermon *hermon, unsigned long qpn, - const struct hermonprm_qp_ee_state_transitions *ctx ){ - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_RST2INIT_QP, - 1, sizeof ( *ctx ) ), - 0, ctx, qpn, NULL ); -} - -static inline int -hermon_cmd_init2rtr_qp ( struct hermon *hermon, unsigned long qpn, - const struct hermonprm_qp_ee_state_transitions *ctx ){ - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_INIT2RTR_QP, - 1, sizeof ( *ctx ) ), - 0, ctx, qpn, NULL ); -} - -static inline int -hermon_cmd_rtr2rts_qp ( struct hermon *hermon, unsigned long qpn, - const struct hermonprm_qp_ee_state_transitions *ctx ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_RTR2RTS_QP, - 1, sizeof ( *ctx ) ), - 0, ctx, qpn, NULL ); -} - -static inline int -hermon_cmd_rts2rts_qp ( struct hermon *hermon, unsigned long qpn, - const struct hermonprm_qp_ee_state_transitions *ctx ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_RTS2RTS_QP, - 1, sizeof ( *ctx ) ), - 0, ctx, qpn, NULL ); -} - -static inline int -hermon_cmd_2rst_qp ( struct hermon *hermon, unsigned long qpn ) { - return hermon_cmd ( hermon, - HERMON_HCR_VOID_CMD ( HERMON_HCR_2RST_QP ), - 0x03, NULL, qpn, NULL ); -} - -static inline int -hermon_cmd_query_qp ( struct hermon *hermon, unsigned long qpn, - struct hermonprm_qp_ee_state_transitions *ctx ) { - return hermon_cmd ( hermon, - HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_QP, - 1, sizeof ( *ctx ) ), - 0, NULL, qpn, ctx ); -} - -static inline int -hermon_cmd_conf_special_qp ( struct hermon *hermon, unsigned int internal_qps, - unsigned long base_qpn ) { - return hermon_cmd ( hermon, - HERMON_HCR_VOID_CMD ( HERMON_HCR_CONF_SPECIAL_QP ), - internal_qps, NULL, base_qpn, NULL ); -} - -static inline int -hermon_cmd_mad_ifc ( struct hermon *hermon, unsigned int port, - union hermonprm_mad *mad ) { - return hermon_cmd ( hermon, - HERMON_HCR_INOUT_CMD ( HERMON_HCR_MAD_IFC, - 1, sizeof ( *mad ), - 1, sizeof ( *mad ) ), - 0x03, mad, port, mad ); -} - -static inline int -hermon_cmd_read_mcg ( struct hermon *hermon, unsigned int index, - struct hermonprm_mcg_entry *mcg ) { - return hermon_cmd ( hermon, - HERMON_HCR_OUT_CMD ( HERMON_HCR_READ_MCG, - 1, sizeof ( *mcg ) ), - 0, NULL, index, mcg ); -} - -static inline int -hermon_cmd_write_mcg ( struct hermon *hermon, unsigned int index, - const struct hermonprm_mcg_entry *mcg ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MCG, - 1, sizeof ( *mcg ) ), - 0, mcg, index, NULL ); -} - -static inline int -hermon_cmd_mgid_hash ( struct hermon *hermon, const struct ib_gid *gid, - struct hermonprm_mgm_hash *hash ) { - return hermon_cmd ( hermon, - HERMON_HCR_INOUT_CMD ( HERMON_HCR_MGID_HASH, - 1, sizeof ( *gid ), - 0, sizeof ( *hash ) ), - 0, gid, 0, hash ); -} - -static inline int -hermon_cmd_run_fw ( struct hermon *hermon ) { - return hermon_cmd ( hermon, - HERMON_HCR_VOID_CMD ( HERMON_HCR_RUN_FW ), - 0, NULL, 0, NULL ); -} - -static inline int -hermon_cmd_unmap_icm ( struct hermon *hermon, unsigned int page_count, - const struct hermonprm_scalar_parameter *offset ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_UNMAP_ICM, - 0, sizeof ( *offset ) ), - 0, offset, page_count, NULL ); -} - -static inline int -hermon_cmd_map_icm ( struct hermon *hermon, - const struct hermonprm_virtual_physical_mapping *map ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM, - 1, sizeof ( *map ) ), - 0, map, 1, NULL ); -} - -static inline int -hermon_cmd_unmap_icm_aux ( struct hermon *hermon ) { - return hermon_cmd ( hermon, - HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_ICM_AUX ), - 0, NULL, 0, NULL ); -} - -static inline int -hermon_cmd_map_icm_aux ( struct hermon *hermon, - const struct hermonprm_virtual_physical_mapping *map ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM_AUX, - 1, sizeof ( *map ) ), - 0, map, 1, NULL ); -} - -static inline int -hermon_cmd_set_icm_size ( struct hermon *hermon, - const struct hermonprm_scalar_parameter *icm_size, - struct hermonprm_scalar_parameter *icm_aux_size ) { - return hermon_cmd ( hermon, - HERMON_HCR_INOUT_CMD ( HERMON_HCR_SET_ICM_SIZE, - 0, sizeof ( *icm_size ), - 0, sizeof (*icm_aux_size) ), - 0, icm_size, 0, icm_aux_size ); -} - -static inline int -hermon_cmd_unmap_fa ( struct hermon *hermon ) { - return hermon_cmd ( hermon, - HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_FA ), - 0, NULL, 0, NULL ); -} - -static inline int -hermon_cmd_map_fa ( struct hermon *hermon, - const struct hermonprm_virtual_physical_mapping *map ) { - return hermon_cmd ( hermon, - HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_FA, - 1, sizeof ( *map ) ), - 0, map, 1, NULL ); -} - -static inline int -hermon_cmd_sense_port ( struct hermon *hermon, unsigned int port, - struct hermonprm_sense_port *port_type ) { - return hermon_cmd ( hermon, - HERMON_HCR_OUT_CMD ( HERMON_HCR_SENSE_PORT, - 1, sizeof ( *port_type ) ), - 0, NULL, port, port_type ); -} - - -/*************************************************************************** - * - * Memory translation table operations - * - *************************************************************************** - */ - -/** - * Allocate MTT entries - * - * @v hermon Hermon device - * @v memory Memory to map into MTT - * @v len Length of memory to map - * @v mtt MTT descriptor to fill in - * @ret rc Return status code - */ -static int hermon_alloc_mtt ( struct hermon *hermon, - const void *memory, size_t len, - struct hermon_mtt *mtt ) { - struct hermonprm_write_mtt write_mtt; - physaddr_t start; - unsigned int page_offset; - unsigned int num_pages; - int mtt_offset; - unsigned int mtt_base_addr; - unsigned int i; - int rc; - - /* Find available MTT entries */ - start = virt_to_phys ( memory ); - page_offset = ( start & ( HERMON_PAGE_SIZE - 1 ) ); - start -= page_offset; - len += page_offset; - num_pages = ( ( len + HERMON_PAGE_SIZE - 1 ) / HERMON_PAGE_SIZE ); - mtt_offset = hermon_bitmask_alloc ( hermon->mtt_inuse, HERMON_MAX_MTTS, - num_pages ); - if ( mtt_offset < 0 ) { - DBGC ( hermon, "Hermon %p could not allocate %d MTT entries\n", - hermon, num_pages ); - rc = mtt_offset; - goto err_mtt_offset; - } - mtt_base_addr = ( ( hermon->cap.reserved_mtts + mtt_offset ) * - hermon->cap.mtt_entry_size ); - - /* Fill in MTT structure */ - mtt->mtt_offset = mtt_offset; - mtt->num_pages = num_pages; - mtt->mtt_base_addr = mtt_base_addr; - mtt->page_offset = page_offset; - - /* Construct and issue WRITE_MTT commands */ - for ( i = 0 ; i < num_pages ; i++ ) { - memset ( &write_mtt, 0, sizeof ( write_mtt ) ); - MLX_FILL_1 ( &write_mtt.mtt_base_addr, 1, - value, mtt_base_addr ); - MLX_FILL_2 ( &write_mtt.mtt, 1, - p, 1, - ptag_l, ( start >> 3 ) ); - if ( ( rc = hermon_cmd_write_mtt ( hermon, - &write_mtt ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not write MTT at %x\n", - hermon, mtt_base_addr ); - goto err_write_mtt; - } - start += HERMON_PAGE_SIZE; - mtt_base_addr += hermon->cap.mtt_entry_size; - } - - return 0; - - err_write_mtt: - hermon_bitmask_free ( hermon->mtt_inuse, mtt_offset, num_pages ); - err_mtt_offset: - return rc; -} - -/** - * Free MTT entries - * - * @v hermon Hermon device - * @v mtt MTT descriptor - */ -static void hermon_free_mtt ( struct hermon *hermon, - struct hermon_mtt *mtt ) { - hermon_bitmask_free ( hermon->mtt_inuse, mtt->mtt_offset, - mtt->num_pages ); -} - -/*************************************************************************** - * - * MAD operations - * - *************************************************************************** - */ - -/** - * Issue management datagram - * - * @v ibdev Infiniband device - * @v mad Management datagram - * @ret rc Return status code - */ -static int hermon_mad ( struct ib_device *ibdev, union ib_mad *mad ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - union hermonprm_mad mad_ifc; - int rc; - - linker_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ), - mad_size_mismatch ); - - /* Copy in request packet */ - memcpy ( &mad_ifc.mad, mad, sizeof ( mad_ifc.mad ) ); - - /* Issue MAD */ - if ( ( rc = hermon_cmd_mad_ifc ( hermon, ibdev->port, - &mad_ifc ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not issue MAD IFC: %s\n", - hermon, strerror ( rc ) ); - return rc; - } - - /* Copy out reply packet */ - memcpy ( mad, &mad_ifc.mad, sizeof ( *mad ) ); - - if ( mad->hdr.status != 0 ) { - DBGC ( hermon, "Hermon %p MAD IFC status %04x\n", - hermon, ntohs ( mad->hdr.status ) ); - return -EIO; - } - return 0; -} - -/*************************************************************************** - * - * Completion queue operations - * - *************************************************************************** - */ - -/** - * Create completion queue - * - * @v ibdev Infiniband device - * @v cq Completion queue - * @ret rc Return status code - */ -static int hermon_create_cq ( struct ib_device *ibdev, - struct ib_completion_queue *cq ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermon_completion_queue *hermon_cq; - struct hermonprm_completion_queue_context cqctx; - int cqn_offset; - unsigned int i; - int rc; - - /* Find a free completion queue number */ - cqn_offset = hermon_bitmask_alloc ( hermon->cq_inuse, - HERMON_MAX_CQS, 1 ); - if ( cqn_offset < 0 ) { - DBGC ( hermon, "Hermon %p out of completion queues\n", - hermon ); - rc = cqn_offset; - goto err_cqn_offset; - } - cq->cqn = ( hermon->cap.reserved_cqs + cqn_offset ); - - /* Allocate control structures */ - hermon_cq = zalloc ( sizeof ( *hermon_cq ) ); - if ( ! hermon_cq ) { - rc = -ENOMEM; - goto err_hermon_cq; - } - - /* Allocate completion queue itself */ - hermon_cq->cqe_size = ( cq->num_cqes * sizeof ( hermon_cq->cqe[0] ) ); - hermon_cq->cqe = malloc_dma ( hermon_cq->cqe_size, - sizeof ( hermon_cq->cqe[0] ) ); - if ( ! hermon_cq->cqe ) { - rc = -ENOMEM; - goto err_cqe; - } - memset ( hermon_cq->cqe, 0, hermon_cq->cqe_size ); - for ( i = 0 ; i < cq->num_cqes ; i++ ) { - MLX_FILL_1 ( &hermon_cq->cqe[i].normal, 7, owner, 1 ); - } - barrier(); - - /* Allocate MTT entries */ - if ( ( rc = hermon_alloc_mtt ( hermon, hermon_cq->cqe, - hermon_cq->cqe_size, - &hermon_cq->mtt ) ) != 0 ) - goto err_alloc_mtt; - - /* Hand queue over to hardware */ - memset ( &cqctx, 0, sizeof ( cqctx ) ); - MLX_FILL_1 ( &cqctx, 0, st, 0xa /* "Event fired" */ ); - MLX_FILL_1 ( &cqctx, 2, - page_offset, ( hermon_cq->mtt.page_offset >> 5 ) ); - MLX_FILL_2 ( &cqctx, 3, - usr_page, HERMON_UAR_NON_EQ_PAGE, - log_cq_size, fls ( cq->num_cqes - 1 ) ); - MLX_FILL_1 ( &cqctx, 7, mtt_base_addr_l, - ( hermon_cq->mtt.mtt_base_addr >> 3 ) ); - MLX_FILL_1 ( &cqctx, 15, db_record_addr_l, - ( virt_to_phys ( &hermon_cq->doorbell ) >> 3 ) ); - if ( ( rc = hermon_cmd_sw2hw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) { - DBGC ( hermon, "Hermon %p SW2HW_CQ failed: %s\n", - hermon, strerror ( rc ) ); - goto err_sw2hw_cq; - } - - DBGC ( hermon, "Hermon %p CQN %#lx ring at [%p,%p)\n", - hermon, cq->cqn, hermon_cq->cqe, - ( ( ( void * ) hermon_cq->cqe ) + hermon_cq->cqe_size ) ); - ib_cq_set_drvdata ( cq, hermon_cq ); - return 0; - - err_sw2hw_cq: - hermon_free_mtt ( hermon, &hermon_cq->mtt ); - err_alloc_mtt: - free_dma ( hermon_cq->cqe, hermon_cq->cqe_size ); - err_cqe: - free ( hermon_cq ); - err_hermon_cq: - hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 ); - err_cqn_offset: - return rc; -} - -/** - * Destroy completion queue - * - * @v ibdev Infiniband device - * @v cq Completion queue - */ -static void hermon_destroy_cq ( struct ib_device *ibdev, - struct ib_completion_queue *cq ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq ); - struct hermonprm_completion_queue_context cqctx; - int cqn_offset; - int rc; - - /* Take ownership back from hardware */ - if ( ( rc = hermon_cmd_hw2sw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) { - DBGC ( hermon, "Hermon %p FATAL HW2SW_CQ failed on CQN %#lx: " - "%s\n", hermon, cq->cqn, strerror ( rc ) ); - /* Leak memory and return; at least we avoid corruption */ - return; - } - - /* Free MTT entries */ - hermon_free_mtt ( hermon, &hermon_cq->mtt ); - - /* Free memory */ - free_dma ( hermon_cq->cqe, hermon_cq->cqe_size ); - free ( hermon_cq ); - - /* Mark queue number as free */ - cqn_offset = ( cq->cqn - hermon->cap.reserved_cqs ); - hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 ); - - ib_cq_set_drvdata ( cq, NULL ); -} - -/*************************************************************************** - * - * Queue pair operations - * - *************************************************************************** - */ - -/** - * Assign queue pair number - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @ret rc Return status code - */ -static int hermon_alloc_qpn ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - unsigned int port_offset; - int qpn_offset; - - /* Calculate queue pair number */ - port_offset = ( ibdev->port - HERMON_PORT_BASE ); - - switch ( qp->type ) { - case IB_QPT_SMI: - qp->qpn = ( hermon->special_qpn_base + port_offset ); - return 0; - case IB_QPT_GSI: - qp->qpn = ( hermon->special_qpn_base + 2 + port_offset ); - return 0; - case IB_QPT_UD: - case IB_QPT_RC: - /* Find a free queue pair number */ - qpn_offset = hermon_bitmask_alloc ( hermon->qp_inuse, - HERMON_MAX_QPS, 1 ); - if ( qpn_offset < 0 ) { - DBGC ( hermon, "Hermon %p out of queue pairs\n", - hermon ); - return qpn_offset; - } - qp->qpn = ( ( random() & HERMON_QPN_RANDOM_MASK ) | - ( hermon->qpn_base + qpn_offset ) ); - return 0; - default: - DBGC ( hermon, "Hermon %p unsupported QP type %d\n", - hermon, qp->type ); - return -ENOTSUP; - } -} - -/** - * Free queue pair number - * - * @v ibdev Infiniband device - * @v qp Queue pair - */ -static void hermon_free_qpn ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - int qpn_offset; - - qpn_offset = ( ( qp->qpn & ~HERMON_QPN_RANDOM_MASK ) - - hermon->qpn_base ); - if ( qpn_offset >= 0 ) - hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 ); -} - -/** - * Calculate transmission rate - * - * @v av Address vector - * @ret hermon_rate Hermon rate - */ -static unsigned int hermon_rate ( struct ib_address_vector *av ) { - return ( ( ( av->rate >= IB_RATE_2_5 ) && ( av->rate <= IB_RATE_120 ) ) - ? ( av->rate + 5 ) : 0 ); -} - -/** - * Calculate schedule queue - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @ret sched_queue Schedule queue - */ -static unsigned int hermon_sched_queue ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - return ( ( ( qp->type == IB_QPT_SMI ) ? - HERMON_SCHED_QP0 : HERMON_SCHED_DEFAULT ) | - ( ( ibdev->port - 1 ) << 6 ) ); -} - -/** Queue pair transport service type map */ -static uint8_t hermon_qp_st[] = { - [IB_QPT_SMI] = HERMON_ST_MLX, - [IB_QPT_GSI] = HERMON_ST_MLX, - [IB_QPT_UD] = HERMON_ST_UD, - [IB_QPT_RC] = HERMON_ST_RC, -}; - -/** - * Dump queue pair context (for debugging only) - * - * @v hermon Hermon device - * @v qp Queue pair - * @ret rc Return status code - */ -static inline int hermon_dump_qpctx ( struct hermon *hermon, - struct ib_queue_pair *qp ) { - struct hermonprm_qp_ee_state_transitions qpctx; - int rc; - - memset ( &qpctx, 0, sizeof ( qpctx ) ); - if ( ( rc = hermon_cmd_query_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ) { - DBGC ( hermon, "Hermon %p QUERY_QP failed: %s\n", - hermon, strerror ( rc ) ); - return rc; - } - DBGC ( hermon, "Hermon %p QPN %lx context:\n", hermon, qp->qpn ); - DBGC_HDA ( hermon, 0, &qpctx.u.dwords[2], - ( sizeof ( qpctx ) - 8 ) ); - - return 0; -} - -/** - * Create queue pair - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @ret rc Return status code - */ -static int hermon_create_qp ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermon_queue_pair *hermon_qp; - struct hermonprm_qp_ee_state_transitions qpctx; - int rc; - - /* Calculate queue pair number */ - if ( ( rc = hermon_alloc_qpn ( ibdev, qp ) ) != 0 ) - goto err_alloc_qpn; - - /* Allocate control structures */ - hermon_qp = zalloc ( sizeof ( *hermon_qp ) ); - if ( ! hermon_qp ) { - rc = -ENOMEM; - goto err_hermon_qp; - } - - /* Calculate doorbell address */ - hermon_qp->send.doorbell = - ( hermon->uar + HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE + - HERMON_DB_POST_SND_OFFSET ); - - /* Allocate work queue buffer */ - hermon_qp->send.num_wqes = ( qp->send.num_wqes /* headroom */ + 1 + - ( 2048 / sizeof ( hermon_qp->send.wqe[0] ) ) ); - hermon_qp->send.num_wqes = - ( 1 << fls ( hermon_qp->send.num_wqes - 1 ) ); /* round up */ - hermon_qp->send.wqe_size = ( hermon_qp->send.num_wqes * - sizeof ( hermon_qp->send.wqe[0] ) ); - hermon_qp->recv.wqe_size = ( qp->recv.num_wqes * - sizeof ( hermon_qp->recv.wqe[0] ) ); - hermon_qp->wqe_size = ( hermon_qp->send.wqe_size + - hermon_qp->recv.wqe_size ); - hermon_qp->wqe = malloc_dma ( hermon_qp->wqe_size, - sizeof ( hermon_qp->send.wqe[0] ) ); - if ( ! hermon_qp->wqe ) { - rc = -ENOMEM; - goto err_alloc_wqe; - } - hermon_qp->send.wqe = hermon_qp->wqe; - memset ( hermon_qp->send.wqe, 0xff, hermon_qp->send.wqe_size ); - hermon_qp->recv.wqe = ( hermon_qp->wqe + hermon_qp->send.wqe_size ); - memset ( hermon_qp->recv.wqe, 0, hermon_qp->recv.wqe_size ); - - /* Allocate MTT entries */ - if ( ( rc = hermon_alloc_mtt ( hermon, hermon_qp->wqe, - hermon_qp->wqe_size, - &hermon_qp->mtt ) ) != 0 ) { - goto err_alloc_mtt; - } - - /* Transition queue to INIT state */ - memset ( &qpctx, 0, sizeof ( qpctx ) ); - MLX_FILL_2 ( &qpctx, 2, - qpc_eec_data.pm_state, HERMON_PM_STATE_MIGRATED, - qpc_eec_data.st, hermon_qp_st[qp->type] ); - MLX_FILL_1 ( &qpctx, 3, qpc_eec_data.pd, HERMON_GLOBAL_PD ); - MLX_FILL_4 ( &qpctx, 4, - qpc_eec_data.log_rq_size, fls ( qp->recv.num_wqes - 1 ), - qpc_eec_data.log_rq_stride, - ( fls ( sizeof ( hermon_qp->recv.wqe[0] ) - 1 ) - 4 ), - qpc_eec_data.log_sq_size, - fls ( hermon_qp->send.num_wqes - 1 ), - qpc_eec_data.log_sq_stride, - ( fls ( sizeof ( hermon_qp->send.wqe[0] ) - 1 ) - 4 ) ); - MLX_FILL_1 ( &qpctx, 5, - qpc_eec_data.usr_page, HERMON_UAR_NON_EQ_PAGE ); - MLX_FILL_1 ( &qpctx, 33, qpc_eec_data.cqn_snd, qp->send.cq->cqn ); - MLX_FILL_4 ( &qpctx, 38, - qpc_eec_data.rre, 1, - qpc_eec_data.rwe, 1, - qpc_eec_data.rae, 1, - qpc_eec_data.page_offset, - ( hermon_qp->mtt.page_offset >> 6 ) ); - MLX_FILL_1 ( &qpctx, 41, qpc_eec_data.cqn_rcv, qp->recv.cq->cqn ); - MLX_FILL_1 ( &qpctx, 43, qpc_eec_data.db_record_addr_l, - ( virt_to_phys ( &hermon_qp->recv.doorbell ) >> 2 ) ); - MLX_FILL_1 ( &qpctx, 53, qpc_eec_data.mtt_base_addr_l, - ( hermon_qp->mtt.mtt_base_addr >> 3 ) ); - if ( ( rc = hermon_cmd_rst2init_qp ( hermon, qp->qpn, - &qpctx ) ) != 0 ) { - DBGC ( hermon, "Hermon %p RST2INIT_QP failed: %s\n", - hermon, strerror ( rc ) ); - goto err_rst2init_qp; - } - hermon_qp->state = HERMON_QP_ST_INIT; - - DBGC ( hermon, "Hermon %p QPN %#lx send ring at [%p,%p)\n", - hermon, qp->qpn, hermon_qp->send.wqe, - ( ((void *)hermon_qp->send.wqe ) + hermon_qp->send.wqe_size ) ); - DBGC ( hermon, "Hermon %p QPN %#lx receive ring at [%p,%p)\n", - hermon, qp->qpn, hermon_qp->recv.wqe, - ( ((void *)hermon_qp->recv.wqe ) + hermon_qp->recv.wqe_size ) ); - ib_qp_set_drvdata ( qp, hermon_qp ); - return 0; - - hermon_cmd_2rst_qp ( hermon, qp->qpn ); - err_rst2init_qp: - hermon_free_mtt ( hermon, &hermon_qp->mtt ); - err_alloc_mtt: - free_dma ( hermon_qp->wqe, hermon_qp->wqe_size ); - err_alloc_wqe: - free ( hermon_qp ); - err_hermon_qp: - hermon_free_qpn ( ibdev, qp ); - err_alloc_qpn: - return rc; -} - -/** - * Modify queue pair - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @ret rc Return status code - */ -static int hermon_modify_qp ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp ); - struct hermonprm_qp_ee_state_transitions qpctx; - int rc; - - /* Transition queue to RTR state, if applicable */ - if ( hermon_qp->state < HERMON_QP_ST_RTR ) { - memset ( &qpctx, 0, sizeof ( qpctx ) ); - MLX_FILL_2 ( &qpctx, 4, - qpc_eec_data.mtu, HERMON_MTU_2048, - qpc_eec_data.msg_max, 31 ); - MLX_FILL_1 ( &qpctx, 7, - qpc_eec_data.remote_qpn_een, qp->av.qpn ); - MLX_FILL_1 ( &qpctx, 9, - qpc_eec_data.primary_address_path.rlid, - qp->av.lid ); - MLX_FILL_1 ( &qpctx, 10, - qpc_eec_data.primary_address_path.max_stat_rate, - hermon_rate ( &qp->av ) ); - memcpy ( &qpctx.u.dwords[12], &qp->av.gid, - sizeof ( qp->av.gid ) ); - MLX_FILL_1 ( &qpctx, 16, - qpc_eec_data.primary_address_path.sched_queue, - hermon_sched_queue ( ibdev, qp ) ); - MLX_FILL_1 ( &qpctx, 39, - qpc_eec_data.next_rcv_psn, qp->recv.psn ); - if ( ( rc = hermon_cmd_init2rtr_qp ( hermon, qp->qpn, - &qpctx ) ) != 0 ) { - DBGC ( hermon, "Hermon %p INIT2RTR_QP failed: %s\n", - hermon, strerror ( rc ) ); - return rc; - } - hermon_qp->state = HERMON_QP_ST_RTR; - } - - /* Transition queue to RTS state */ - if ( hermon_qp->state < HERMON_QP_ST_RTS ) { - memset ( &qpctx, 0, sizeof ( qpctx ) ); - MLX_FILL_1 ( &qpctx, 10, - qpc_eec_data.primary_address_path.ack_timeout, - 14 /* 4.096us * 2^(14) = 67ms */ ); - MLX_FILL_2 ( &qpctx, 30, - qpc_eec_data.retry_count, HERMON_RETRY_MAX, - qpc_eec_data.rnr_retry, HERMON_RETRY_MAX ); - MLX_FILL_1 ( &qpctx, 32, - qpc_eec_data.next_send_psn, qp->send.psn ); - if ( ( rc = hermon_cmd_rtr2rts_qp ( hermon, qp->qpn, - &qpctx ) ) != 0 ) { - DBGC ( hermon, "Hermon %p RTR2RTS_QP failed: %s\n", - hermon, strerror ( rc ) ); - return rc; - } - hermon_qp->state = HERMON_QP_ST_RTS; - } - - /* Update parameters in RTS state */ - memset ( &qpctx, 0, sizeof ( qpctx ) ); - MLX_FILL_1 ( &qpctx, 0, opt_param_mask, HERMON_QP_OPT_PARAM_QKEY ); - MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey ); - if ( ( rc = hermon_cmd_rts2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){ - DBGC ( hermon, "Hermon %p RTS2RTS_QP failed: %s\n", - hermon, strerror ( rc ) ); - return rc; - } - - return 0; -} - -/** - * Destroy queue pair - * - * @v ibdev Infiniband device - * @v qp Queue pair - */ -static void hermon_destroy_qp ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp ); - int rc; - - /* Take ownership back from hardware */ - if ( ( rc = hermon_cmd_2rst_qp ( hermon, qp->qpn ) ) != 0 ) { - DBGC ( hermon, "Hermon %p FATAL 2RST_QP failed on QPN %#lx: " - "%s\n", hermon, qp->qpn, strerror ( rc ) ); - /* Leak memory and return; at least we avoid corruption */ - return; - } - - /* Free MTT entries */ - hermon_free_mtt ( hermon, &hermon_qp->mtt ); - - /* Free memory */ - free_dma ( hermon_qp->wqe, hermon_qp->wqe_size ); - free ( hermon_qp ); - - /* Mark queue number as free */ - hermon_free_qpn ( ibdev, qp ); - - ib_qp_set_drvdata ( qp, NULL ); -} - -/*************************************************************************** - * - * Work request operations - * - *************************************************************************** - */ - -/** - * Construct UD send work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v av Address vector - * @v iobuf I/O buffer - * @v wqe Send work queue entry - * @ret opcode Control opcode - */ -static unsigned int -hermon_fill_ud_send_wqe ( struct ib_device *ibdev, - struct ib_queue_pair *qp __unused, - struct ib_address_vector *av, - struct io_buffer *iobuf, - union hermon_send_wqe *wqe ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - - MLX_FILL_1 ( &wqe->ud.ctrl, 1, ds, - ( ( offsetof ( typeof ( wqe->ud ), data[1] ) / 16 ) ) ); - MLX_FILL_1 ( &wqe->ud.ctrl, 2, c, 0x03 /* generate completion */ ); - MLX_FILL_2 ( &wqe->ud.ud, 0, - ud_address_vector.pd, HERMON_GLOBAL_PD, - ud_address_vector.port_number, ibdev->port ); - MLX_FILL_2 ( &wqe->ud.ud, 1, - ud_address_vector.rlid, av->lid, - ud_address_vector.g, av->gid_present ); - MLX_FILL_1 ( &wqe->ud.ud, 2, - ud_address_vector.max_stat_rate, hermon_rate ( av ) ); - MLX_FILL_1 ( &wqe->ud.ud, 3, ud_address_vector.sl, av->sl ); - memcpy ( &wqe->ud.ud.u.dwords[4], &av->gid, sizeof ( av->gid ) ); - MLX_FILL_1 ( &wqe->ud.ud, 8, destination_qp, av->qpn ); - MLX_FILL_1 ( &wqe->ud.ud, 9, q_key, av->qkey ); - MLX_FILL_1 ( &wqe->ud.data[0], 0, byte_count, iob_len ( iobuf ) ); - MLX_FILL_1 ( &wqe->ud.data[0], 1, l_key, hermon->lkey ); - MLX_FILL_1 ( &wqe->ud.data[0], 3, - local_address_l, virt_to_bus ( iobuf->data ) ); - return HERMON_OPCODE_SEND; -} - -/** - * Construct MLX send work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v av Address vector - * @v iobuf I/O buffer - * @v wqe Send work queue entry - * @ret opcode Control opcode - */ -static unsigned int -hermon_fill_mlx_send_wqe ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct ib_address_vector *av, - struct io_buffer *iobuf, - union hermon_send_wqe *wqe ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct io_buffer headers; - - /* Construct IB headers */ - iob_populate ( &headers, &wqe->mlx.headers, 0, - sizeof ( wqe->mlx.headers ) ); - iob_reserve ( &headers, sizeof ( wqe->mlx.headers ) ); - ib_push ( ibdev, &headers, qp, iob_len ( iobuf ), av ); - - /* Fill work queue entry */ - MLX_FILL_1 ( &wqe->mlx.ctrl, 1, ds, - ( ( offsetof ( typeof ( wqe->mlx ), data[2] ) / 16 ) ) ); - MLX_FILL_5 ( &wqe->mlx.ctrl, 2, - c, 0x03 /* generate completion */, - icrc, 0 /* generate ICRC */, - max_statrate, hermon_rate ( av ), - slr, 0, - v15, ( ( qp->ext_qpn == IB_QPN_SMI ) ? 1 : 0 ) ); - MLX_FILL_1 ( &wqe->mlx.ctrl, 3, rlid, av->lid ); - MLX_FILL_1 ( &wqe->mlx.data[0], 0, - byte_count, iob_len ( &headers ) ); - MLX_FILL_1 ( &wqe->mlx.data[0], 1, l_key, hermon->lkey ); - MLX_FILL_1 ( &wqe->mlx.data[0], 3, - local_address_l, virt_to_bus ( headers.data ) ); - MLX_FILL_1 ( &wqe->mlx.data[1], 0, - byte_count, ( iob_len ( iobuf ) + 4 /* ICRC */ ) ); - MLX_FILL_1 ( &wqe->mlx.data[1], 1, l_key, hermon->lkey ); - MLX_FILL_1 ( &wqe->mlx.data[1], 3, - local_address_l, virt_to_bus ( iobuf->data ) ); - return HERMON_OPCODE_SEND; -} - -/** - * Construct RC send work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v av Address vector - * @v iobuf I/O buffer - * @v wqe Send work queue entry - * @ret opcode Control opcode - */ -static unsigned int -hermon_fill_rc_send_wqe ( struct ib_device *ibdev, - struct ib_queue_pair *qp __unused, - struct ib_address_vector *av __unused, - struct io_buffer *iobuf, - union hermon_send_wqe *wqe ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - - MLX_FILL_1 ( &wqe->rc.ctrl, 1, ds, - ( ( offsetof ( typeof ( wqe->rc ), data[1] ) / 16 ) ) ); - MLX_FILL_1 ( &wqe->rc.ctrl, 2, c, 0x03 /* generate completion */ ); - MLX_FILL_1 ( &wqe->rc.data[0], 0, byte_count, iob_len ( iobuf ) ); - MLX_FILL_1 ( &wqe->rc.data[0], 1, l_key, hermon->lkey ); - MLX_FILL_1 ( &wqe->rc.data[0], 3, - local_address_l, virt_to_bus ( iobuf->data ) ); - return HERMON_OPCODE_SEND; -} - -/** Work queue entry constructors */ -static unsigned int -( * hermon_fill_send_wqe[] ) ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct ib_address_vector *av, - struct io_buffer *iobuf, - union hermon_send_wqe *wqe ) = { - [IB_QPT_SMI] = hermon_fill_mlx_send_wqe, - [IB_QPT_GSI] = hermon_fill_mlx_send_wqe, - [IB_QPT_UD] = hermon_fill_ud_send_wqe, - [IB_QPT_RC] = hermon_fill_rc_send_wqe, -}; - -/** - * Post send work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v av Address vector - * @v iobuf I/O buffer - * @ret rc Return status code - */ -static int hermon_post_send ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct ib_address_vector *av, - struct io_buffer *iobuf ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp ); - struct ib_work_queue *wq = &qp->send; - struct hermon_send_work_queue *hermon_send_wq = &hermon_qp->send; - union hermon_send_wqe *wqe; - union hermonprm_doorbell_register db_reg; - unsigned int wqe_idx_mask; - unsigned int opcode; - - /* Allocate work queue entry */ - wqe_idx_mask = ( wq->num_wqes - 1 ); - if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) { - DBGC ( hermon, "Hermon %p send queue full", hermon ); - return -ENOBUFS; - } - wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf; - wqe = &hermon_send_wq->wqe[ wq->next_idx & - ( hermon_send_wq->num_wqes - 1 ) ]; - - /* Construct work queue entry */ - memset ( ( ( ( void * ) wqe ) + 4 /* avoid ctrl.owner */ ), 0, - ( sizeof ( *wqe ) - 4 ) ); - assert ( qp->type < ( sizeof ( hermon_fill_send_wqe ) / - sizeof ( hermon_fill_send_wqe[0] ) ) ); - assert ( hermon_fill_send_wqe[qp->type] != NULL ); - opcode = hermon_fill_send_wqe[qp->type] ( ibdev, qp, av, iobuf, wqe ); - barrier(); - MLX_FILL_2 ( &wqe->ctrl, 0, - opcode, opcode, - owner, - ( ( wq->next_idx & hermon_send_wq->num_wqes ) ? 1 : 0 ) ); - DBGCP ( hermon, "Hermon %p posting send WQE:\n", hermon ); - DBGCP_HD ( hermon, wqe, sizeof ( *wqe ) ); - barrier(); - - /* Ring doorbell register */ - MLX_FILL_1 ( &db_reg.send, 0, qn, qp->qpn ); - DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n", - virt_to_phys ( hermon_send_wq->doorbell ), db_reg.dword[0] ); - writel ( db_reg.dword[0], ( hermon_send_wq->doorbell ) ); - - /* Update work queue's index */ - wq->next_idx++; - - return 0; -} - -/** - * Post receive work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v iobuf I/O buffer - * @ret rc Return status code - */ -static int hermon_post_recv ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct io_buffer *iobuf ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp ); - struct ib_work_queue *wq = &qp->recv; - struct hermon_recv_work_queue *hermon_recv_wq = &hermon_qp->recv; - struct hermonprm_recv_wqe *wqe; - unsigned int wqe_idx_mask; - - /* Allocate work queue entry */ - wqe_idx_mask = ( wq->num_wqes - 1 ); - if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) { - DBGC ( hermon, "Hermon %p receive queue full", hermon ); - return -ENOBUFS; - } - wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf; - wqe = &hermon_recv_wq->wqe[wq->next_idx & wqe_idx_mask].recv; - - /* Construct work queue entry */ - MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_tailroom ( iobuf ) ); - MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->lkey ); - MLX_FILL_1 ( &wqe->data[0], 3, - local_address_l, virt_to_bus ( iobuf->data ) ); - - /* Update work queue's index */ - wq->next_idx++; - - /* Update doorbell record */ - barrier(); - MLX_FILL_1 ( &hermon_recv_wq->doorbell, 0, receive_wqe_counter, - ( wq->next_idx & 0xffff ) ); - - return 0; -} - -/** - * Handle completion - * - * @v ibdev Infiniband device - * @v cq Completion queue - * @v cqe Hardware completion queue entry - * @ret rc Return status code - */ -static int hermon_complete ( struct ib_device *ibdev, - struct ib_completion_queue *cq, - union hermonprm_completion_entry *cqe ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct ib_work_queue *wq; - struct ib_queue_pair *qp; - struct hermon_queue_pair *hermon_qp; - struct io_buffer *iobuf; - struct ib_address_vector recv_av; - struct ib_global_route_header *grh; - struct ib_address_vector *av; - unsigned int opcode; - unsigned long qpn; - int is_send; - unsigned int wqe_idx; - size_t len; - int rc = 0; - - /* Parse completion */ - qpn = MLX_GET ( &cqe->normal, qpn ); - is_send = MLX_GET ( &cqe->normal, s_r ); - opcode = MLX_GET ( &cqe->normal, opcode ); - if ( opcode >= HERMON_OPCODE_RECV_ERROR ) { - /* "s" field is not valid for error opcodes */ - is_send = ( opcode == HERMON_OPCODE_SEND_ERROR ); - DBGC ( hermon, "Hermon %p CQN %lx syndrome %x vendor %x\n", - hermon, cq->cqn, MLX_GET ( &cqe->error, syndrome ), - MLX_GET ( &cqe->error, vendor_error_syndrome ) ); - rc = -EIO; - /* Don't return immediately; propagate error to completer */ - } - - /* Identify work queue */ - wq = ib_find_wq ( cq, qpn, is_send ); - if ( ! wq ) { - DBGC ( hermon, "Hermon %p CQN %lx unknown %s QPN %lx\n", - hermon, cq->cqn, ( is_send ? "send" : "recv" ), qpn ); - return -EIO; - } - qp = wq->qp; - hermon_qp = ib_qp_get_drvdata ( qp ); - - /* Identify I/O buffer */ - wqe_idx = ( MLX_GET ( &cqe->normal, wqe_counter ) & - ( wq->num_wqes - 1 ) ); - iobuf = wq->iobufs[wqe_idx]; - if ( ! iobuf ) { - DBGC ( hermon, "Hermon %p CQN %lx QPN %lx empty WQE %x\n", - hermon, cq->cqn, qp->qpn, wqe_idx ); - return -EIO; - } - wq->iobufs[wqe_idx] = NULL; - - if ( is_send ) { - /* Hand off to completion handler */ - ib_complete_send ( ibdev, qp, iobuf, rc ); - } else { - /* Set received length */ - len = MLX_GET ( &cqe->normal, byte_cnt ); - assert ( len <= iob_tailroom ( iobuf ) ); - iob_put ( iobuf, len ); - switch ( qp->type ) { - case IB_QPT_SMI: - case IB_QPT_GSI: - case IB_QPT_UD: - assert ( iob_len ( iobuf ) >= sizeof ( *grh ) ); - grh = iobuf->data; - iob_pull ( iobuf, sizeof ( *grh ) ); - /* Construct address vector */ - av = &recv_av; - memset ( av, 0, sizeof ( *av ) ); - av->qpn = MLX_GET ( &cqe->normal, srq_rqpn ); - av->lid = MLX_GET ( &cqe->normal, slid_smac47_32 ); - av->sl = MLX_GET ( &cqe->normal, sl ); - av->gid_present = MLX_GET ( &cqe->normal, g ); - memcpy ( &av->gid, &grh->sgid, sizeof ( av->gid ) ); - break; - case IB_QPT_RC: - av = &qp->av; - break; - default: - assert ( 0 ); - return -EINVAL; - } - /* Hand off to completion handler */ - ib_complete_recv ( ibdev, qp, av, iobuf, rc ); - } - - return rc; -} - -/** - * Poll completion queue - * - * @v ibdev Infiniband device - * @v cq Completion queue - */ -static void hermon_poll_cq ( struct ib_device *ibdev, - struct ib_completion_queue *cq ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq ); - union hermonprm_completion_entry *cqe; - unsigned int cqe_idx_mask; - int rc; - - while ( 1 ) { - /* Look for completion entry */ - cqe_idx_mask = ( cq->num_cqes - 1 ); - cqe = &hermon_cq->cqe[cq->next_idx & cqe_idx_mask]; - if ( MLX_GET ( &cqe->normal, owner ) ^ - ( ( cq->next_idx & cq->num_cqes ) ? 1 : 0 ) ) { - /* Entry still owned by hardware; end of poll */ - break; - } - DBGCP ( hermon, "Hermon %p completion:\n", hermon ); - DBGCP_HD ( hermon, cqe, sizeof ( *cqe ) ); - - /* Handle completion */ - if ( ( rc = hermon_complete ( ibdev, cq, cqe ) ) != 0 ) { - DBGC ( hermon, "Hermon %p failed to complete: %s\n", - hermon, strerror ( rc ) ); - DBGC_HD ( hermon, cqe, sizeof ( *cqe ) ); - } - - /* Update completion queue's index */ - cq->next_idx++; - - /* Update doorbell record */ - MLX_FILL_1 ( &hermon_cq->doorbell, 0, update_ci, - ( cq->next_idx & 0x00ffffffUL ) ); - } -} - -/*************************************************************************** - * - * Event queues - * - *************************************************************************** - */ - -/** - * Create event queue - * - * @v hermon Hermon device - * @ret rc Return status code - */ -static int hermon_create_eq ( struct hermon *hermon ) { - struct hermon_event_queue *hermon_eq = &hermon->eq; - struct hermonprm_eqc eqctx; - struct hermonprm_event_mask mask; - unsigned int i; - int rc; - - /* Select event queue number */ - hermon_eq->eqn = ( 4 * hermon->cap.reserved_uars ); - if ( hermon_eq->eqn < hermon->cap.reserved_eqs ) - hermon_eq->eqn = hermon->cap.reserved_eqs; - - /* Calculate doorbell address */ - hermon_eq->doorbell = - ( hermon->uar + HERMON_DB_EQ_OFFSET ( hermon_eq->eqn ) ); - - /* Allocate event queue itself */ - hermon_eq->eqe_size = - ( HERMON_NUM_EQES * sizeof ( hermon_eq->eqe[0] ) ); - hermon_eq->eqe = malloc_dma ( hermon_eq->eqe_size, - sizeof ( hermon_eq->eqe[0] ) ); - if ( ! hermon_eq->eqe ) { - rc = -ENOMEM; - goto err_eqe; - } - memset ( hermon_eq->eqe, 0, hermon_eq->eqe_size ); - for ( i = 0 ; i < HERMON_NUM_EQES ; i++ ) { - MLX_FILL_1 ( &hermon_eq->eqe[i].generic, 7, owner, 1 ); - } - barrier(); - - /* Allocate MTT entries */ - if ( ( rc = hermon_alloc_mtt ( hermon, hermon_eq->eqe, - hermon_eq->eqe_size, - &hermon_eq->mtt ) ) != 0 ) - goto err_alloc_mtt; - - /* Hand queue over to hardware */ - memset ( &eqctx, 0, sizeof ( eqctx ) ); - MLX_FILL_1 ( &eqctx, 0, st, 0xa /* "Fired" */ ); - MLX_FILL_1 ( &eqctx, 2, - page_offset, ( hermon_eq->mtt.page_offset >> 5 ) ); - MLX_FILL_1 ( &eqctx, 3, log_eq_size, fls ( HERMON_NUM_EQES - 1 ) ); - MLX_FILL_1 ( &eqctx, 7, mtt_base_addr_l, - ( hermon_eq->mtt.mtt_base_addr >> 3 ) ); - if ( ( rc = hermon_cmd_sw2hw_eq ( hermon, hermon_eq->eqn, - &eqctx ) ) != 0 ) { - DBGC ( hermon, "Hermon %p SW2HW_EQ failed: %s\n", - hermon, strerror ( rc ) ); - goto err_sw2hw_eq; - } - - /* Map events to this event queue */ - memset ( &mask, 0, sizeof ( mask ) ); - MLX_FILL_1 ( &mask, 1, port_state_change, 1 ); - if ( ( rc = hermon_cmd_map_eq ( hermon, - ( HERMON_MAP_EQ | hermon_eq->eqn ), - &mask ) ) != 0 ) { - DBGC ( hermon, "Hermon %p MAP_EQ failed: %s\n", - hermon, strerror ( rc ) ); - goto err_map_eq; - } - - DBGC ( hermon, "Hermon %p EQN %#lx ring at [%p,%p])\n", - hermon, hermon_eq->eqn, hermon_eq->eqe, - ( ( ( void * ) hermon_eq->eqe ) + hermon_eq->eqe_size ) ); - return 0; - - err_map_eq: - hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn, &eqctx ); - err_sw2hw_eq: - hermon_free_mtt ( hermon, &hermon_eq->mtt ); - err_alloc_mtt: - free_dma ( hermon_eq->eqe, hermon_eq->eqe_size ); - err_eqe: - memset ( hermon_eq, 0, sizeof ( *hermon_eq ) ); - return rc; -} - -/** - * Destroy event queue - * - * @v hermon Hermon device - */ -static void hermon_destroy_eq ( struct hermon *hermon ) { - struct hermon_event_queue *hermon_eq = &hermon->eq; - struct hermonprm_eqc eqctx; - struct hermonprm_event_mask mask; - int rc; - - /* Unmap events from event queue */ - memset ( &mask, 0, sizeof ( mask ) ); - MLX_FILL_1 ( &mask, 1, port_state_change, 1 ); - if ( ( rc = hermon_cmd_map_eq ( hermon, - ( HERMON_UNMAP_EQ | hermon_eq->eqn ), - &mask ) ) != 0 ) { - DBGC ( hermon, "Hermon %p FATAL MAP_EQ failed to unmap: %s\n", - hermon, strerror ( rc ) ); - /* Continue; HCA may die but system should survive */ - } - - /* Take ownership back from hardware */ - if ( ( rc = hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn, - &eqctx ) ) != 0 ) { - DBGC ( hermon, "Hermon %p FATAL HW2SW_EQ failed: %s\n", - hermon, strerror ( rc ) ); - /* Leak memory and return; at least we avoid corruption */ - return; - } - - /* Free MTT entries */ - hermon_free_mtt ( hermon, &hermon_eq->mtt ); - - /* Free memory */ - free_dma ( hermon_eq->eqe, hermon_eq->eqe_size ); - memset ( hermon_eq, 0, sizeof ( *hermon_eq ) ); -} - -/** - * Handle port state event - * - * @v hermon Hermon device - * @v eqe Port state change event queue entry - */ -static void hermon_event_port_state_change ( struct hermon *hermon, - union hermonprm_event_entry *eqe){ - unsigned int port; - int link_up; - - /* Get port and link status */ - port = ( MLX_GET ( &eqe->port_state_change, data.p ) - 1 ); - link_up = ( MLX_GET ( &eqe->generic, event_sub_type ) & 0x04 ); - DBGC ( hermon, "Hermon %p port %d link %s\n", hermon, ( port + 1 ), - ( link_up ? "up" : "down" ) ); - - /* Sanity check */ - if ( port >= hermon->cap.num_ports ) { - DBGC ( hermon, "Hermon %p port %d does not exist!\n", - hermon, ( port + 1 ) ); - return; - } - - /* Update MAD parameters */ - ib_smc_update ( hermon->ibdev[port], hermon_mad ); - - /* Notify Infiniband core of link state change */ - ib_link_state_changed ( hermon->ibdev[port] ); -} - -/** - * Poll event queue - * - * @v ibdev Infiniband device - */ -static void hermon_poll_eq ( struct ib_device *ibdev ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermon_event_queue *hermon_eq = &hermon->eq; - union hermonprm_event_entry *eqe; - union hermonprm_doorbell_register db_reg; - unsigned int eqe_idx_mask; - unsigned int event_type; - - while ( 1 ) { - /* Look for event entry */ - eqe_idx_mask = ( HERMON_NUM_EQES - 1 ); - eqe = &hermon_eq->eqe[hermon_eq->next_idx & eqe_idx_mask]; - if ( MLX_GET ( &eqe->generic, owner ) ^ - ( ( hermon_eq->next_idx & HERMON_NUM_EQES ) ? 1 : 0 ) ) { - /* Entry still owned by hardware; end of poll */ - break; - } - DBGCP ( hermon, "Hermon %p event:\n", hermon ); - DBGCP_HD ( hermon, eqe, sizeof ( *eqe ) ); - - /* Handle event */ - event_type = MLX_GET ( &eqe->generic, event_type ); - switch ( event_type ) { - case HERMON_EV_PORT_STATE_CHANGE: - hermon_event_port_state_change ( hermon, eqe ); - break; - default: - DBGC ( hermon, "Hermon %p unrecognised event type " - "%#x:\n", hermon, event_type ); - DBGC_HD ( hermon, eqe, sizeof ( *eqe ) ); - break; - } - - /* Update event queue's index */ - hermon_eq->next_idx++; - - /* Ring doorbell */ - MLX_FILL_1 ( &db_reg.event, 0, - ci, ( hermon_eq->next_idx & 0x00ffffffUL ) ); - DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n", - virt_to_phys ( hermon_eq->doorbell ), - db_reg.dword[0] ); - writel ( db_reg.dword[0], hermon_eq->doorbell ); - } -} - -/*************************************************************************** - * - * Infiniband link-layer operations - * - *************************************************************************** - */ - -/** - * Sense port type - * - * @v ibdev Infiniband device - * @ret port_type Port type, or negative error - */ -static int hermon_sense_port_type ( struct ib_device *ibdev ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermonprm_sense_port sense_port; - int port_type; - int rc; - - /* If DPDP is not supported, always assume Infiniband */ - if ( ! hermon->cap.dpdp ) - return HERMON_PORT_TYPE_IB; - - /* Sense the port type */ - if ( ( rc = hermon_cmd_sense_port ( hermon, ibdev->port, - &sense_port ) ) != 0 ) { - DBGC ( hermon, "Hermon %p port %d sense failed: %s\n", - hermon, ibdev->port, strerror ( rc ) ); - return rc; - } - port_type = MLX_GET ( &sense_port, port_type ); - - DBGC ( hermon, "Hermon %p port %d type %d\n", - hermon, ibdev->port, port_type ); - return port_type; -} - -/** - * Initialise Infiniband link - * - * @v ibdev Infiniband device - * @ret rc Return status code - */ -static int hermon_open ( struct ib_device *ibdev ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermonprm_init_port init_port; - int port_type; - int rc; - - /* Check we are connected to an Infiniband network */ - if ( ( rc = port_type = hermon_sense_port_type ( ibdev ) ) < 0 ) - return rc; - if ( port_type != HERMON_PORT_TYPE_IB ) { - DBGC ( hermon, "Hermon %p port %d not connected to an " - "Infiniband network", hermon, ibdev->port ); - return -ENOTCONN; - } - - /* Init Port */ - memset ( &init_port, 0, sizeof ( init_port ) ); - MLX_FILL_2 ( &init_port, 0, - port_width_cap, 3, - vl_cap, 1 ); - MLX_FILL_2 ( &init_port, 1, - mtu, HERMON_MTU_2048, - max_gid, 1 ); - MLX_FILL_1 ( &init_port, 2, max_pkey, 64 ); - if ( ( rc = hermon_cmd_init_port ( hermon, ibdev->port, - &init_port ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not intialise port: %s\n", - hermon, strerror ( rc ) ); - return rc; - } - - /* Update MAD parameters */ - ib_smc_update ( ibdev, hermon_mad ); - - return 0; -} - -/** - * Close Infiniband link - * - * @v ibdev Infiniband device - */ -static void hermon_close ( struct ib_device *ibdev ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - int rc; - - if ( ( rc = hermon_cmd_close_port ( hermon, ibdev->port ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not close port: %s\n", - hermon, strerror ( rc ) ); - /* Nothing we can do about this */ - } -} - -/** - * Inform embedded subnet management agent of a received MAD - * - * @v ibdev Infiniband device - * @v mad MAD - * @ret rc Return status code - */ -static int hermon_inform_sma ( struct ib_device *ibdev, - union ib_mad *mad ) { - int rc; - - /* Send the MAD to the embedded SMA */ - if ( ( rc = hermon_mad ( ibdev, mad ) ) != 0 ) - return rc; - - /* Update parameters held in software */ - ib_smc_update ( ibdev, hermon_mad ); - - return 0; -} - -/*************************************************************************** - * - * Multicast group operations - * - *************************************************************************** - */ - -/** - * Attach to multicast group - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v gid Multicast GID - * @ret rc Return status code - */ -static int hermon_mcast_attach ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct ib_gid *gid ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermonprm_mgm_hash hash; - struct hermonprm_mcg_entry mcg; - unsigned int index; - int rc; - - /* Generate hash table index */ - if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not hash GID: %s\n", - hermon, strerror ( rc ) ); - return rc; - } - index = MLX_GET ( &hash, hash ); - - /* Check for existing hash table entry */ - if ( ( rc = hermon_cmd_read_mcg ( hermon, index, &mcg ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not read MCG %#x: %s\n", - hermon, index, strerror ( rc ) ); - return rc; - } - if ( MLX_GET ( &mcg, hdr.members_count ) != 0 ) { - /* FIXME: this implementation allows only a single QP - * per multicast group, and doesn't handle hash - * collisions. Sufficient for IPoIB but may need to - * be extended in future. - */ - DBGC ( hermon, "Hermon %p MGID index %#x already in use\n", - hermon, index ); - return -EBUSY; - } - - /* Update hash table entry */ - MLX_FILL_1 ( &mcg, 1, hdr.members_count, 1 ); - MLX_FILL_1 ( &mcg, 8, qp[0].qpn, qp->qpn ); - memcpy ( &mcg.u.dwords[4], gid, sizeof ( *gid ) ); - if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n", - hermon, index, strerror ( rc ) ); - return rc; - } - - return 0; -} - -/** - * Detach from multicast group - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v gid Multicast GID - */ -static void hermon_mcast_detach ( struct ib_device *ibdev, - struct ib_queue_pair *qp __unused, - struct ib_gid *gid ) { - struct hermon *hermon = ib_get_drvdata ( ibdev ); - struct hermonprm_mgm_hash hash; - struct hermonprm_mcg_entry mcg; - unsigned int index; - int rc; - - /* Generate hash table index */ - if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not hash GID: %s\n", - hermon, strerror ( rc ) ); - return; - } - index = MLX_GET ( &hash, hash ); - - /* Clear hash table entry */ - memset ( &mcg, 0, sizeof ( mcg ) ); - if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n", - hermon, index, strerror ( rc ) ); - return; - } -} - -/** Hermon Infiniband operations */ -static struct ib_device_operations hermon_ib_operations = { - .create_cq = hermon_create_cq, - .destroy_cq = hermon_destroy_cq, - .create_qp = hermon_create_qp, - .modify_qp = hermon_modify_qp, - .destroy_qp = hermon_destroy_qp, - .post_send = hermon_post_send, - .post_recv = hermon_post_recv, - .poll_cq = hermon_poll_cq, - .poll_eq = hermon_poll_eq, - .open = hermon_open, - .close = hermon_close, - .mcast_attach = hermon_mcast_attach, - .mcast_detach = hermon_mcast_detach, - .set_port_info = hermon_inform_sma, - .set_pkey_table = hermon_inform_sma, -}; - -/*************************************************************************** - * - * Firmware control - * - *************************************************************************** - */ - -/** - * Map virtual to physical address for firmware usage - * - * @v hermon Hermon device - * @v map Mapping function - * @v va Virtual address - * @v pa Physical address - * @v len Length of region - * @ret rc Return status code - */ -static int hermon_map_vpm ( struct hermon *hermon, - int ( *map ) ( struct hermon *hermon, - const struct hermonprm_virtual_physical_mapping* ), - uint64_t va, physaddr_t pa, size_t len ) { - struct hermonprm_virtual_physical_mapping mapping; - int rc; - - assert ( ( va & ( HERMON_PAGE_SIZE - 1 ) ) == 0 ); - assert ( ( pa & ( HERMON_PAGE_SIZE - 1 ) ) == 0 ); - assert ( ( len & ( HERMON_PAGE_SIZE - 1 ) ) == 0 ); - - /* These mappings tend to generate huge volumes of - * uninteresting debug data, which basically makes it - * impossible to use debugging otherwise. - */ - DBG_DISABLE ( DBGLVL_LOG | DBGLVL_EXTRA ); - - while ( len ) { - memset ( &mapping, 0, sizeof ( mapping ) ); - MLX_FILL_1 ( &mapping, 0, va_h, ( va >> 32 ) ); - MLX_FILL_1 ( &mapping, 1, va_l, ( va >> 12 ) ); - MLX_FILL_2 ( &mapping, 3, - log2size, 0, - pa_l, ( pa >> 12 ) ); - if ( ( rc = map ( hermon, &mapping ) ) != 0 ) { - DBG_ENABLE ( DBGLVL_LOG | DBGLVL_EXTRA ); - DBGC ( hermon, "Hermon %p could not map %llx => %lx: " - "%s\n", hermon, va, pa, strerror ( rc ) ); - return rc; - } - pa += HERMON_PAGE_SIZE; - va += HERMON_PAGE_SIZE; - len -= HERMON_PAGE_SIZE; - } - - DBG_ENABLE ( DBGLVL_LOG | DBGLVL_EXTRA ); - return 0; -} - -/** - * Start firmware running - * - * @v hermon Hermon device - * @ret rc Return status code - */ -static int hermon_start_firmware ( struct hermon *hermon ) { - struct hermonprm_query_fw fw; - unsigned int fw_pages; - size_t fw_size; - physaddr_t fw_base; - int rc; - - /* Get firmware parameters */ - if ( ( rc = hermon_cmd_query_fw ( hermon, &fw ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not query firmware: %s\n", - hermon, strerror ( rc ) ); - goto err_query_fw; - } - DBGC ( hermon, "Hermon %p firmware version %d.%d.%d\n", hermon, - MLX_GET ( &fw, fw_rev_major ), MLX_GET ( &fw, fw_rev_minor ), - MLX_GET ( &fw, fw_rev_subminor ) ); - fw_pages = MLX_GET ( &fw, fw_pages ); - DBGC ( hermon, "Hermon %p requires %d pages (%d kB) for firmware\n", - hermon, fw_pages, ( fw_pages * ( HERMON_PAGE_SIZE / 1024 ) ) ); - - /* Allocate firmware pages and map firmware area */ - fw_size = ( fw_pages * HERMON_PAGE_SIZE ); - hermon->firmware_area = umalloc ( fw_size ); - if ( ! hermon->firmware_area ) { - rc = -ENOMEM; - goto err_alloc_fa; - } - fw_base = user_to_phys ( hermon->firmware_area, 0 ); - DBGC ( hermon, "Hermon %p firmware area at physical [%lx,%lx)\n", - hermon, fw_base, ( fw_base + fw_size ) ); - if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_fa, - 0, fw_base, fw_size ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not map firmware: %s\n", - hermon, strerror ( rc ) ); - goto err_map_fa; - } - - /* Start firmware */ - if ( ( rc = hermon_cmd_run_fw ( hermon ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not run firmware: %s\n", - hermon, strerror ( rc ) ); - goto err_run_fw; - } - - DBGC ( hermon, "Hermon %p firmware started\n", hermon ); - return 0; - - err_run_fw: - err_map_fa: - hermon_cmd_unmap_fa ( hermon ); - ufree ( hermon->firmware_area ); - hermon->firmware_area = UNULL; - err_alloc_fa: - err_query_fw: - return rc; -} - -/** - * Stop firmware running - * - * @v hermon Hermon device - */ -static void hermon_stop_firmware ( struct hermon *hermon ) { - int rc; - - if ( ( rc = hermon_cmd_unmap_fa ( hermon ) ) != 0 ) { - DBGC ( hermon, "Hermon %p FATAL could not stop firmware: %s\n", - hermon, strerror ( rc ) ); - /* Leak memory and return; at least we avoid corruption */ - return; - } - ufree ( hermon->firmware_area ); - hermon->firmware_area = UNULL; -} - -/*************************************************************************** - * - * Infinihost Context Memory management - * - *************************************************************************** - */ - -/** - * Get device limits - * - * @v hermon Hermon device - * @ret rc Return status code - */ -static int hermon_get_cap ( struct hermon *hermon ) { - struct hermonprm_query_dev_cap dev_cap; - int rc; - - if ( ( rc = hermon_cmd_query_dev_cap ( hermon, &dev_cap ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not get device limits: %s\n", - hermon, strerror ( rc ) ); - return rc; - } - - hermon->cap.cmpt_entry_size = MLX_GET ( &dev_cap, c_mpt_entry_sz ); - hermon->cap.reserved_qps = - ( 1 << MLX_GET ( &dev_cap, log2_rsvd_qps ) ); - hermon->cap.qpc_entry_size = MLX_GET ( &dev_cap, qpc_entry_sz ); - hermon->cap.altc_entry_size = MLX_GET ( &dev_cap, altc_entry_sz ); - hermon->cap.auxc_entry_size = MLX_GET ( &dev_cap, aux_entry_sz ); - hermon->cap.reserved_srqs = - ( 1 << MLX_GET ( &dev_cap, log2_rsvd_srqs ) ); - hermon->cap.srqc_entry_size = MLX_GET ( &dev_cap, srq_entry_sz ); - hermon->cap.reserved_cqs = - ( 1 << MLX_GET ( &dev_cap, log2_rsvd_cqs ) ); - hermon->cap.cqc_entry_size = MLX_GET ( &dev_cap, cqc_entry_sz ); - hermon->cap.reserved_eqs = MLX_GET ( &dev_cap, num_rsvd_eqs ); - hermon->cap.eqc_entry_size = MLX_GET ( &dev_cap, eqc_entry_sz ); - hermon->cap.reserved_mtts = - ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mtts ) ); - hermon->cap.mtt_entry_size = MLX_GET ( &dev_cap, mtt_entry_sz ); - hermon->cap.reserved_mrws = - ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mrws ) ); - hermon->cap.dmpt_entry_size = MLX_GET ( &dev_cap, d_mpt_entry_sz ); - hermon->cap.reserved_uars = MLX_GET ( &dev_cap, num_rsvd_uars ); - hermon->cap.num_ports = MLX_GET ( &dev_cap, num_ports ); - hermon->cap.dpdp = MLX_GET ( &dev_cap, dpdp ); - - /* Sanity check */ - if ( hermon->cap.num_ports > HERMON_MAX_PORTS ) { - DBGC ( hermon, "Hermon %p has %d ports (only %d supported)\n", - hermon, hermon->cap.num_ports, HERMON_MAX_PORTS ); - hermon->cap.num_ports = HERMON_MAX_PORTS; - } - - return 0; -} - -/** - * Get ICM usage - * - * @v log_num_entries Log2 of the number of entries - * @v entry_size Entry size - * @ret usage Usage size in ICM - */ -static size_t icm_usage ( unsigned int log_num_entries, size_t entry_size ) { - size_t usage; - - usage = ( ( 1 << log_num_entries ) * entry_size ); - usage = ( ( usage + HERMON_PAGE_SIZE - 1 ) & - ~( HERMON_PAGE_SIZE - 1 ) ); - return usage; -} - -/** - * Allocate ICM - * - * @v hermon Hermon device - * @v init_hca INIT_HCA structure to fill in - * @ret rc Return status code - */ -static int hermon_alloc_icm ( struct hermon *hermon, - struct hermonprm_init_hca *init_hca ) { - struct hermonprm_scalar_parameter icm_size; - struct hermonprm_scalar_parameter icm_aux_size; - uint64_t icm_offset = 0; - unsigned int log_num_qps, log_num_srqs, log_num_cqs, log_num_eqs; - unsigned int log_num_mtts, log_num_mpts; - size_t cmpt_max_len; - size_t qp_cmpt_len, srq_cmpt_len, cq_cmpt_len, eq_cmpt_len; - size_t icm_len, icm_aux_len; - physaddr_t icm_phys; - int i; - int rc; - - /* - * Start by carving up the ICM virtual address space - * - */ - - /* Calculate number of each object type within ICM */ - log_num_qps = fls ( hermon->cap.reserved_qps + - HERMON_RSVD_SPECIAL_QPS + HERMON_MAX_QPS - 1 ); - log_num_srqs = fls ( hermon->cap.reserved_srqs - 1 ); - log_num_cqs = fls ( hermon->cap.reserved_cqs + HERMON_MAX_CQS - 1 ); - log_num_eqs = fls ( hermon->cap.reserved_eqs + HERMON_MAX_EQS - 1 ); - log_num_mtts = fls ( hermon->cap.reserved_mtts + HERMON_MAX_MTTS - 1 ); - - /* ICM starts with the cMPT tables, which are sparse */ - cmpt_max_len = ( HERMON_CMPT_MAX_ENTRIES * - ( ( uint64_t ) hermon->cap.cmpt_entry_size ) ); - qp_cmpt_len = icm_usage ( log_num_qps, hermon->cap.cmpt_entry_size ); - hermon->icm_map[HERMON_ICM_QP_CMPT].offset = icm_offset; - hermon->icm_map[HERMON_ICM_QP_CMPT].len = qp_cmpt_len; - icm_offset += cmpt_max_len; - srq_cmpt_len = icm_usage ( log_num_srqs, hermon->cap.cmpt_entry_size ); - hermon->icm_map[HERMON_ICM_SRQ_CMPT].offset = icm_offset; - hermon->icm_map[HERMON_ICM_SRQ_CMPT].len = srq_cmpt_len; - icm_offset += cmpt_max_len; - cq_cmpt_len = icm_usage ( log_num_cqs, hermon->cap.cmpt_entry_size ); - hermon->icm_map[HERMON_ICM_CQ_CMPT].offset = icm_offset; - hermon->icm_map[HERMON_ICM_CQ_CMPT].len = cq_cmpt_len; - icm_offset += cmpt_max_len; - eq_cmpt_len = icm_usage ( log_num_eqs, hermon->cap.cmpt_entry_size ); - hermon->icm_map[HERMON_ICM_EQ_CMPT].offset = icm_offset; - hermon->icm_map[HERMON_ICM_EQ_CMPT].len = eq_cmpt_len; - icm_offset += cmpt_max_len; - - hermon->icm_map[HERMON_ICM_OTHER].offset = icm_offset; - - /* Queue pair contexts */ - MLX_FILL_1 ( init_hca, 12, - qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_h, - ( icm_offset >> 32 ) ); - MLX_FILL_2 ( init_hca, 13, - qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_l, - ( icm_offset >> 5 ), - qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp, - log_num_qps ); - DBGC ( hermon, "Hermon %p ICM QPC base = %llx\n", hermon, icm_offset ); - icm_offset += icm_usage ( log_num_qps, hermon->cap.qpc_entry_size ); - - /* Extended alternate path contexts */ - MLX_FILL_1 ( init_hca, 24, - qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_h, - ( icm_offset >> 32 ) ); - MLX_FILL_1 ( init_hca, 25, - qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_l, - icm_offset ); - DBGC ( hermon, "Hermon %p ICM ALTC base = %llx\n", hermon, icm_offset); - icm_offset += icm_usage ( log_num_qps, - hermon->cap.altc_entry_size ); - - /* Extended auxiliary contexts */ - MLX_FILL_1 ( init_hca, 28, - qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_h, - ( icm_offset >> 32 ) ); - MLX_FILL_1 ( init_hca, 29, - qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_l, - icm_offset ); - DBGC ( hermon, "Hermon %p ICM AUXC base = %llx\n", hermon, icm_offset); - icm_offset += icm_usage ( log_num_qps, - hermon->cap.auxc_entry_size ); - - /* Shared receive queue contexts */ - MLX_FILL_1 ( init_hca, 18, - qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_h, - ( icm_offset >> 32 ) ); - MLX_FILL_2 ( init_hca, 19, - qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_l, - ( icm_offset >> 5 ), - qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq, - log_num_srqs ); - DBGC ( hermon, "Hermon %p ICM SRQC base = %llx\n", hermon, icm_offset); - icm_offset += icm_usage ( log_num_srqs, - hermon->cap.srqc_entry_size ); - - /* Completion queue contexts */ - MLX_FILL_1 ( init_hca, 20, - qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_h, - ( icm_offset >> 32 ) ); - MLX_FILL_2 ( init_hca, 21, - qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_l, - ( icm_offset >> 5 ), - qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq, - log_num_cqs ); - DBGC ( hermon, "Hermon %p ICM CQC base = %llx\n", hermon, icm_offset ); - icm_offset += icm_usage ( log_num_cqs, hermon->cap.cqc_entry_size ); - - /* Event queue contexts */ - MLX_FILL_1 ( init_hca, 32, - qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_h, - ( icm_offset >> 32 ) ); - MLX_FILL_2 ( init_hca, 33, - qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_l, - ( icm_offset >> 5 ), - qpc_eec_cqc_eqc_rdb_parameters.log_num_of_eq, - log_num_eqs ); - DBGC ( hermon, "Hermon %p ICM EQC base = %llx\n", hermon, icm_offset ); - icm_offset += icm_usage ( log_num_eqs, hermon->cap.eqc_entry_size ); - - /* Memory translation table */ - MLX_FILL_1 ( init_hca, 64, - tpt_parameters.mtt_base_addr_h, ( icm_offset >> 32 ) ); - MLX_FILL_1 ( init_hca, 65, - tpt_parameters.mtt_base_addr_l, icm_offset ); - DBGC ( hermon, "Hermon %p ICM MTT base = %llx\n", hermon, icm_offset ); - icm_offset += icm_usage ( log_num_mtts, - hermon->cap.mtt_entry_size ); - - /* Memory protection table */ - log_num_mpts = fls ( hermon->cap.reserved_mrws + 1 - 1 ); - MLX_FILL_1 ( init_hca, 60, - tpt_parameters.dmpt_base_adr_h, ( icm_offset >> 32 ) ); - MLX_FILL_1 ( init_hca, 61, - tpt_parameters.dmpt_base_adr_l, icm_offset ); - MLX_FILL_1 ( init_hca, 62, - tpt_parameters.log_dmpt_sz, log_num_mpts ); - DBGC ( hermon, "Hermon %p ICM DMPT base = %llx\n", hermon, icm_offset); - icm_offset += icm_usage ( log_num_mpts, - hermon->cap.dmpt_entry_size ); - - /* Multicast table */ - MLX_FILL_1 ( init_hca, 48, - multicast_parameters.mc_base_addr_h, - ( icm_offset >> 32 ) ); - MLX_FILL_1 ( init_hca, 49, - multicast_parameters.mc_base_addr_l, icm_offset ); - MLX_FILL_1 ( init_hca, 52, - multicast_parameters.log_mc_table_entry_sz, - fls ( sizeof ( struct hermonprm_mcg_entry ) - 1 ) ); - MLX_FILL_1 ( init_hca, 53, - multicast_parameters.log_mc_table_hash_sz, 3 ); - MLX_FILL_1 ( init_hca, 54, - multicast_parameters.log_mc_table_sz, 3 ); - DBGC ( hermon, "Hermon %p ICM MC base = %llx\n", hermon, icm_offset ); - icm_offset += ( ( 8 * sizeof ( struct hermonprm_mcg_entry ) + - HERMON_PAGE_SIZE - 1 ) & ~( HERMON_PAGE_SIZE - 1 ) ); - - hermon->icm_map[HERMON_ICM_OTHER].len = - ( icm_offset - hermon->icm_map[HERMON_ICM_OTHER].offset ); - - /* - * Allocate and map physical memory for (portions of) ICM - * - * Map is: - * ICM AUX area (aligned to its own size) - * cMPT areas - * Other areas - */ - - /* Calculate physical memory required for ICM */ - icm_len = 0; - for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) { - icm_len += hermon->icm_map[i].len; - } - - /* Get ICM auxiliary area size */ - memset ( &icm_size, 0, sizeof ( icm_size ) ); - MLX_FILL_1 ( &icm_size, 0, value_hi, ( icm_offset >> 32 ) ); - MLX_FILL_1 ( &icm_size, 1, value, icm_offset ); - if ( ( rc = hermon_cmd_set_icm_size ( hermon, &icm_size, - &icm_aux_size ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not set ICM size: %s\n", - hermon, strerror ( rc ) ); - goto err_set_icm_size; - } - icm_aux_len = ( MLX_GET ( &icm_aux_size, value ) * HERMON_PAGE_SIZE ); - - /* Allocate ICM data and auxiliary area */ - DBGC ( hermon, "Hermon %p requires %zd kB ICM and %zd kB AUX ICM\n", - hermon, ( icm_len / 1024 ), ( icm_aux_len / 1024 ) ); - hermon->icm = umalloc ( icm_aux_len + icm_len ); - if ( ! hermon->icm ) { - rc = -ENOMEM; - goto err_alloc; - } - icm_phys = user_to_phys ( hermon->icm, 0 ); - - /* Map ICM auxiliary area */ - DBGC ( hermon, "Hermon %p mapping ICM AUX => %08lx\n", - hermon, icm_phys ); - if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm_aux, - 0, icm_phys, icm_aux_len ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not map AUX ICM: %s\n", - hermon, strerror ( rc ) ); - goto err_map_icm_aux; - } - icm_phys += icm_aux_len; - - /* MAP ICM area */ - for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) { - DBGC ( hermon, "Hermon %p mapping ICM %llx+%zx => %08lx\n", - hermon, hermon->icm_map[i].offset, - hermon->icm_map[i].len, icm_phys ); - if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm, - hermon->icm_map[i].offset, - icm_phys, - hermon->icm_map[i].len ) ) != 0 ){ - DBGC ( hermon, "Hermon %p could not map ICM: %s\n", - hermon, strerror ( rc ) ); - goto err_map_icm; - } - icm_phys += hermon->icm_map[i].len; - } - - return 0; - - err_map_icm: - assert ( i == 0 ); /* We don't handle partial failure at present */ - err_map_icm_aux: - hermon_cmd_unmap_icm_aux ( hermon ); - ufree ( hermon->icm ); - hermon->icm = UNULL; - err_alloc: - err_set_icm_size: - return rc; -} - -/** - * Free ICM - * - * @v hermon Hermon device - */ -static void hermon_free_icm ( struct hermon *hermon ) { - struct hermonprm_scalar_parameter unmap_icm; - int i; - - for ( i = ( HERMON_ICM_NUM_REGIONS - 1 ) ; i >= 0 ; i-- ) { - memset ( &unmap_icm, 0, sizeof ( unmap_icm ) ); - MLX_FILL_1 ( &unmap_icm, 0, value_hi, - ( hermon->icm_map[i].offset >> 32 ) ); - MLX_FILL_1 ( &unmap_icm, 1, value, - hermon->icm_map[i].offset ); - hermon_cmd_unmap_icm ( hermon, - ( 1 << fls ( ( hermon->icm_map[i].len / - HERMON_PAGE_SIZE ) - 1)), - &unmap_icm ); - } - hermon_cmd_unmap_icm_aux ( hermon ); - ufree ( hermon->icm ); - hermon->icm = UNULL; -} - -/*************************************************************************** - * - * PCI interface - * - *************************************************************************** - */ - -/** - * Set up memory protection table - * - * @v hermon Hermon device - * @ret rc Return status code - */ -static int hermon_setup_mpt ( struct hermon *hermon ) { - struct hermonprm_mpt mpt; - uint32_t key; - int rc; - - /* Derive key */ - key = ( hermon->cap.reserved_mrws | HERMON_MKEY_PREFIX ); - hermon->lkey = ( ( key << 8 ) | ( key >> 24 ) ); - - /* Initialise memory protection table */ - memset ( &mpt, 0, sizeof ( mpt ) ); - MLX_FILL_7 ( &mpt, 0, - atomic, 1, - rw, 1, - rr, 1, - lw, 1, - lr, 1, - pa, 1, - r_w, 1 ); - MLX_FILL_1 ( &mpt, 2, mem_key, key ); - MLX_FILL_1 ( &mpt, 3, - pd, HERMON_GLOBAL_PD ); - MLX_FILL_1 ( &mpt, 10, len64, 1 ); - if ( ( rc = hermon_cmd_sw2hw_mpt ( hermon, - hermon->cap.reserved_mrws, - &mpt ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not set up MPT: %s\n", - hermon, strerror ( rc ) ); - return rc; - } - - return 0; -} - -/** - * Configure special queue pairs - * - * @v hermon Hermon device - * @ret rc Return status code - */ -static int hermon_configure_special_qps ( struct hermon *hermon ) { - int rc; - - /* Special QP block must be aligned on its own size */ - hermon->special_qpn_base = ( ( hermon->cap.reserved_qps + - HERMON_NUM_SPECIAL_QPS - 1 ) - & ~( HERMON_NUM_SPECIAL_QPS - 1 ) ); - hermon->qpn_base = ( hermon->special_qpn_base + - HERMON_NUM_SPECIAL_QPS ); - DBGC ( hermon, "Hermon %p special QPs at [%lx,%lx]\n", hermon, - hermon->special_qpn_base, ( hermon->qpn_base - 1 ) ); - - /* Issue command to configure special QPs */ - if ( ( rc = hermon_cmd_conf_special_qp ( hermon, 0x00, - hermon->special_qpn_base ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not configure special QPs: " - "%s\n", hermon, strerror ( rc ) ); - return rc; - } - - return 0; -} - -/** - * Reset device - * - * @v hermon Hermon device - * @v pci PCI device - */ -static void hermon_reset ( struct hermon *hermon, - struct pci_device *pci ) { - struct pci_config_backup backup; - static const uint8_t backup_exclude[] = - PCI_CONFIG_BACKUP_EXCLUDE ( 0x58, 0x5c ); - - pci_backup ( pci, &backup, backup_exclude ); - writel ( HERMON_RESET_MAGIC, - ( hermon->config + HERMON_RESET_OFFSET ) ); - mdelay ( HERMON_RESET_WAIT_TIME_MS ); - pci_restore ( pci, &backup, backup_exclude ); -} - -/** - * Probe PCI device - * - * @v pci PCI device - * @v id PCI ID - * @ret rc Return status code - */ -static int hermon_probe ( struct pci_device *pci, - const struct pci_device_id *id __unused ) { - struct hermon *hermon; - struct ib_device *ibdev; - struct hermonprm_init_hca init_hca; - unsigned int i; - int rc; - - /* Allocate Hermon device */ - hermon = zalloc ( sizeof ( *hermon ) ); - if ( ! hermon ) { - rc = -ENOMEM; - goto err_alloc_hermon; - } - pci_set_drvdata ( pci, hermon ); - - /* Fix up PCI device */ - adjust_pci_device ( pci ); - - /* Get PCI BARs */ - hermon->config = ioremap ( pci_bar_start ( pci, HERMON_PCI_CONFIG_BAR), - HERMON_PCI_CONFIG_BAR_SIZE ); - hermon->uar = ioremap ( pci_bar_start ( pci, HERMON_PCI_UAR_BAR ), - HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE ); - - /* Reset device */ - hermon_reset ( hermon, pci ); - - /* Allocate space for mailboxes */ - hermon->mailbox_in = malloc_dma ( HERMON_MBOX_SIZE, - HERMON_MBOX_ALIGN ); - if ( ! hermon->mailbox_in ) { - rc = -ENOMEM; - goto err_mailbox_in; - } - hermon->mailbox_out = malloc_dma ( HERMON_MBOX_SIZE, - HERMON_MBOX_ALIGN ); - if ( ! hermon->mailbox_out ) { - rc = -ENOMEM; - goto err_mailbox_out; - } - - /* Start firmware */ - if ( ( rc = hermon_start_firmware ( hermon ) ) != 0 ) - goto err_start_firmware; - - /* Get device limits */ - if ( ( rc = hermon_get_cap ( hermon ) ) != 0 ) - goto err_get_cap; - - /* Allocate Infiniband devices */ - for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) { - ibdev = alloc_ibdev ( 0 ); - if ( ! ibdev ) { - rc = -ENOMEM; - goto err_alloc_ibdev; - } - hermon->ibdev[i] = ibdev; - ibdev->op = &hermon_ib_operations; - ibdev->dev = &pci->dev; - ibdev->port = ( HERMON_PORT_BASE + i ); - ib_set_drvdata ( ibdev, hermon ); - } - - /* Allocate ICM */ - memset ( &init_hca, 0, sizeof ( init_hca ) ); - if ( ( rc = hermon_alloc_icm ( hermon, &init_hca ) ) != 0 ) - goto err_alloc_icm; - - /* Initialise HCA */ - MLX_FILL_1 ( &init_hca, 0, version, 0x02 /* "Must be 0x02" */ ); - MLX_FILL_1 ( &init_hca, 5, udp, 1 ); - MLX_FILL_1 ( &init_hca, 74, uar_parameters.log_max_uars, 8 ); - if ( ( rc = hermon_cmd_init_hca ( hermon, &init_hca ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not initialise HCA: %s\n", - hermon, strerror ( rc ) ); - goto err_init_hca; - } - - /* Set up memory protection */ - if ( ( rc = hermon_setup_mpt ( hermon ) ) != 0 ) - goto err_setup_mpt; - for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) - hermon->ibdev[i]->rdma_key = hermon->lkey; - - /* Set up event queue */ - if ( ( rc = hermon_create_eq ( hermon ) ) != 0 ) - goto err_create_eq; - - /* Configure special QPs */ - if ( ( rc = hermon_configure_special_qps ( hermon ) ) != 0 ) - goto err_conf_special_qps; - - /* Update IPoIB MAC address */ - for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) { - ib_smc_update ( hermon->ibdev[i], hermon_mad ); - } - - /* Register Infiniband devices */ - for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) { - if ( ( rc = register_ibdev ( hermon->ibdev[i] ) ) != 0 ) { - DBGC ( hermon, "Hermon %p could not register IB " - "device: %s\n", hermon, strerror ( rc ) ); - goto err_register_ibdev; - } - } - - return 0; - - i = hermon->cap.num_ports; - err_register_ibdev: - for ( i-- ; ( signed int ) i >= 0 ; i-- ) - unregister_ibdev ( hermon->ibdev[i] ); - err_conf_special_qps: - hermon_destroy_eq ( hermon ); - err_create_eq: - err_setup_mpt: - hermon_cmd_close_hca ( hermon ); - err_init_hca: - hermon_free_icm ( hermon ); - err_alloc_icm: - i = hermon->cap.num_ports; - err_alloc_ibdev: - for ( i-- ; ( signed int ) i >= 0 ; i-- ) - ibdev_put ( hermon->ibdev[i] ); - err_get_cap: - hermon_stop_firmware ( hermon ); - err_start_firmware: - free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE ); - err_mailbox_out: - free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE ); - err_mailbox_in: - free ( hermon ); - err_alloc_hermon: - return rc; -} - -/** - * Remove PCI device - * - * @v pci PCI device - */ -static void hermon_remove ( struct pci_device *pci ) { - struct hermon *hermon = pci_get_drvdata ( pci ); - int i; - - for ( i = ( hermon->cap.num_ports - 1 ) ; i >= 0 ; i-- ) - unregister_ibdev ( hermon->ibdev[i] ); - hermon_destroy_eq ( hermon ); - hermon_cmd_close_hca ( hermon ); - hermon_free_icm ( hermon ); - hermon_stop_firmware ( hermon ); - hermon_stop_firmware ( hermon ); - free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE ); - free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE ); - for ( i = ( hermon->cap.num_ports - 1 ) ; i >= 0 ; i-- ) - ibdev_put ( hermon->ibdev[i] ); - free ( hermon ); -} - -static struct pci_device_id hermon_nics[] = { - PCI_ROM ( 0x15b3, 0x6340, "mt25408", "MT25408 HCA driver", 0 ), - PCI_ROM ( 0x15b3, 0x634a, "mt25418", "MT25418 HCA driver", 0 ), - PCI_ROM ( 0x15b3, 0x6732, "mt26418", "MT26418 HCA driver", 0 ), - PCI_ROM ( 0x15b3, 0x673c, "mt26428", "MT26428 HCA driver", 0 ), -}; - -struct pci_driver hermon_driver __pci_driver = { - .ids = hermon_nics, - .id_count = ( sizeof ( hermon_nics ) / sizeof ( hermon_nics[0] ) ), - .probe = hermon_probe, - .remove = hermon_remove, -}; diff --git a/gpxe/src/drivers/infiniband/hermon.h b/gpxe/src/drivers/infiniband/hermon.h deleted file mode 100644 index c53f3da5..00000000 --- a/gpxe/src/drivers/infiniband/hermon.h +++ /dev/null @@ -1,610 +0,0 @@ -#ifndef _HERMON_H -#define _HERMON_H - -/** @file - * - * Mellanox Hermon Infiniband HCA driver - * - */ - -FILE_LICENCE ( GPL2_OR_LATER ); - -#include <stdint.h> -#include <gpxe/uaccess.h> -#include <gpxe/ib_packet.h> -#include "mlx_bitops.h" -#include "MT25408_PRM.h" - -/* - * Hardware constants - * - */ - -/* Ports in existence */ -#define HERMON_MAX_PORTS 2 -#define HERMON_PORT_BASE 1 - -/* PCI BARs */ -#define HERMON_PCI_CONFIG_BAR PCI_BASE_ADDRESS_0 -#define HERMON_PCI_CONFIG_BAR_SIZE 0x100000 -#define HERMON_PCI_UAR_BAR PCI_BASE_ADDRESS_2 - -/* Device reset */ -#define HERMON_RESET_OFFSET 0x0f0010 -#define HERMON_RESET_MAGIC 0x01000000UL -#define HERMON_RESET_WAIT_TIME_MS 1000 - -/* Work queue entry and completion queue entry opcodes */ -#define HERMON_OPCODE_NOP 0x00 -#define HERMON_OPCODE_SEND 0x0a -#define HERMON_OPCODE_RECV_ERROR 0xfe -#define HERMON_OPCODE_SEND_ERROR 0xff - -/* HCA command register opcodes */ -#define HERMON_HCR_QUERY_DEV_CAP 0x0003 -#define HERMON_HCR_QUERY_FW 0x0004 -#define HERMON_HCR_INIT_HCA 0x0007 -#define HERMON_HCR_CLOSE_HCA 0x0008 -#define HERMON_HCR_INIT_PORT 0x0009 -#define HERMON_HCR_CLOSE_PORT 0x000a -#define HERMON_HCR_SW2HW_MPT 0x000d -#define HERMON_HCR_WRITE_MTT 0x0011 -#define HERMON_HCR_MAP_EQ 0x0012 -#define HERMON_HCR_SW2HW_EQ 0x0013 -#define HERMON_HCR_HW2SW_EQ 0x0014 -#define HERMON_HCR_QUERY_EQ 0x0015 -#define HERMON_HCR_SW2HW_CQ 0x0016 -#define HERMON_HCR_HW2SW_CQ 0x0017 -#define HERMON_HCR_RST2INIT_QP 0x0019 -#define HERMON_HCR_INIT2RTR_QP 0x001a -#define HERMON_HCR_RTR2RTS_QP 0x001b -#define HERMON_HCR_RTS2RTS_QP 0x001c -#define HERMON_HCR_2RST_QP 0x0021 -#define HERMON_HCR_QUERY_QP 0x0022 -#define HERMON_HCR_CONF_SPECIAL_QP 0x0023 -#define HERMON_HCR_MAD_IFC 0x0024 -#define HERMON_HCR_READ_MCG 0x0025 -#define HERMON_HCR_WRITE_MCG 0x0026 -#define HERMON_HCR_MGID_HASH 0x0027 -#define HERMON_HCR_SENSE_PORT 0x004d -#define HERMON_HCR_RUN_FW 0x0ff6 -#define HERMON_HCR_DISABLE_LAM 0x0ff7 -#define HERMON_HCR_ENABLE_LAM 0x0ff8 -#define HERMON_HCR_UNMAP_ICM 0x0ff9 -#define HERMON_HCR_MAP_ICM 0x0ffa -#define HERMON_HCR_UNMAP_ICM_AUX 0x0ffb -#define HERMON_HCR_MAP_ICM_AUX 0x0ffc -#define HERMON_HCR_SET_ICM_SIZE 0x0ffd -#define HERMON_HCR_UNMAP_FA 0x0ffe -#define HERMON_HCR_MAP_FA 0x0fff - -/* Service types */ -#define HERMON_ST_RC 0x00 -#define HERMON_ST_UD 0x03 -#define HERMON_ST_MLX 0x07 - -/* MTUs */ -#define HERMON_MTU_2048 0x04 - -#define HERMON_INVALID_LKEY 0x00000100UL - -#define HERMON_PAGE_SIZE 4096 - -#define HERMON_DB_POST_SND_OFFSET 0x14 -#define HERMON_DB_EQ_OFFSET(_eqn) \ - ( 0x800 + HERMON_PAGE_SIZE * ( (_eqn) / 4 ) + 0x08 * ( (_eqn) % 4 ) ) - -#define HERMON_QP_OPT_PARAM_PM_STATE 0x00000400UL -#define HERMON_QP_OPT_PARAM_QKEY 0x00000020UL -#define HERMON_QP_OPT_PARAM_ALT_PATH 0x00000001UL - -#define HERMON_MAP_EQ ( 0UL << 31 ) -#define HERMON_UNMAP_EQ ( 1UL << 31 ) - -#define HERMON_EV_PORT_STATE_CHANGE 0x09 - -#define HERMON_SCHED_QP0 0x3f -#define HERMON_SCHED_DEFAULT 0x83 - -#define HERMON_PM_STATE_ARMED 0x00 -#define HERMON_PM_STATE_REARM 0x01 -#define HERMON_PM_STATE_MIGRATED 0x03 - -#define HERMON_RETRY_MAX 0x07 - -/* - * Datatypes that seem to be missing from the autogenerated documentation - * - */ -struct hermonprm_mgm_hash_st { - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t hash[0x00010]; - pseudo_bit_t reserved1[0x00010]; -} __attribute__ (( packed )); - -struct hermonprm_mcg_entry_st { - struct hermonprm_mcg_hdr_st hdr; - struct hermonprm_mcg_qp_dw_st qp[8]; -} __attribute__ (( packed )); - -struct hermonprm_cq_db_record_st { - pseudo_bit_t update_ci[0x00018]; - pseudo_bit_t reserved0[0x00008]; -/* -------------- */ - pseudo_bit_t arm_ci[0x00018]; - pseudo_bit_t cmd[0x00003]; - pseudo_bit_t reserved1[0x00001]; - pseudo_bit_t cmd_sn[0x00002]; - pseudo_bit_t reserved2[0x00002]; -} __attribute__ (( packed )); - -struct hermonprm_send_db_register_st { - pseudo_bit_t reserved[0x00008]; - pseudo_bit_t qn[0x00018]; -} __attribute__ (( packed )); - -struct hermonprm_event_db_register_st { - pseudo_bit_t ci[0x00018]; - pseudo_bit_t reserver[0x00007]; - pseudo_bit_t a[0x00001]; -} __attribute__ (( packed )); - -struct hermonprm_scalar_parameter_st { - pseudo_bit_t value_hi[0x00020]; -/* -------------- */ - pseudo_bit_t value[0x00020]; -} __attribute__ (( packed )); - -struct hermonprm_event_mask_st { - pseudo_bit_t reserved0[0x00020]; -/* -------------- */ - pseudo_bit_t completion[0x00001]; - pseudo_bit_t reserved1[0x0008]; - pseudo_bit_t port_state_change[0x00001]; - pseudo_bit_t reserved2[0x00016]; -} __attribute__ (( packed )); - -struct hermonprm_port_state_change_event_st { - pseudo_bit_t reserved[0x00020]; - struct hermonprm_port_state_change_st data; -} __attribute__ (( packed )); - -/** Hermon sense port */ -struct hermonprm_sense_port_st { - pseudo_bit_t port_type[0x00020]; -/* -------------- */ - pseudo_bit_t reserved[0x00020]; -}; -#define HERMON_PORT_TYPE_IB 1 - -/* - * Wrapper structures for hardware datatypes - * - */ - -struct MLX_DECLARE_STRUCT ( hermonprm_completion_queue_context ); -struct MLX_DECLARE_STRUCT ( hermonprm_completion_queue_entry ); -struct MLX_DECLARE_STRUCT ( hermonprm_completion_with_error ); -struct MLX_DECLARE_STRUCT ( hermonprm_cq_db_record ); -struct MLX_DECLARE_STRUCT ( hermonprm_eqc ); -struct MLX_DECLARE_STRUCT ( hermonprm_event_db_register ); -struct MLX_DECLARE_STRUCT ( hermonprm_event_mask ); -struct MLX_DECLARE_STRUCT ( hermonprm_event_queue_entry ); -struct MLX_DECLARE_STRUCT ( hermonprm_hca_command_register ); -struct MLX_DECLARE_STRUCT ( hermonprm_init_hca ); -struct MLX_DECLARE_STRUCT ( hermonprm_init_port ); -struct MLX_DECLARE_STRUCT ( hermonprm_mad_ifc ); -struct MLX_DECLARE_STRUCT ( hermonprm_mcg_entry ); -struct MLX_DECLARE_STRUCT ( hermonprm_mgm_hash ); -struct MLX_DECLARE_STRUCT ( hermonprm_mpt ); -struct MLX_DECLARE_STRUCT ( hermonprm_mtt ); -struct MLX_DECLARE_STRUCT ( hermonprm_port_state_change_event ); -struct MLX_DECLARE_STRUCT ( hermonprm_qp_db_record ); -struct MLX_DECLARE_STRUCT ( hermonprm_qp_ee_state_transitions ); -struct MLX_DECLARE_STRUCT ( hermonprm_query_dev_cap ); -struct MLX_DECLARE_STRUCT ( hermonprm_query_fw ); -struct MLX_DECLARE_STRUCT ( hermonprm_queue_pair_ee_context_entry ); -struct MLX_DECLARE_STRUCT ( hermonprm_scalar_parameter ); -struct MLX_DECLARE_STRUCT ( hermonprm_sense_port ); -struct MLX_DECLARE_STRUCT ( hermonprm_send_db_register ); -struct MLX_DECLARE_STRUCT ( hermonprm_ud_address_vector ); -struct MLX_DECLARE_STRUCT ( hermonprm_virtual_physical_mapping ); -struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_ctrl_mlx ); -struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_ctrl_send ); -struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_data_ptr ); -struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_ud ); - -/* - * Composite hardware datatypes - * - */ - -struct hermonprm_write_mtt { - struct hermonprm_scalar_parameter mtt_base_addr; - struct hermonprm_scalar_parameter reserved; - struct hermonprm_mtt mtt; -} __attribute__ (( packed )); - -#define HERMON_MAX_GATHER 2 - -struct hermonprm_ud_send_wqe { - struct hermonprm_wqe_segment_ctrl_send ctrl; - struct hermonprm_wqe_segment_ud ud; - struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_GATHER]; -} __attribute__ (( packed )); - -struct hermonprm_mlx_send_wqe { - struct hermonprm_wqe_segment_ctrl_mlx ctrl; - struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_GATHER]; - uint8_t headers[IB_MAX_HEADER_SIZE]; -} __attribute__ (( packed )); - -struct hermonprm_rc_send_wqe { - struct hermonprm_wqe_segment_ctrl_send ctrl; - struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_GATHER]; -} __attribute__ (( packed )); - -#define HERMON_MAX_SCATTER 1 - -struct hermonprm_recv_wqe { - struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_SCATTER]; -} __attribute__ (( packed )); - -union hermonprm_completion_entry { - struct hermonprm_completion_queue_entry normal; - struct hermonprm_completion_with_error error; -} __attribute__ (( packed )); - -union hermonprm_event_entry { - struct hermonprm_event_queue_entry generic; - struct hermonprm_port_state_change_event port_state_change; -} __attribute__ (( packed )); - -union hermonprm_doorbell_register { - struct hermonprm_send_db_register send; - struct hermonprm_event_db_register event; - uint32_t dword[1]; -} __attribute__ (( packed )); - -union hermonprm_mad { - struct hermonprm_mad_ifc ifc; - union ib_mad mad; -} __attribute__ (( packed )); - -/* - * gPXE-specific definitions - * - */ - -/** Hermon device capabilitiess */ -struct hermon_dev_cap { - /** CMPT entry size */ - size_t cmpt_entry_size; - /** Number of reserved QPs */ - unsigned int reserved_qps; - /** QP context entry size */ - size_t qpc_entry_size; - /** Alternate path context entry size */ - size_t altc_entry_size; - /** Auxiliary context entry size */ - size_t auxc_entry_size; - /** Number of reserved SRQs */ - unsigned int reserved_srqs; - /** SRQ context entry size */ - size_t srqc_entry_size; - /** Number of reserved CQs */ - unsigned int reserved_cqs; - /** CQ context entry size */ - size_t cqc_entry_size; - /** Number of reserved EQs */ - unsigned int reserved_eqs; - /** EQ context entry size */ - size_t eqc_entry_size; - /** Number of reserved MTTs */ - unsigned int reserved_mtts; - /** MTT entry size */ - size_t mtt_entry_size; - /** Number of reserved MRWs */ - unsigned int reserved_mrws; - /** DMPT entry size */ - size_t dmpt_entry_size; - /** Number of reserved UARs */ - unsigned int reserved_uars; - /** Number of ports */ - unsigned int num_ports; - /** Dual-port different protocol */ - int dpdp; -}; - -/** Number of cMPT entries of each type */ -#define HERMON_CMPT_MAX_ENTRIES ( 1 << 24 ) - -/** Hermon ICM memory map entry */ -struct hermon_icm_map { - /** Offset (virtual address within ICM) */ - uint64_t offset; - /** Length */ - size_t len; -}; - -/** Discontiguous regions within Hermon ICM */ -enum hermon_icm_map_regions { - HERMON_ICM_QP_CMPT = 0, - HERMON_ICM_SRQ_CMPT, - HERMON_ICM_CQ_CMPT, - HERMON_ICM_EQ_CMPT, - HERMON_ICM_OTHER, - HERMON_ICM_NUM_REGIONS -}; - -/** UAR page for doorbell accesses - * - * Pages 0-127 are reserved for event queue doorbells only, so we use - * page 128. - */ -#define HERMON_UAR_NON_EQ_PAGE 128 - -/** Maximum number of allocatable MTT entries - * - * This is a policy decision, not a device limit. - */ -#define HERMON_MAX_MTTS 64 - -/** A Hermon MTT descriptor */ -struct hermon_mtt { - /** MTT offset */ - unsigned int mtt_offset; - /** Number of pages */ - unsigned int num_pages; - /** MTT base address */ - unsigned int mtt_base_addr; - /** Offset within page */ - unsigned int page_offset; -}; - -/** Alignment of Hermon send work queue entries */ -#define HERMON_SEND_WQE_ALIGN 128 - -/** A Hermon send work queue entry */ -union hermon_send_wqe { - struct hermonprm_wqe_segment_ctrl_send ctrl; - struct hermonprm_ud_send_wqe ud; - struct hermonprm_mlx_send_wqe mlx; - struct hermonprm_rc_send_wqe rc; - uint8_t force_align[HERMON_SEND_WQE_ALIGN]; -} __attribute__ (( packed )); - -/** A Hermon send work queue */ -struct hermon_send_work_queue { - /** Number of work queue entries, including headroom - * - * Hermon requires us to leave unused space within the send - * WQ, so we create a send WQ with more entries than are - * requested in the create_qp() call. - */ - unsigned int num_wqes; - /** Work queue entries */ - union hermon_send_wqe *wqe; - /** Size of work queue */ - size_t wqe_size; - /** Doorbell register */ - void *doorbell; -}; - -/** Alignment of Hermon receive work queue entries */ -#define HERMON_RECV_WQE_ALIGN 16 - -/** A Hermon receive work queue entry */ -union hermon_recv_wqe { - struct hermonprm_recv_wqe recv; - uint8_t force_align[HERMON_RECV_WQE_ALIGN]; -} __attribute__ (( packed )); - -/** A Hermon receive work queue */ -struct hermon_recv_work_queue { - /** Work queue entries */ - union hermon_recv_wqe *wqe; - /** Size of work queue */ - size_t wqe_size; - /** Doorbell */ - struct hermonprm_qp_db_record doorbell __attribute__ (( aligned (4) )); -}; - -/** Number of special queue pairs */ -#define HERMON_NUM_SPECIAL_QPS 8 - -/** Number of queue pairs reserved for the "special QP" block - * - * The special QPs must be within a contiguous block aligned on its - * own size. - */ -#define HERMON_RSVD_SPECIAL_QPS ( ( HERMON_NUM_SPECIAL_QPS << 1 ) - 1 ) - -/** Maximum number of allocatable queue pairs - * - * This is a policy decision, not a device limit. - */ -#define HERMON_MAX_QPS 8 - -/** Queue pair number randomisation mask */ -#define HERMON_QPN_RANDOM_MASK 0xfff000 - -/** Hermon queue pair state */ -enum hermon_queue_pair_state { - HERMON_QP_ST_RST = 0, - HERMON_QP_ST_INIT, - HERMON_QP_ST_RTR, - HERMON_QP_ST_RTS, -}; - -/** A Hermon queue pair */ -struct hermon_queue_pair { - /** Work queue buffer */ - void *wqe; - /** Size of work queue buffer */ - size_t wqe_size; - /** MTT descriptor */ - struct hermon_mtt mtt; - /** Send work queue */ - struct hermon_send_work_queue send; - /** Receive work queue */ - struct hermon_recv_work_queue recv; - /** Queue state */ - enum hermon_queue_pair_state state; -}; - -/** Maximum number of allocatable completion queues - * - * This is a policy decision, not a device limit. - */ -#define HERMON_MAX_CQS 8 - -/** A Hermon completion queue */ -struct hermon_completion_queue { - /** Completion queue entries */ - union hermonprm_completion_entry *cqe; - /** Size of completion queue */ - size_t cqe_size; - /** MTT descriptor */ - struct hermon_mtt mtt; - /** Doorbell */ - struct hermonprm_cq_db_record doorbell __attribute__ (( aligned (8) )); -}; - -/** Maximum number of allocatable event queues - * - * This is a policy decision, not a device limit. - */ -#define HERMON_MAX_EQS 8 - -/** A Hermon event queue */ -struct hermon_event_queue { - /** Event queue entries */ - union hermonprm_event_entry *eqe; - /** Size of event queue */ - size_t eqe_size; - /** MTT descriptor */ - struct hermon_mtt mtt; - /** Event queue number */ - unsigned long eqn; - /** Next event queue entry index */ - unsigned long next_idx; - /** Doorbell register */ - void *doorbell; -}; - -/** Number of event queue entries - * - * This is a policy decision. - */ -#define HERMON_NUM_EQES 4 - -/** A Hermon resource bitmask */ -typedef uint32_t hermon_bitmask_t; - -/** Size of a hermon resource bitmask */ -#define HERMON_BITMASK_SIZE(max_entries) \ - ( ( (max_entries) + ( 8 * sizeof ( hermon_bitmask_t ) ) - 1 ) / \ - ( 8 * sizeof ( hermon_bitmask_t ) ) ) - -/** A Hermon device */ -struct hermon { - /** PCI configuration registers */ - void *config; - /** PCI user Access Region */ - void *uar; - - /** Command toggle */ - unsigned int toggle; - /** Command input mailbox */ - void *mailbox_in; - /** Command output mailbox */ - void *mailbox_out; - - /** Firmware area in external memory */ - userptr_t firmware_area; - /** ICM map */ - struct hermon_icm_map icm_map[HERMON_ICM_NUM_REGIONS]; - /** ICM area */ - userptr_t icm; - - /** Event queue */ - struct hermon_event_queue eq; - /** Unrestricted LKey - * - * Used to get unrestricted memory access. - */ - unsigned long lkey; - - /** Completion queue in-use bitmask */ - hermon_bitmask_t cq_inuse[ HERMON_BITMASK_SIZE ( HERMON_MAX_CQS ) ]; - /** Queue pair in-use bitmask */ - hermon_bitmask_t qp_inuse[ HERMON_BITMASK_SIZE ( HERMON_MAX_QPS ) ]; - /** MTT entry in-use bitmask */ - hermon_bitmask_t mtt_inuse[ HERMON_BITMASK_SIZE ( HERMON_MAX_MTTS ) ]; - - /** Device capabilities */ - struct hermon_dev_cap cap; - /** Special QPN base */ - unsigned long special_qpn_base; - /** QPN base */ - unsigned long qpn_base; - - /** Infiniband devices */ - struct ib_device *ibdev[HERMON_MAX_PORTS]; -}; - -/** Global protection domain */ -#define HERMON_GLOBAL_PD 0x123456 - -/** Memory key prefix */ -#define HERMON_MKEY_PREFIX 0x77000000UL - -/* - * HCA commands - * - */ - -#define HERMON_HCR_BASE 0x80680 -#define HERMON_HCR_REG(x) ( HERMON_HCR_BASE + 4 * (x) ) -#define HERMON_HCR_MAX_WAIT_MS 2000 -#define HERMON_MBOX_ALIGN 4096 -#define HERMON_MBOX_SIZE 512 - -/* HCA command is split into - * - * bits 11:0 Opcode - * bit 12 Input uses mailbox - * bit 13 Output uses mailbox - * bits 22:14 Input parameter length (in dwords) - * bits 31:23 Output parameter length (in dwords) - * - * Encoding the information in this way allows us to cut out several - * parameters to the hermon_command() call. - */ -#define HERMON_HCR_IN_MBOX 0x00001000UL -#define HERMON_HCR_OUT_MBOX 0x00002000UL -#define HERMON_HCR_OPCODE( _command ) ( (_command) & 0xfff ) -#define HERMON_HCR_IN_LEN( _command ) ( ( (_command) >> 12 ) & 0x7fc ) -#define HERMON_HCR_OUT_LEN( _command ) ( ( (_command) >> 21 ) & 0x7fc ) - -/** Build HCR command from component parts */ -#define HERMON_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len, \ - _out_mbox, _out_len ) \ - ( (_opcode) | \ - ( (_in_mbox) ? HERMON_HCR_IN_MBOX : 0 ) | \ - ( ( (_in_len) / 4 ) << 14 ) | \ - ( (_out_mbox) ? HERMON_HCR_OUT_MBOX : 0 ) | \ - ( ( (_out_len) / 4 ) << 23 ) ) - -#define HERMON_HCR_IN_CMD( _opcode, _in_mbox, _in_len ) \ - HERMON_HCR_INOUT_CMD ( _opcode, _in_mbox, _in_len, 0, 0 ) - -#define HERMON_HCR_OUT_CMD( _opcode, _out_mbox, _out_len ) \ - HERMON_HCR_INOUT_CMD ( _opcode, 0, 0, _out_mbox, _out_len ) - -#define HERMON_HCR_VOID_CMD( _opcode ) \ - HERMON_HCR_INOUT_CMD ( _opcode, 0, 0, 0, 0 ) - -#endif /* _HERMON_H */ diff --git a/gpxe/src/drivers/infiniband/linda.c b/gpxe/src/drivers/infiniband/linda.c deleted file mode 100644 index b9a7ba58..00000000 --- a/gpxe/src/drivers/infiniband/linda.c +++ /dev/null @@ -1,2432 +0,0 @@ -/* - * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -FILE_LICENCE ( GPL2_OR_LATER ); - -#include <stdint.h> -#include <stdlib.h> -#include <errno.h> -#include <unistd.h> -#include <assert.h> -#include <gpxe/io.h> -#include <gpxe/pci.h> -#include <gpxe/infiniband.h> -#include <gpxe/i2c.h> -#include <gpxe/bitbash.h> -#include <gpxe/malloc.h> -#include <gpxe/iobuf.h> -#include "linda.h" - -/** - * @file - * - * QLogic Linda Infiniband HCA - * - */ - -/** A Linda send work queue */ -struct linda_send_work_queue { - /** Send buffer usage */ - uint8_t *send_buf; - /** Producer index */ - unsigned int prod; - /** Consumer index */ - unsigned int cons; -}; - -/** A Linda receive work queue */ -struct linda_recv_work_queue { - /** Receive header ring */ - void *header; - /** Receive header producer offset (written by hardware) */ - struct QIB_7220_scalar header_prod; - /** Receive header consumer offset */ - unsigned int header_cons; - /** Offset within register space of the eager array */ - unsigned long eager_array; - /** Number of entries in eager array */ - unsigned int eager_entries; - /** Eager array producer index */ - unsigned int eager_prod; - /** Eager array consumer index */ - unsigned int eager_cons; -}; - -/** A Linda HCA */ -struct linda { - /** Registers */ - void *regs; - - /** In-use contexts */ - uint8_t used_ctx[LINDA_NUM_CONTEXTS]; - /** Send work queues */ - struct linda_send_work_queue send_wq[LINDA_NUM_CONTEXTS]; - /** Receive work queues */ - struct linda_recv_work_queue recv_wq[LINDA_NUM_CONTEXTS]; - - /** Offset within register space of the first send buffer */ - unsigned long send_buffer_base; - /** Send buffer availability (reported by hardware) */ - struct QIB_7220_SendBufAvail *sendbufavail; - /** Send buffer availability (maintained by software) */ - uint8_t send_buf[LINDA_MAX_SEND_BUFS]; - /** Send buffer availability producer counter */ - unsigned int send_buf_prod; - /** Send buffer availability consumer counter */ - unsigned int send_buf_cons; - /** Number of reserved send buffers (across all QPs) */ - unsigned int reserved_send_bufs; - - /** I2C bit-bashing interface */ - struct i2c_bit_basher i2c; - /** I2C serial EEPROM */ - struct i2c_device eeprom; -}; - -/*************************************************************************** - * - * Linda register access - * - *************************************************************************** - * - * This card requires atomic 64-bit accesses. Strange things happen - * if you try to use 32-bit accesses; sometimes they work, sometimes - * they don't, sometimes you get random data. - * - * These accessors use the "movq" MMX instruction, and so won't work - * on really old Pentiums (which won't have PCIe anyway, so this is - * something of a moot point). - */ - -/** - * Read Linda qword register - * - * @v linda Linda device - * @v dwords Register buffer to read into - * @v offset Register offset - */ -static void linda_readq ( struct linda *linda, uint32_t *dwords, - unsigned long offset ) { - void *addr = ( linda->regs + offset ); - - __asm__ __volatile__ ( "movq (%1), %%mm0\n\t" - "movq %%mm0, (%0)\n\t" - : : "r" ( dwords ), "r" ( addr ) : "memory" ); - - DBGIO ( "[%08lx] => %08x%08x\n", - virt_to_phys ( addr ), dwords[1], dwords[0] ); -} -#define linda_readq( _linda, _ptr, _offset ) \ - linda_readq ( (_linda), (_ptr)->u.dwords, (_offset) ) -#define linda_readq_array8b( _linda, _ptr, _offset, _idx ) \ - linda_readq ( (_linda), (_ptr), ( (_offset) + ( (_idx) * 8 ) ) ) -#define linda_readq_array64k( _linda, _ptr, _offset, _idx ) \ - linda_readq ( (_linda), (_ptr), ( (_offset) + ( (_idx) * 65536 ) ) ) - -/** - * Write Linda qword register - * - * @v linda Linda device - * @v dwords Register buffer to write - * @v offset Register offset - */ -static void linda_writeq ( struct linda *linda, const uint32_t *dwords, - unsigned long offset ) { - void *addr = ( linda->regs + offset ); - - DBGIO ( "[%08lx] <= %08x%08x\n", - virt_to_phys ( addr ), dwords[1], dwords[0] ); - - __asm__ __volatile__ ( "movq (%0), %%mm0\n\t" - "movq %%mm0, (%1)\n\t" - : : "r" ( dwords ), "r" ( addr ) : "memory" ); -} -#define linda_writeq( _linda, _ptr, _offset ) \ - linda_writeq ( (_linda), (_ptr)->u.dwords, (_offset) ) -#define linda_writeq_array8b( _linda, _ptr, _offset, _idx ) \ - linda_writeq ( (_linda), (_ptr), ( (_offset) + ( (_idx) * 8 ) ) ) -#define linda_writeq_array64k( _linda, _ptr, _offset, _idx ) \ - linda_writeq ( (_linda), (_ptr), ( (_offset) + ( (_idx) * 65536 ) ) ) - -/** - * Write Linda dword register - * - * @v linda Linda device - * @v dword Value to write - * @v offset Register offset - */ -static void linda_writel ( struct linda *linda, uint32_t dword, - unsigned long offset ) { - writel ( dword, ( linda->regs + offset ) ); -} - -/*************************************************************************** - * - * Link state management - * - *************************************************************************** - */ - -/** - * Textual representation of link state - * - * @v link_state Link state - * @ret link_text Link state text - */ -static const char * linda_link_state_text ( unsigned int link_state ) { - switch ( link_state ) { - case LINDA_LINK_STATE_DOWN: return "DOWN"; - case LINDA_LINK_STATE_INIT: return "INIT"; - case LINDA_LINK_STATE_ARM: return "ARM"; - case LINDA_LINK_STATE_ACTIVE: return "ACTIVE"; - case LINDA_LINK_STATE_ACT_DEFER:return "ACT_DEFER"; - default: return "UNKNOWN"; - } -} - -/** - * Handle link state change - * - * @v linda Linda device - */ -static void linda_link_state_changed ( struct ib_device *ibdev ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct QIB_7220_IBCStatus ibcstatus; - struct QIB_7220_EXTCtrl extctrl; - unsigned int link_state; - unsigned int link_width; - unsigned int link_speed; - - /* Read link state */ - linda_readq ( linda, &ibcstatus, QIB_7220_IBCStatus_offset ); - link_state = BIT_GET ( &ibcstatus, LinkState ); - link_width = BIT_GET ( &ibcstatus, LinkWidthActive ); - link_speed = BIT_GET ( &ibcstatus, LinkSpeedActive ); - DBGC ( linda, "Linda %p link state %s (%s %s)\n", linda, - linda_link_state_text ( link_state ), - ( link_speed ? "DDR" : "SDR" ), ( link_width ? "x4" : "x1" ) ); - - /* Set LEDs according to link state */ - linda_readq ( linda, &extctrl, QIB_7220_EXTCtrl_offset ); - BIT_SET ( &extctrl, LEDPriPortGreenOn, - ( ( link_state >= LINDA_LINK_STATE_INIT ) ? 1 : 0 ) ); - BIT_SET ( &extctrl, LEDPriPortYellowOn, - ( ( link_state >= LINDA_LINK_STATE_ACTIVE ) ? 1 : 0 ) ); - linda_writeq ( linda, &extctrl, QIB_7220_EXTCtrl_offset ); - - /* Notify Infiniband core of link state change */ - ibdev->port_state = ( link_state + 1 ); - ibdev->link_width_active = - ( link_width ? IB_LINK_WIDTH_4X : IB_LINK_WIDTH_1X ); - ibdev->link_speed_active = - ( link_speed ? IB_LINK_SPEED_DDR : IB_LINK_SPEED_SDR ); - ib_link_state_changed ( ibdev ); -} - -/** - * Wait for link state change to take effect - * - * @v linda Linda device - * @v new_link_state Expected link state - * @ret rc Return status code - */ -static int linda_link_state_check ( struct linda *linda, - unsigned int new_link_state ) { - struct QIB_7220_IBCStatus ibcstatus; - unsigned int link_state; - unsigned int i; - - for ( i = 0 ; i < LINDA_LINK_STATE_MAX_WAIT_US ; i++ ) { - linda_readq ( linda, &ibcstatus, QIB_7220_IBCStatus_offset ); - link_state = BIT_GET ( &ibcstatus, LinkState ); - if ( link_state == new_link_state ) - return 0; - udelay ( 1 ); - } - - DBGC ( linda, "Linda %p timed out waiting for link state %s\n", - linda, linda_link_state_text ( link_state ) ); - return -ETIMEDOUT; -} - -/** - * Set port information - * - * @v ibdev Infiniband device - * @v mad Set port information MAD - */ -static int linda_set_port_info ( struct ib_device *ibdev, union ib_mad *mad ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct ib_port_info *port_info = &mad->smp.smp_data.port_info; - struct QIB_7220_IBCCtrl ibcctrl; - unsigned int port_state; - unsigned int link_state; - - /* Set new link state */ - port_state = ( port_info->link_speed_supported__port_state & 0xf ); - if ( port_state ) { - link_state = ( port_state - 1 ); - DBGC ( linda, "Linda %p set link state to %s (%x)\n", linda, - linda_link_state_text ( link_state ), link_state ); - linda_readq ( linda, &ibcctrl, QIB_7220_IBCCtrl_offset ); - BIT_SET ( &ibcctrl, LinkCmd, link_state ); - linda_writeq ( linda, &ibcctrl, QIB_7220_IBCCtrl_offset ); - - /* Wait for link state change to take effect. Ignore - * errors; the current link state will be returned via - * the GetResponse MAD. - */ - linda_link_state_check ( linda, link_state ); - } - - /* Detect and report link state change */ - linda_link_state_changed ( ibdev ); - - return 0; -} - -/** - * Set partition key table - * - * @v ibdev Infiniband device - * @v mad Set partition key table MAD - */ -static int linda_set_pkey_table ( struct ib_device *ibdev __unused, - union ib_mad *mad __unused ) { - /* Nothing to do */ - return 0; -} - -/*************************************************************************** - * - * Context allocation - * - *************************************************************************** - */ - -/** - * Map context number to QPN - * - * @v ctx Context index - * @ret qpn Queue pair number - */ -static int linda_ctx_to_qpn ( unsigned int ctx ) { - /* This mapping is fixed by hardware */ - return ( ctx * 2 ); -} - -/** - * Map QPN to context number - * - * @v qpn Queue pair number - * @ret ctx Context index - */ -static int linda_qpn_to_ctx ( unsigned int qpn ) { - /* This mapping is fixed by hardware */ - return ( qpn / 2 ); -} - -/** - * Allocate a context - * - * @v linda Linda device - * @ret ctx Context index, or negative error - */ -static int linda_alloc_ctx ( struct linda *linda ) { - unsigned int ctx; - - for ( ctx = 0 ; ctx < LINDA_NUM_CONTEXTS ; ctx++ ) { - - if ( ! linda->used_ctx[ctx] ) { - linda->used_ctx[ctx ] = 1; - DBGC2 ( linda, "Linda %p CTX %d allocated\n", - linda, ctx ); - return ctx; - } - } - - DBGC ( linda, "Linda %p out of available contexts\n", linda ); - return -ENOENT; -} - -/** - * Free a context - * - * @v linda Linda device - * @v ctx Context index - */ -static void linda_free_ctx ( struct linda *linda, unsigned int ctx ) { - - linda->used_ctx[ctx] = 0; - DBGC2 ( linda, "Linda %p CTX %d freed\n", linda, ctx ); -} - -/*************************************************************************** - * - * Send datapath - * - *************************************************************************** - */ - -/** Send buffer toggle bit - * - * We encode send buffers as 7 bits of send buffer index plus a single - * bit which should match the "check" bit in the SendBufAvail array. - */ -#define LINDA_SEND_BUF_TOGGLE 0x80 - -/** - * Allocate a send buffer - * - * @v linda Linda device - * @ret send_buf Send buffer - * - * You must guarantee that a send buffer is available. This is done - * by refusing to allocate more TX WQEs in total than the number of - * available send buffers. - */ -static unsigned int linda_alloc_send_buf ( struct linda *linda ) { - unsigned int send_buf; - - send_buf = linda->send_buf[linda->send_buf_cons]; - send_buf ^= LINDA_SEND_BUF_TOGGLE; - linda->send_buf_cons = ( ( linda->send_buf_cons + 1 ) % - LINDA_MAX_SEND_BUFS ); - return send_buf; -} - -/** - * Free a send buffer - * - * @v linda Linda device - * @v send_buf Send buffer - */ -static void linda_free_send_buf ( struct linda *linda, - unsigned int send_buf ) { - linda->send_buf[linda->send_buf_prod] = send_buf; - linda->send_buf_prod = ( ( linda->send_buf_prod + 1 ) % - LINDA_MAX_SEND_BUFS ); -} - -/** - * Check to see if send buffer is in use - * - * @v linda Linda device - * @v send_buf Send buffer - * @ret in_use Send buffer is in use - */ -static int linda_send_buf_in_use ( struct linda *linda, - unsigned int send_buf ) { - unsigned int send_idx; - unsigned int send_check; - unsigned int inusecheck; - unsigned int inuse; - unsigned int check; - - send_idx = ( send_buf & ~LINDA_SEND_BUF_TOGGLE ); - send_check = ( !! ( send_buf & LINDA_SEND_BUF_TOGGLE ) ); - inusecheck = BIT_GET ( linda->sendbufavail, InUseCheck[send_idx] ); - inuse = ( !! ( inusecheck & 0x02 ) ); - check = ( !! ( inusecheck & 0x01 ) ); - return ( inuse || ( check != send_check ) ); -} - -/** - * Calculate starting offset for send buffer - * - * @v linda Linda device - * @v send_buf Send buffer - * @ret offset Starting offset - */ -static unsigned long linda_send_buffer_offset ( struct linda *linda, - unsigned int send_buf ) { - return ( linda->send_buffer_base + - ( ( send_buf & ~LINDA_SEND_BUF_TOGGLE ) * - LINDA_SEND_BUF_SIZE ) ); -} - -/** - * Create send work queue - * - * @v linda Linda device - * @v qp Queue pair - */ -static int linda_create_send_wq ( struct linda *linda, - struct ib_queue_pair *qp ) { - struct ib_work_queue *wq = &qp->send; - struct linda_send_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - int rc; - - /* Reserve send buffers */ - if ( ( linda->reserved_send_bufs + qp->send.num_wqes ) > - LINDA_MAX_SEND_BUFS ) { - DBGC ( linda, "Linda %p out of send buffers (have %d, used " - "%d, need %d)\n", linda, LINDA_MAX_SEND_BUFS, - linda->reserved_send_bufs, qp->send.num_wqes ); - rc = -ENOBUFS; - goto err_reserve_bufs; - } - linda->reserved_send_bufs += qp->send.num_wqes; - - /* Reset work queue */ - linda_wq->prod = 0; - linda_wq->cons = 0; - - /* Allocate space for send buffer uasge list */ - linda_wq->send_buf = zalloc ( qp->send.num_wqes * - sizeof ( linda_wq->send_buf[0] ) ); - if ( ! linda_wq->send_buf ) { - rc = -ENOBUFS; - goto err_alloc_send_buf; - } - - return 0; - - free ( linda_wq->send_buf ); - err_alloc_send_buf: - linda->reserved_send_bufs -= qp->send.num_wqes; - err_reserve_bufs: - return rc; -} - -/** - * Destroy send work queue - * - * @v linda Linda device - * @v qp Queue pair - */ -static void linda_destroy_send_wq ( struct linda *linda, - struct ib_queue_pair *qp ) { - struct ib_work_queue *wq = &qp->send; - struct linda_send_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - - free ( linda_wq->send_buf ); - linda->reserved_send_bufs -= qp->send.num_wqes; -} - -/** - * Initialise send datapath - * - * @v linda Linda device - * @ret rc Return status code - */ -static int linda_init_send ( struct linda *linda ) { - struct QIB_7220_SendBufBase sendbufbase; - struct QIB_7220_SendBufAvailAddr sendbufavailaddr; - struct QIB_7220_SendCtrl sendctrl; - unsigned int i; - int rc; - - /* Retrieve SendBufBase */ - linda_readq ( linda, &sendbufbase, QIB_7220_SendBufBase_offset ); - linda->send_buffer_base = BIT_GET ( &sendbufbase, - BaseAddr_SmallPIO ); - DBGC ( linda, "Linda %p send buffers at %lx\n", - linda, linda->send_buffer_base ); - - /* Initialise the send_buf[] array */ - for ( i = 0 ; i < LINDA_MAX_SEND_BUFS ; i++ ) - linda->send_buf[i] = i; - - /* Allocate space for the SendBufAvail array */ - linda->sendbufavail = malloc_dma ( sizeof ( *linda->sendbufavail ), - LINDA_SENDBUFAVAIL_ALIGN ); - if ( ! linda->sendbufavail ) { - rc = -ENOMEM; - goto err_alloc_sendbufavail; - } - memset ( linda->sendbufavail, 0, sizeof ( linda->sendbufavail ) ); - - /* Program SendBufAvailAddr into the hardware */ - memset ( &sendbufavailaddr, 0, sizeof ( sendbufavailaddr ) ); - BIT_FILL_1 ( &sendbufavailaddr, SendBufAvailAddr, - ( virt_to_bus ( linda->sendbufavail ) >> 6 ) ); - linda_writeq ( linda, &sendbufavailaddr, - QIB_7220_SendBufAvailAddr_offset ); - - /* Enable sending and DMA of SendBufAvail */ - memset ( &sendctrl, 0, sizeof ( sendctrl ) ); - BIT_FILL_2 ( &sendctrl, - SendBufAvailUpd, 1, - SPioEnable, 1 ); - linda_writeq ( linda, &sendctrl, QIB_7220_SendCtrl_offset ); - - return 0; - - free_dma ( linda->sendbufavail, sizeof ( *linda->sendbufavail ) ); - err_alloc_sendbufavail: - return rc; -} - -/** - * Shut down send datapath - * - * @v linda Linda device - */ -static void linda_fini_send ( struct linda *linda ) { - struct QIB_7220_SendCtrl sendctrl; - - /* Disable sending and DMA of SendBufAvail */ - memset ( &sendctrl, 0, sizeof ( sendctrl ) ); - linda_writeq ( linda, &sendctrl, QIB_7220_SendCtrl_offset ); - mb(); - - /* Ensure hardware has seen this disable */ - linda_readq ( linda, &sendctrl, QIB_7220_SendCtrl_offset ); - - free_dma ( linda->sendbufavail, sizeof ( *linda->sendbufavail ) ); -} - -/*************************************************************************** - * - * Receive datapath - * - *************************************************************************** - */ - -/** - * Create receive work queue - * - * @v linda Linda device - * @v qp Queue pair - * @ret rc Return status code - */ -static int linda_create_recv_wq ( struct linda *linda, - struct ib_queue_pair *qp ) { - struct ib_work_queue *wq = &qp->recv; - struct linda_recv_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - struct QIB_7220_RcvHdrAddr0 rcvhdraddr; - struct QIB_7220_RcvHdrTailAddr0 rcvhdrtailaddr; - struct QIB_7220_RcvHdrHead0 rcvhdrhead; - struct QIB_7220_scalar rcvegrindexhead; - struct QIB_7220_RcvCtrl rcvctrl; - unsigned int ctx = linda_qpn_to_ctx ( qp->qpn ); - int rc; - - /* Reset context information */ - memset ( &linda_wq->header_prod, 0, - sizeof ( linda_wq->header_prod ) ); - linda_wq->header_cons = 0; - linda_wq->eager_prod = 0; - linda_wq->eager_cons = 0; - - /* Allocate receive header buffer */ - linda_wq->header = malloc_dma ( LINDA_RECV_HEADERS_SIZE, - LINDA_RECV_HEADERS_ALIGN ); - if ( ! linda_wq->header ) { - rc = -ENOMEM; - goto err_alloc_header; - } - - /* Enable context in hardware */ - memset ( &rcvhdraddr, 0, sizeof ( rcvhdraddr ) ); - BIT_FILL_1 ( &rcvhdraddr, RcvHdrAddr0, - ( virt_to_bus ( linda_wq->header ) >> 2 ) ); - linda_writeq_array8b ( linda, &rcvhdraddr, - QIB_7220_RcvHdrAddr0_offset, ctx ); - memset ( &rcvhdrtailaddr, 0, sizeof ( rcvhdrtailaddr ) ); - BIT_FILL_1 ( &rcvhdrtailaddr, RcvHdrTailAddr0, - ( virt_to_bus ( &linda_wq->header_prod ) >> 2 ) ); - linda_writeq_array8b ( linda, &rcvhdrtailaddr, - QIB_7220_RcvHdrTailAddr0_offset, ctx ); - memset ( &rcvhdrhead, 0, sizeof ( rcvhdrhead ) ); - BIT_FILL_1 ( &rcvhdrhead, counter, 1 ); - linda_writeq_array64k ( linda, &rcvhdrhead, - QIB_7220_RcvHdrHead0_offset, ctx ); - memset ( &rcvegrindexhead, 0, sizeof ( rcvegrindexhead ) ); - BIT_FILL_1 ( &rcvegrindexhead, Value, 1 ); - linda_writeq_array64k ( linda, &rcvegrindexhead, - QIB_7220_RcvEgrIndexHead0_offset, ctx ); - linda_readq ( linda, &rcvctrl, QIB_7220_RcvCtrl_offset ); - BIT_SET ( &rcvctrl, PortEnable[ctx], 1 ); - BIT_SET ( &rcvctrl, IntrAvail[ctx], 1 ); - linda_writeq ( linda, &rcvctrl, QIB_7220_RcvCtrl_offset ); - - DBGC ( linda, "Linda %p QPN %ld CTX %d hdrs [%lx,%lx) prod %lx\n", - linda, qp->qpn, ctx, virt_to_bus ( linda_wq->header ), - ( virt_to_bus ( linda_wq->header ) + LINDA_RECV_HEADERS_SIZE ), - virt_to_bus ( &linda_wq->header_prod ) ); - return 0; - - free_dma ( linda_wq->header, LINDA_RECV_HEADERS_SIZE ); - err_alloc_header: - return rc; -} - -/** - * Destroy receive work queue - * - * @v linda Linda device - * @v qp Queue pair - */ -static void linda_destroy_recv_wq ( struct linda *linda, - struct ib_queue_pair *qp ) { - struct ib_work_queue *wq = &qp->recv; - struct linda_recv_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - struct QIB_7220_RcvCtrl rcvctrl; - unsigned int ctx = linda_qpn_to_ctx ( qp->qpn ); - - /* Disable context in hardware */ - linda_readq ( linda, &rcvctrl, QIB_7220_RcvCtrl_offset ); - BIT_SET ( &rcvctrl, PortEnable[ctx], 0 ); - BIT_SET ( &rcvctrl, IntrAvail[ctx], 0 ); - linda_writeq ( linda, &rcvctrl, QIB_7220_RcvCtrl_offset ); - - /* Make sure the hardware has seen that the context is disabled */ - linda_readq ( linda, &rcvctrl, QIB_7220_RcvCtrl_offset ); - mb(); - - /* Free headers ring */ - free_dma ( linda_wq->header, LINDA_RECV_HEADERS_SIZE ); - - /* Free context */ - linda_free_ctx ( linda, ctx ); -} - -/** - * Initialise receive datapath - * - * @v linda Linda device - * @ret rc Return status code - */ -static int linda_init_recv ( struct linda *linda ) { - struct QIB_7220_RcvCtrl rcvctrl; - struct QIB_7220_scalar rcvegrbase; - struct QIB_7220_scalar rcvhdrentsize; - struct QIB_7220_scalar rcvhdrcnt; - struct QIB_7220_RcvBTHQP rcvbthqp; - unsigned int portcfg; - unsigned long egrbase; - unsigned int eager_array_size_0; - unsigned int eager_array_size_other; - unsigned int ctx; - - /* Select configuration based on number of contexts */ - switch ( LINDA_NUM_CONTEXTS ) { - case 5: - portcfg = LINDA_PORTCFG_5CTX; - eager_array_size_0 = LINDA_EAGER_ARRAY_SIZE_5CTX_0; - eager_array_size_other = LINDA_EAGER_ARRAY_SIZE_5CTX_OTHER; - break; - case 9: - portcfg = LINDA_PORTCFG_9CTX; - eager_array_size_0 = LINDA_EAGER_ARRAY_SIZE_9CTX_0; - eager_array_size_other = LINDA_EAGER_ARRAY_SIZE_9CTX_OTHER; - break; - case 17: - portcfg = LINDA_PORTCFG_17CTX; - eager_array_size_0 = LINDA_EAGER_ARRAY_SIZE_17CTX_0; - eager_array_size_other = LINDA_EAGER_ARRAY_SIZE_17CTX_OTHER; - break; - default: - linker_assert ( 0, invalid_LINDA_NUM_CONTEXTS ); - return -EINVAL; - } - - /* Configure number of contexts */ - memset ( &rcvctrl, 0, sizeof ( rcvctrl ) ); - BIT_FILL_3 ( &rcvctrl, - TailUpd, 1, - PortCfg, portcfg, - RcvQPMapEnable, 1 ); - linda_writeq ( linda, &rcvctrl, QIB_7220_RcvCtrl_offset ); - - /* Configure receive header buffer sizes */ - memset ( &rcvhdrcnt, 0, sizeof ( rcvhdrcnt ) ); - BIT_FILL_1 ( &rcvhdrcnt, Value, LINDA_RECV_HEADER_COUNT ); - linda_writeq ( linda, &rcvhdrcnt, QIB_7220_RcvHdrCnt_offset ); - memset ( &rcvhdrentsize, 0, sizeof ( rcvhdrentsize ) ); - BIT_FILL_1 ( &rcvhdrentsize, Value, ( LINDA_RECV_HEADER_SIZE >> 2 ) ); - linda_writeq ( linda, &rcvhdrentsize, QIB_7220_RcvHdrEntSize_offset ); - - /* Calculate eager array start addresses for each context */ - linda_readq ( linda, &rcvegrbase, QIB_7220_RcvEgrBase_offset ); - egrbase = BIT_GET ( &rcvegrbase, Value ); - linda->recv_wq[0].eager_array = egrbase; - linda->recv_wq[0].eager_entries = eager_array_size_0; - egrbase += ( eager_array_size_0 * sizeof ( struct QIB_7220_RcvEgr ) ); - for ( ctx = 1 ; ctx < LINDA_NUM_CONTEXTS ; ctx++ ) { - linda->recv_wq[ctx].eager_array = egrbase; - linda->recv_wq[ctx].eager_entries = eager_array_size_other; - egrbase += ( eager_array_size_other * - sizeof ( struct QIB_7220_RcvEgr ) ); - } - for ( ctx = 0 ; ctx < LINDA_NUM_CONTEXTS ; ctx++ ) { - DBGC ( linda, "Linda %p CTX %d eager array at %lx (%d " - "entries)\n", linda, ctx, - linda->recv_wq[ctx].eager_array, - linda->recv_wq[ctx].eager_entries ); - } - - /* Set the BTH QP for Infinipath packets to an unused value */ - memset ( &rcvbthqp, 0, sizeof ( rcvbthqp ) ); - BIT_FILL_1 ( &rcvbthqp, RcvBTHQP, LINDA_QP_IDETH ); - linda_writeq ( linda, &rcvbthqp, QIB_7220_RcvBTHQP_offset ); - - return 0; -} - -/** - * Shut down receive datapath - * - * @v linda Linda device - */ -static void linda_fini_recv ( struct linda *linda __unused ) { - /* Nothing to do; all contexts were already disabled when the - * queue pairs were destroyed - */ -} - -/*************************************************************************** - * - * Completion queue operations - * - *************************************************************************** - */ - -/** - * Create completion queue - * - * @v ibdev Infiniband device - * @v cq Completion queue - * @ret rc Return status code - */ -static int linda_create_cq ( struct ib_device *ibdev, - struct ib_completion_queue *cq ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - static int cqn; - - /* The hardware has no concept of completion queues. We - * simply use the association between CQs and WQs (already - * handled by the IB core) to decide which WQs to poll. - * - * We do set a CQN, just to avoid confusing debug messages - * from the IB core. - */ - cq->cqn = ++cqn; - DBGC ( linda, "Linda %p CQN %ld created\n", linda, cq->cqn ); - - return 0; -} - -/** - * Destroy completion queue - * - * @v ibdev Infiniband device - * @v cq Completion queue - */ -static void linda_destroy_cq ( struct ib_device *ibdev, - struct ib_completion_queue *cq ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - - /* Nothing to do */ - DBGC ( linda, "Linda %p CQN %ld destroyed\n", linda, cq->cqn ); -} - -/*************************************************************************** - * - * Queue pair operations - * - *************************************************************************** - */ - -/** - * Create queue pair - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @ret rc Return status code - */ -static int linda_create_qp ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - int ctx; - int rc; - - /* Locate an available context */ - ctx = linda_alloc_ctx ( linda ); - if ( ctx < 0 ) { - rc = ctx; - goto err_alloc_ctx; - } - - /* Set queue pair number based on context index */ - qp->qpn = linda_ctx_to_qpn ( ctx ); - - /* Set work-queue private data pointers */ - ib_wq_set_drvdata ( &qp->send, &linda->send_wq[ctx] ); - ib_wq_set_drvdata ( &qp->recv, &linda->recv_wq[ctx] ); - - /* Create receive work queue */ - if ( ( rc = linda_create_recv_wq ( linda, qp ) ) != 0 ) - goto err_create_recv_wq; - - /* Create send work queue */ - if ( ( rc = linda_create_send_wq ( linda, qp ) ) != 0 ) - goto err_create_send_wq; - - return 0; - - linda_destroy_send_wq ( linda, qp ); - err_create_send_wq: - linda_destroy_recv_wq ( linda, qp ); - err_create_recv_wq: - linda_free_ctx ( linda, ctx ); - err_alloc_ctx: - return rc; -} - -/** - * Modify queue pair - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @ret rc Return status code - */ -static int linda_modify_qp ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - - /* Nothing to do; the hardware doesn't have a notion of queue - * keys - */ - DBGC ( linda, "Linda %p QPN %ld modified\n", linda, qp->qpn ); - return 0; -} - -/** - * Destroy queue pair - * - * @v ibdev Infiniband device - * @v qp Queue pair - */ -static void linda_destroy_qp ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - - linda_destroy_send_wq ( linda, qp ); - linda_destroy_recv_wq ( linda, qp ); -} - -/*************************************************************************** - * - * Work request operations - * - *************************************************************************** - */ - -/** - * Post send work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v av Address vector - * @v iobuf I/O buffer - * @ret rc Return status code - */ -static int linda_post_send ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct ib_address_vector *av, - struct io_buffer *iobuf ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct ib_work_queue *wq = &qp->send; - struct linda_send_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - struct QIB_7220_SendPbc sendpbc; - uint8_t header_buf[IB_MAX_HEADER_SIZE]; - struct io_buffer headers; - unsigned int send_buf; - unsigned long start_offset; - unsigned long offset; - size_t len; - ssize_t frag_len; - uint32_t *data; - - /* Allocate send buffer and calculate offset */ - send_buf = linda_alloc_send_buf ( linda ); - start_offset = offset = linda_send_buffer_offset ( linda, send_buf ); - - /* Store I/O buffer and send buffer index */ - assert ( wq->iobufs[linda_wq->prod] == NULL ); - wq->iobufs[linda_wq->prod] = iobuf; - linda_wq->send_buf[linda_wq->prod] = send_buf; - - /* Construct headers */ - iob_populate ( &headers, header_buf, 0, sizeof ( header_buf ) ); - iob_reserve ( &headers, sizeof ( header_buf ) ); - ib_push ( ibdev, &headers, qp, iob_len ( iobuf ), av ); - - /* Calculate packet length */ - len = ( ( sizeof ( sendpbc ) + iob_len ( &headers ) + - iob_len ( iobuf ) + 3 ) & ~3 ); - - /* Construct send per-buffer control word */ - memset ( &sendpbc, 0, sizeof ( sendpbc ) ); - BIT_FILL_2 ( &sendpbc, - LengthP1_toibc, ( ( len >> 2 ) - 1 ), - VL15, 1 ); - - /* Write SendPbc */ - DBG_DISABLE ( DBGLVL_IO ); - linda_writeq ( linda, &sendpbc, offset ); - offset += sizeof ( sendpbc ); - - /* Write headers */ - for ( data = headers.data, frag_len = iob_len ( &headers ) ; - frag_len > 0 ; data++, offset += 4, frag_len -= 4 ) { - linda_writel ( linda, *data, offset ); - } - - /* Write data */ - for ( data = iobuf->data, frag_len = iob_len ( iobuf ) ; - frag_len > 0 ; data++, offset += 4, frag_len -= 4 ) { - linda_writel ( linda, *data, offset ); - } - DBG_ENABLE ( DBGLVL_IO ); - - assert ( ( start_offset + len ) == offset ); - DBGC2 ( linda, "Linda %p QPN %ld TX %d(%d) posted [%lx,%lx)\n", - linda, qp->qpn, send_buf, linda_wq->prod, - start_offset, offset ); - - /* Increment producer counter */ - linda_wq->prod = ( ( linda_wq->prod + 1 ) & ( wq->num_wqes - 1 ) ); - - return 0; -} - -/** - * Complete send work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v wqe_idx Work queue entry index - */ -static void linda_complete_send ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - unsigned int wqe_idx ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct ib_work_queue *wq = &qp->send; - struct linda_send_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - struct io_buffer *iobuf; - unsigned int send_buf; - - /* Parse completion */ - send_buf = linda_wq->send_buf[wqe_idx]; - DBGC2 ( linda, "Linda %p QPN %ld TX %d(%d) complete\n", - linda, qp->qpn, send_buf, wqe_idx ); - - /* Complete work queue entry */ - iobuf = wq->iobufs[wqe_idx]; - assert ( iobuf != NULL ); - ib_complete_send ( ibdev, qp, iobuf, 0 ); - wq->iobufs[wqe_idx] = NULL; - - /* Free send buffer */ - linda_free_send_buf ( linda, send_buf ); -} - -/** - * Poll send work queue - * - * @v ibdev Infiniband device - * @v qp Queue pair - */ -static void linda_poll_send_wq ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct ib_work_queue *wq = &qp->send; - struct linda_send_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - unsigned int send_buf; - - /* Look for completions */ - while ( wq->fill ) { - - /* Check to see if send buffer has completed */ - send_buf = linda_wq->send_buf[linda_wq->cons]; - if ( linda_send_buf_in_use ( linda, send_buf ) ) - break; - - /* Complete this buffer */ - linda_complete_send ( ibdev, qp, linda_wq->cons ); - - /* Increment consumer counter */ - linda_wq->cons = ( ( linda_wq->cons + 1 ) & - ( wq->num_wqes - 1 ) ); - } -} - -/** - * Post receive work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v iobuf I/O buffer - * @ret rc Return status code - */ -static int linda_post_recv ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct io_buffer *iobuf ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct ib_work_queue *wq = &qp->recv; - struct linda_recv_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - struct QIB_7220_RcvEgr rcvegr; - struct QIB_7220_scalar rcvegrindexhead; - unsigned int ctx = linda_qpn_to_ctx ( qp->qpn ); - physaddr_t addr; - size_t len; - unsigned int wqe_idx; - unsigned int bufsize; - - /* Sanity checks */ - addr = virt_to_bus ( iobuf->data ); - len = iob_tailroom ( iobuf ); - if ( addr & ( LINDA_EAGER_BUFFER_ALIGN - 1 ) ) { - DBGC ( linda, "Linda %p QPN %ld misaligned RX buffer " - "(%08lx)\n", linda, qp->qpn, addr ); - return -EINVAL; - } - if ( len != LINDA_RECV_PAYLOAD_SIZE ) { - DBGC ( linda, "Linda %p QPN %ld wrong RX buffer size (%zd)\n", - linda, qp->qpn, len ); - return -EINVAL; - } - - /* Calculate eager producer index and WQE index */ - wqe_idx = ( linda_wq->eager_prod & ( wq->num_wqes - 1 ) ); - assert ( wq->iobufs[wqe_idx] == NULL ); - - /* Store I/O buffer */ - wq->iobufs[wqe_idx] = iobuf; - - /* Calculate buffer size */ - switch ( LINDA_RECV_PAYLOAD_SIZE ) { - case 2048: bufsize = LINDA_EAGER_BUFFER_2K; break; - case 4096: bufsize = LINDA_EAGER_BUFFER_4K; break; - case 8192: bufsize = LINDA_EAGER_BUFFER_8K; break; - case 16384: bufsize = LINDA_EAGER_BUFFER_16K; break; - case 32768: bufsize = LINDA_EAGER_BUFFER_32K; break; - case 65536: bufsize = LINDA_EAGER_BUFFER_64K; break; - default: linker_assert ( 0, invalid_rx_payload_size ); - bufsize = LINDA_EAGER_BUFFER_NONE; - } - - /* Post eager buffer */ - memset ( &rcvegr, 0, sizeof ( rcvegr ) ); - BIT_FILL_2 ( &rcvegr, - Addr, ( addr >> 11 ), - BufSize, bufsize ); - linda_writeq_array8b ( linda, &rcvegr, - linda_wq->eager_array, linda_wq->eager_prod ); - DBGC2 ( linda, "Linda %p QPN %ld RX egr %d(%d) posted [%lx,%lx)\n", - linda, qp->qpn, linda_wq->eager_prod, wqe_idx, - addr, ( addr + len ) ); - - /* Increment producer index */ - linda_wq->eager_prod = ( ( linda_wq->eager_prod + 1 ) & - ( linda_wq->eager_entries - 1 ) ); - - /* Update head index */ - memset ( &rcvegrindexhead, 0, sizeof ( rcvegrindexhead ) ); - BIT_FILL_1 ( &rcvegrindexhead, - Value, ( ( linda_wq->eager_prod + 1 ) & - ( linda_wq->eager_entries - 1 ) ) ); - linda_writeq_array64k ( linda, &rcvegrindexhead, - QIB_7220_RcvEgrIndexHead0_offset, ctx ); - - return 0; -} - -/** - * Complete receive work queue entry - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v header_offs Header offset - */ -static void linda_complete_recv ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - unsigned int header_offs ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct ib_work_queue *wq = &qp->recv; - struct linda_recv_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - struct QIB_7220_RcvHdrFlags *rcvhdrflags; - struct QIB_7220_RcvEgr rcvegr; - struct io_buffer headers; - struct io_buffer *iobuf; - struct ib_queue_pair *intended_qp; - struct ib_address_vector av; - unsigned int rcvtype; - unsigned int pktlen; - unsigned int egrindex; - unsigned int useegrbfr; - unsigned int iberr, mkerr, tiderr, khdrerr, mtuerr; - unsigned int lenerr, parityerr, vcrcerr, icrcerr; - unsigned int err; - unsigned int hdrqoffset; - unsigned int header_len; - unsigned int padded_payload_len; - unsigned int wqe_idx; - size_t payload_len; - int qp0; - int rc; - - /* RcvHdrFlags are at the end of the header entry */ - rcvhdrflags = ( linda_wq->header + header_offs + - LINDA_RECV_HEADER_SIZE - sizeof ( *rcvhdrflags ) ); - rcvtype = BIT_GET ( rcvhdrflags, RcvType ); - pktlen = ( BIT_GET ( rcvhdrflags, PktLen ) << 2 ); - egrindex = BIT_GET ( rcvhdrflags, EgrIndex ); - useegrbfr = BIT_GET ( rcvhdrflags, UseEgrBfr ); - hdrqoffset = ( BIT_GET ( rcvhdrflags, HdrqOffset ) << 2 ); - iberr = BIT_GET ( rcvhdrflags, IBErr ); - mkerr = BIT_GET ( rcvhdrflags, MKErr ); - tiderr = BIT_GET ( rcvhdrflags, TIDErr ); - khdrerr = BIT_GET ( rcvhdrflags, KHdrErr ); - mtuerr = BIT_GET ( rcvhdrflags, MTUErr ); - lenerr = BIT_GET ( rcvhdrflags, LenErr ); - parityerr = BIT_GET ( rcvhdrflags, ParityErr ); - vcrcerr = BIT_GET ( rcvhdrflags, VCRCErr ); - icrcerr = BIT_GET ( rcvhdrflags, ICRCErr ); - header_len = ( LINDA_RECV_HEADER_SIZE - hdrqoffset - - sizeof ( *rcvhdrflags ) ); - padded_payload_len = ( pktlen - header_len - 4 /* ICRC */ ); - err = ( iberr | mkerr | tiderr | khdrerr | mtuerr | - lenerr | parityerr | vcrcerr | icrcerr ); - /* IB header is placed immediately before RcvHdrFlags */ - iob_populate ( &headers, ( ( ( void * ) rcvhdrflags ) - header_len ), - header_len, header_len ); - - /* Dump diagnostic information */ - if ( err || ( ! useegrbfr ) ) { - DBGC ( linda, "Linda %p QPN %ld RX egr %d%s hdr %d type %d " - "len %d(%d+%d+4)%s%s%s%s%s%s%s%s%s%s%s\n", linda, - qp->qpn, egrindex, ( useegrbfr ? "" : "(unused)" ), - ( header_offs / LINDA_RECV_HEADER_SIZE ), rcvtype, - pktlen, header_len, padded_payload_len, - ( err ? " [Err" : "" ), ( iberr ? " IB" : "" ), - ( mkerr ? " MK" : "" ), ( tiderr ? " TID" : "" ), - ( khdrerr ? " KHdr" : "" ), ( mtuerr ? " MTU" : "" ), - ( lenerr ? " Len" : "" ), ( parityerr ? " Parity" : ""), - ( vcrcerr ? " VCRC" : "" ), ( icrcerr ? " ICRC" : "" ), - ( err ? "]" : "" ) ); - } else { - DBGC2 ( linda, "Linda %p QPN %ld RX egr %d hdr %d type %d " - "len %d(%d+%d+4)\n", linda, qp->qpn, egrindex, - ( header_offs / LINDA_RECV_HEADER_SIZE ), rcvtype, - pktlen, header_len, padded_payload_len ); - } - DBGCP_HDA ( linda, hdrqoffset, headers.data, - ( header_len + sizeof ( *rcvhdrflags ) ) ); - - /* Parse header to generate address vector */ - qp0 = ( qp->qpn == 0 ); - intended_qp = NULL; - if ( ( rc = ib_pull ( ibdev, &headers, ( qp0 ? &intended_qp : NULL ), - &payload_len, &av ) ) != 0 ) { - DBGC ( linda, "Linda %p could not parse headers: %s\n", - linda, strerror ( rc ) ); - err = 1; - } - if ( ! intended_qp ) - intended_qp = qp; - - /* Complete this buffer and any skipped buffers. Note that - * when the hardware runs out of buffers, it will repeatedly - * report the same buffer (the tail) as a TID error, and that - * it also has a habit of sometimes skipping over several - * buffers at once. - */ - while ( 1 ) { - - /* If we have caught up to the producer counter, stop. - * This will happen when the hardware first runs out - * of buffers and starts reporting TID errors against - * the eager buffer it wants to use next. - */ - if ( linda_wq->eager_cons == linda_wq->eager_prod ) - break; - - /* If we have caught up to where we should be after - * completing this egrindex, stop. We phrase the test - * this way to avoid completing the entire ring when - * we receive the same egrindex twice in a row. - */ - if ( ( linda_wq->eager_cons == - ( ( egrindex + 1 ) & ( linda_wq->eager_entries - 1 ) ))) - break; - - /* Identify work queue entry and corresponding I/O - * buffer. - */ - wqe_idx = ( linda_wq->eager_cons & ( wq->num_wqes - 1 ) ); - iobuf = wq->iobufs[wqe_idx]; - assert ( iobuf != NULL ); - wq->iobufs[wqe_idx] = NULL; - - /* Complete the eager buffer */ - if ( linda_wq->eager_cons == egrindex ) { - /* Completing the eager buffer described in - * this header entry. - */ - iob_put ( iobuf, payload_len ); - rc = ( err ? -EIO : ( useegrbfr ? 0 : -ECANCELED ) ); - /* Redirect to target QP if necessary */ - if ( qp != intended_qp ) { - DBGC ( linda, "Linda %p redirecting QPN %ld " - "=> %ld\n", - linda, qp->qpn, intended_qp->qpn ); - /* Compensate for incorrect fill levels */ - qp->recv.fill--; - intended_qp->recv.fill++; - } - ib_complete_recv ( ibdev, intended_qp, &av, iobuf, rc); - } else { - /* Completing on a skipped-over eager buffer */ - ib_complete_recv ( ibdev, qp, &av, iobuf, -ECANCELED ); - } - - /* Clear eager buffer */ - memset ( &rcvegr, 0, sizeof ( rcvegr ) ); - linda_writeq_array8b ( linda, &rcvegr, linda_wq->eager_array, - linda_wq->eager_cons ); - - /* Increment consumer index */ - linda_wq->eager_cons = ( ( linda_wq->eager_cons + 1 ) & - ( linda_wq->eager_entries - 1 ) ); - } -} - -/** - * Poll receive work queue - * - * @v ibdev Infiniband device - * @v qp Queue pair - */ -static void linda_poll_recv_wq ( struct ib_device *ibdev, - struct ib_queue_pair *qp ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct ib_work_queue *wq = &qp->recv; - struct linda_recv_work_queue *linda_wq = ib_wq_get_drvdata ( wq ); - struct QIB_7220_RcvHdrHead0 rcvhdrhead; - unsigned int ctx = linda_qpn_to_ctx ( qp->qpn ); - unsigned int header_prod; - - /* Check for received packets */ - header_prod = ( BIT_GET ( &linda_wq->header_prod, Value ) << 2 ); - if ( header_prod == linda_wq->header_cons ) - return; - - /* Process all received packets */ - while ( linda_wq->header_cons != header_prod ) { - - /* Complete the receive */ - linda_complete_recv ( ibdev, qp, linda_wq->header_cons ); - - /* Increment the consumer offset */ - linda_wq->header_cons += LINDA_RECV_HEADER_SIZE; - linda_wq->header_cons %= LINDA_RECV_HEADERS_SIZE; - } - - /* Update consumer offset */ - memset ( &rcvhdrhead, 0, sizeof ( rcvhdrhead ) ); - BIT_FILL_2 ( &rcvhdrhead, - RcvHeadPointer, ( linda_wq->header_cons >> 2 ), - counter, 1 ); - linda_writeq_array64k ( linda, &rcvhdrhead, - QIB_7220_RcvHdrHead0_offset, ctx ); -} - -/** - * Poll completion queue - * - * @v ibdev Infiniband device - * @v cq Completion queue - */ -static void linda_poll_cq ( struct ib_device *ibdev, - struct ib_completion_queue *cq ) { - struct ib_work_queue *wq; - - /* Poll associated send and receive queues */ - list_for_each_entry ( wq, &cq->work_queues, list ) { - if ( wq->is_send ) { - linda_poll_send_wq ( ibdev, wq->qp ); - } else { - linda_poll_recv_wq ( ibdev, wq->qp ); - } - } -} - -/*************************************************************************** - * - * Event queues - * - *************************************************************************** - */ - -/** - * Poll event queue - * - * @v ibdev Infiniband device - */ -static void linda_poll_eq ( struct ib_device *ibdev ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct QIB_7220_ErrStatus errstatus; - struct QIB_7220_ErrClear errclear; - - /* Check for link status changes */ - DBG_DISABLE ( DBGLVL_IO ); - linda_readq ( linda, &errstatus, QIB_7220_ErrStatus_offset ); - DBG_ENABLE ( DBGLVL_IO ); - if ( BIT_GET ( &errstatus, IBStatusChanged ) ) { - linda_link_state_changed ( ibdev ); - memset ( &errclear, 0, sizeof ( errclear ) ); - BIT_FILL_1 ( &errclear, IBStatusChangedClear, 1 ); - linda_writeq ( linda, &errclear, QIB_7220_ErrClear_offset ); - } -} - -/*************************************************************************** - * - * Infiniband link-layer operations - * - *************************************************************************** - */ - -/** - * Initialise Infiniband link - * - * @v ibdev Infiniband device - * @ret rc Return status code - */ -static int linda_open ( struct ib_device *ibdev ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct QIB_7220_Control control; - - /* Disable link */ - linda_readq ( linda, &control, QIB_7220_Control_offset ); - BIT_SET ( &control, LinkEn, 1 ); - linda_writeq ( linda, &control, QIB_7220_Control_offset ); - return 0; -} - -/** - * Close Infiniband link - * - * @v ibdev Infiniband device - */ -static void linda_close ( struct ib_device *ibdev ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - struct QIB_7220_Control control; - - /* Disable link */ - linda_readq ( linda, &control, QIB_7220_Control_offset ); - BIT_SET ( &control, LinkEn, 0 ); - linda_writeq ( linda, &control, QIB_7220_Control_offset ); -} - -/*************************************************************************** - * - * Multicast group operations - * - *************************************************************************** - */ - -/** - * Attach to multicast group - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v gid Multicast GID - * @ret rc Return status code - */ -static int linda_mcast_attach ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct ib_gid *gid ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - - ( void ) linda; - ( void ) qp; - ( void ) gid; - return 0; -} - -/** - * Detach from multicast group - * - * @v ibdev Infiniband device - * @v qp Queue pair - * @v gid Multicast GID - */ -static void linda_mcast_detach ( struct ib_device *ibdev, - struct ib_queue_pair *qp, - struct ib_gid *gid ) { - struct linda *linda = ib_get_drvdata ( ibdev ); - - ( void ) linda; - ( void ) qp; - ( void ) gid; -} - -/** Linda Infiniband operations */ -static struct ib_device_operations linda_ib_operations = { - .create_cq = linda_create_cq, - .destroy_cq = linda_destroy_cq, - .create_qp = linda_create_qp, - .modify_qp = linda_modify_qp, - .destroy_qp = linda_destroy_qp, - .post_send = linda_post_send, - .post_recv = linda_post_recv, - .poll_cq = linda_poll_cq, - .poll_eq = linda_poll_eq, - .open = linda_open, - .close = linda_close, - .mcast_attach = linda_mcast_attach, - .mcast_detach = linda_mcast_detach, - .set_port_info = linda_set_port_info, - .set_pkey_table = linda_set_pkey_table, -}; - -/*************************************************************************** - * - * I2C bus operations - * - *************************************************************************** - */ - -/** Linda I2C bit to GPIO mappings */ -static unsigned int linda_i2c_bits[] = { - [I2C_BIT_SCL] = ( 1 << LINDA_GPIO_SCL ), - [I2C_BIT_SDA] = ( 1 << LINDA_GPIO_SDA ), -}; - -/** - * Read Linda I2C line status - * - * @v basher Bit-bashing interface - * @v bit_id Bit number - * @ret zero Input is a logic 0 - * @ret non-zero Input is a logic 1 - */ -static int linda_i2c_read_bit ( struct bit_basher *basher, - unsigned int bit_id ) { - struct linda *linda = - container_of ( basher, struct linda, i2c.basher ); - struct QIB_7220_EXTStatus extstatus; - unsigned int status; - - DBG_DISABLE ( DBGLVL_IO ); - - linda_readq ( linda, &extstatus, QIB_7220_EXTStatus_offset ); - status = ( BIT_GET ( &extstatus, GPIOIn ) & linda_i2c_bits[bit_id] ); - - DBG_ENABLE ( DBGLVL_IO ); - - return status; -} - -/** - * Write Linda I2C line status - * - * @v basher Bit-bashing interface - * @v bit_id Bit number - * @v data Value to write - */ -static void linda_i2c_write_bit ( struct bit_basher *basher, - unsigned int bit_id, unsigned long data ) { - struct linda *linda = - container_of ( basher, struct linda, i2c.basher ); - struct QIB_7220_EXTCtrl extctrl; - struct QIB_7220_GPIO gpioout; - unsigned int bit = linda_i2c_bits[bit_id]; - unsigned int outputs = 0; - unsigned int output_enables = 0; - - DBG_DISABLE ( DBGLVL_IO ); - - /* Read current GPIO mask and outputs */ - linda_readq ( linda, &extctrl, QIB_7220_EXTCtrl_offset ); - linda_readq ( linda, &gpioout, QIB_7220_GPIOOut_offset ); - - /* Update outputs and output enables. I2C lines are tied - * high, so we always set the output to 0 and use the output - * enable to control the line. - */ - output_enables = BIT_GET ( &extctrl, GPIOOe ); - output_enables = ( ( output_enables & ~bit ) | ( ~data & bit ) ); - outputs = BIT_GET ( &gpioout, GPIO ); - outputs = ( outputs & ~bit ); - BIT_SET ( &extctrl, GPIOOe, output_enables ); - BIT_SET ( &gpioout, GPIO, outputs ); - - /* Write the output enable first; that way we avoid logic - * hazards. - */ - linda_writeq ( linda, &extctrl, QIB_7220_EXTCtrl_offset ); - linda_writeq ( linda, &gpioout, QIB_7220_GPIOOut_offset ); - mb(); - - DBG_ENABLE ( DBGLVL_IO ); -} - -/** Linda I2C bit-bashing interface operations */ -static struct bit_basher_operations linda_i2c_basher_ops = { - .read = linda_i2c_read_bit, - .write = linda_i2c_write_bit, -}; - -/** - * Initialise Linda I2C subsystem - * - * @v linda Linda device - * @ret rc Return status code - */ -static int linda_init_i2c ( struct linda *linda ) { - static int try_eeprom_address[] = { 0x51, 0x50 }; - unsigned int i; - int rc; - - /* Initialise bus */ - if ( ( rc = init_i2c_bit_basher ( &linda->i2c, - &linda_i2c_basher_ops ) ) != 0 ) { - DBGC ( linda, "Linda %p could not initialise I2C bus: %s\n", - linda, strerror ( rc ) ); - return rc; - } - - /* Probe for devices */ - for ( i = 0 ; i < ( sizeof ( try_eeprom_address ) / - sizeof ( try_eeprom_address[0] ) ) ; i++ ) { - init_i2c_eeprom ( &linda->eeprom, try_eeprom_address[i] ); - if ( ( rc = i2c_check_presence ( &linda->i2c.i2c, - &linda->eeprom ) ) == 0 ) { - DBGC2 ( linda, "Linda %p found EEPROM at %02x\n", - linda, try_eeprom_address[i] ); - return 0; - } - } - - DBGC ( linda, "Linda %p could not find EEPROM\n", linda ); - return -ENODEV; -} - -/** - * Read EEPROM parameters - * - * @v linda Linda device - * @v guid GUID to fill in - * @ret rc Return status code - */ -static int linda_read_eeprom ( struct linda *linda, - struct ib_gid_half *guid ) { - struct i2c_interface *i2c = &linda->i2c.i2c; - int rc; - - /* Read GUID */ - if ( ( rc = i2c->read ( i2c, &linda->eeprom, LINDA_EEPROM_GUID_OFFSET, - guid->u.bytes, sizeof ( *guid ) ) ) != 0 ) { - DBGC ( linda, "Linda %p could not read GUID: %s\n", - linda, strerror ( rc ) ); - return rc; - } - DBGC2 ( linda, "Linda %p has GUID %02x:%02x:%02x:%02x:%02x:%02x:" - "%02x:%02x\n", linda, guid->u.bytes[0], guid->u.bytes[1], - guid->u.bytes[2], guid->u.bytes[3], guid->u.bytes[4], - guid->u.bytes[5], guid->u.bytes[6], guid->u.bytes[7] ); - - /* Read serial number (debug only) */ - if ( DBG_LOG ) { - uint8_t serial[LINDA_EEPROM_SERIAL_SIZE + 1]; - - serial[ sizeof ( serial ) - 1 ] = '\0'; - if ( ( rc = i2c->read ( i2c, &linda->eeprom, - LINDA_EEPROM_SERIAL_OFFSET, serial, - ( sizeof ( serial ) - 1 ) ) ) != 0 ) { - DBGC ( linda, "Linda %p could not read serial: %s\n", - linda, strerror ( rc ) ); - return rc; - } - DBGC2 ( linda, "Linda %p has serial number \"%s\"\n", - linda, serial ); - } - - return 0; -} - -/*************************************************************************** - * - * External parallel bus access - * - *************************************************************************** - */ - -/** - * Request ownership of the IB external parallel bus - * - * @v linda Linda device - * @ret rc Return status code - */ -static int linda_ib_epb_request ( struct linda *linda ) { - struct QIB_7220_ibsd_epb_access_ctrl access; - unsigned int i; - - /* Request ownership */ - memset ( &access, 0, sizeof ( access ) ); - BIT_FILL_1 ( &access, sw_ib_epb_req, 1 ); - linda_writeq ( linda, &access, QIB_7220_ibsd_epb_access_ctrl_offset ); - - /* Wait for ownership to be granted */ - for ( i = 0 ; i < LINDA_EPB_REQUEST_MAX_WAIT_US ; i++ ) { - linda_readq ( linda, &access, - QIB_7220_ibsd_epb_access_ctrl_offset ); - if ( BIT_GET ( &access, sw_ib_epb_req_granted ) ) - return 0; - udelay ( 1 ); - } - - DBGC ( linda, "Linda %p timed out waiting for IB EPB request\n", - linda ); - return -ETIMEDOUT; -} - -/** - * Wait for IB external parallel bus transaction to complete - * - * @v linda Linda device - * @v xact Buffer to hold transaction result - * @ret rc Return status code - */ -static int linda_ib_epb_wait ( struct linda *linda, - struct QIB_7220_ibsd_epb_transaction_reg *xact ) { - unsigned int i; - - /* Discard first read to allow for signals crossing clock domains */ - linda_readq ( linda, xact, QIB_7220_ibsd_epb_transaction_reg_offset ); - - for ( i = 0 ; i < LINDA_EPB_XACT_MAX_WAIT_US ; i++ ) { - linda_readq ( linda, xact, - QIB_7220_ibsd_epb_transaction_reg_offset ); - if ( BIT_GET ( xact, ib_epb_rdy ) ) { - if ( BIT_GET ( xact, ib_epb_req_error ) ) { - DBGC ( linda, "Linda %p EPB transaction " - "failed\n", linda ); - return -EIO; - } else { - return 0; - } - } - udelay ( 1 ); - } - - DBGC ( linda, "Linda %p timed out waiting for IB EPB transaction\n", - linda ); - return -ETIMEDOUT; -} - -/** - * Release ownership of the IB external parallel bus - * - * @v linda Linda device - */ -static void linda_ib_epb_release ( struct linda *linda ) { - struct QIB_7220_ibsd_epb_access_ctrl access; - - memset ( &access, 0, sizeof ( access ) ); - BIT_FILL_1 ( &access, sw_ib_epb_req, 0 ); - linda_writeq ( linda, &access, QIB_7220_ibsd_epb_access_ctrl_offset ); -} - -/** - * Read data via IB external parallel bus - * - * @v linda Linda device - * @v location EPB location - * @ret data Data read, or negative error - * - * You must have already acquired ownership of the IB external - * parallel bus. - */ -static int linda_ib_epb_read ( struct linda *linda, unsigned int location ) { - struct QIB_7220_ibsd_epb_transaction_reg xact; - unsigned int data; - int rc; - - /* Ensure no transaction is currently in progress */ - if ( ( rc = linda_ib_epb_wait ( linda, &xact ) ) != 0 ) - return rc; - - /* Process data */ - memset ( &xact, 0, sizeof ( xact ) ); - BIT_FILL_3 ( &xact, - ib_epb_address, LINDA_EPB_LOC_ADDRESS ( location ), - ib_epb_read_write, LINDA_EPB_READ, - ib_epb_cs, LINDA_EPB_LOC_CS ( location ) ); - linda_writeq ( linda, &xact, - QIB_7220_ibsd_epb_transaction_reg_offset ); - - /* Wait for transaction to complete */ - if ( ( rc = linda_ib_epb_wait ( linda, &xact ) ) != 0 ) - return rc; - - data = BIT_GET ( &xact, ib_epb_data ); - return data; -} - -/** - * Write data via IB external parallel bus - * - * @v linda Linda device - * @v location EPB location - * @v data Data to write - * @ret rc Return status code - * - * You must have already acquired ownership of the IB external - * parallel bus. - */ -static int linda_ib_epb_write ( struct linda *linda, unsigned int location, - unsigned int data ) { - struct QIB_7220_ibsd_epb_transaction_reg xact; - int rc; - - /* Ensure no transaction is currently in progress */ - if ( ( rc = linda_ib_epb_wait ( linda, &xact ) ) != 0 ) - return rc; - - /* Process data */ - memset ( &xact, 0, sizeof ( xact ) ); - BIT_FILL_4 ( &xact, - ib_epb_data, data, - ib_epb_address, LINDA_EPB_LOC_ADDRESS ( location ), - ib_epb_read_write, LINDA_EPB_WRITE, - ib_epb_cs, LINDA_EPB_LOC_CS ( location ) ); - linda_writeq ( linda, &xact, - QIB_7220_ibsd_epb_transaction_reg_offset ); - - /* Wait for transaction to complete */ - if ( ( rc = linda_ib_epb_wait ( linda, &xact ) ) != 0 ) - return rc; - - return 0; -} - -/** - * Read/modify/write EPB register - * - * @v linda Linda device - * @v cs Chip select - * @v channel Channel - * @v element Element - * @v reg Register - * @v value Value to set - * @v mask Mask to apply to old value - * @ret rc Return status code - */ -static int linda_ib_epb_mod_reg ( struct linda *linda, unsigned int cs, - unsigned int channel, unsigned int element, - unsigned int reg, unsigned int value, - unsigned int mask ) { - unsigned int location; - int old_value; - int rc; - - DBG_DISABLE ( DBGLVL_IO ); - - /* Sanity check */ - assert ( ( value & mask ) == value ); - - /* Acquire bus ownership */ - if ( ( rc = linda_ib_epb_request ( linda ) ) != 0 ) - goto out; - - /* Read existing value, if necessary */ - location = LINDA_EPB_LOC ( cs, channel, element, reg ); - if ( (~mask) & 0xff ) { - old_value = linda_ib_epb_read ( linda, location ); - if ( old_value < 0 ) { - rc = old_value; - goto out_release; - } - } else { - old_value = 0; - } - - /* Update value */ - value = ( ( old_value & ~mask ) | value ); - DBGCP ( linda, "Linda %p CS %d EPB(%d,%d,%#02x) %#02x => %#02x\n", - linda, cs, channel, element, reg, old_value, value ); - if ( ( rc = linda_ib_epb_write ( linda, location, value ) ) != 0 ) - goto out_release; - - out_release: - /* Release bus */ - linda_ib_epb_release ( linda ); - out: - DBG_ENABLE ( DBGLVL_IO ); - return rc; -} - -/** - * Transfer data to/from microcontroller RAM - * - * @v linda Linda device - * @v address Starting address - * @v write Data to write, or NULL - * @v read Data to read, or NULL - * @v len Length of data - * @ret rc Return status code - */ -static int linda_ib_epb_ram_xfer ( struct linda *linda, unsigned int address, - const void *write, void *read, - size_t len ) { - unsigned int control; - unsigned int address_hi; - unsigned int address_lo; - int data; - int rc; - - DBG_DISABLE ( DBGLVL_IO ); - - assert ( ! ( write && read ) ); - assert ( ( address % LINDA_EPB_UC_CHUNK_SIZE ) == 0 ); - assert ( ( len % LINDA_EPB_UC_CHUNK_SIZE ) == 0 ); - - /* Acquire bus ownership */ - if ( ( rc = linda_ib_epb_request ( linda ) ) != 0 ) - goto out; - - /* Process data */ - while ( len ) { - - /* Reset the address for each new chunk */ - if ( ( address % LINDA_EPB_UC_CHUNK_SIZE ) == 0 ) { - - /* Write the control register */ - control = ( read ? LINDA_EPB_UC_CTL_READ : - LINDA_EPB_UC_CTL_WRITE ); - if ( ( rc = linda_ib_epb_write ( linda, - LINDA_EPB_UC_CTL, - control ) ) != 0 ) - break; - - /* Write the address registers */ - address_hi = ( address >> 8 ); - if ( ( rc = linda_ib_epb_write ( linda, - LINDA_EPB_UC_ADDR_HI, - address_hi ) ) != 0 ) - break; - address_lo = ( address & 0xff ); - if ( ( rc = linda_ib_epb_write ( linda, - LINDA_EPB_UC_ADDR_LO, - address_lo ) ) != 0 ) - break; - } - - /* Read or write the data */ - if ( read ) { - data = linda_ib_epb_read ( linda, LINDA_EPB_UC_DATA ); - if ( data < 0 ) { - rc = data; - break; - } - *( ( uint8_t * ) read++ ) = data; - } else { - data = *( ( uint8_t * ) write++ ); - if ( ( rc = linda_ib_epb_write ( linda, - LINDA_EPB_UC_DATA, - data ) ) != 0 ) - break; - } - address++; - len--; - - /* Reset the control byte after each chunk */ - if ( ( address % LINDA_EPB_UC_CHUNK_SIZE ) == 0 ) { - if ( ( rc = linda_ib_epb_write ( linda, - LINDA_EPB_UC_CTL, - 0 ) ) != 0 ) - break; - } - } - - /* Release bus */ - linda_ib_epb_release ( linda ); - - out: - DBG_ENABLE ( DBGLVL_IO ); - return rc; -} - -/*************************************************************************** - * - * Infiniband SerDes initialisation - * - *************************************************************************** - */ - -/** A Linda SerDes parameter */ -struct linda_serdes_param { - /** EPB address as constructed by LINDA_EPB_ADDRESS() */ - uint16_t address; - /** Value to set */ - uint8_t value; - /** Mask to apply to old value */ - uint8_t mask; -} __packed; - -/** Magic "all channels" channel number */ -#define LINDA_EPB_ALL_CHANNELS 31 - -/** End of SerDes parameter list marker */ -#define LINDA_SERDES_PARAM_END { 0, 0, 0 } - -/** - * Program IB SerDes register(s) - * - * @v linda Linda device - * @v param SerDes parameter - * @ret rc Return status code - */ -static int linda_set_serdes_param ( struct linda *linda, - struct linda_serdes_param *param ) { - unsigned int channel; - unsigned int channel_start; - unsigned int channel_end; - unsigned int element; - unsigned int reg; - int rc; - - /* Break down the EPB address and determine channels */ - channel = LINDA_EPB_ADDRESS_CHANNEL ( param->address ); - element = LINDA_EPB_ADDRESS_ELEMENT ( param->address ); - reg = LINDA_EPB_ADDRESS_REG ( param->address ); - if ( channel == LINDA_EPB_ALL_CHANNELS ) { - channel_start = 0; - channel_end = 3; - } else { - channel_start = channel_end = channel; - } - - /* Modify register for each specified channel */ - for ( channel = channel_start ; channel <= channel_end ; channel++ ) { - if ( ( rc = linda_ib_epb_mod_reg ( linda, LINDA_EPB_CS_SERDES, - channel, element, reg, - param->value, - param->mask ) ) != 0 ) - return rc; - } - - return 0; -} - -/** - * Program IB SerDes registers - * - * @v linda Linda device - * @v param SerDes parameters - * @v count Number of parameters - * @ret rc Return status code - */ -static int linda_set_serdes_params ( struct linda *linda, - struct linda_serdes_param *params ) { - int rc; - - for ( ; params->mask != 0 ; params++ ){ - if ( ( rc = linda_set_serdes_param ( linda, - params ) ) != 0 ) - return rc; - } - - return 0; -} - -#define LINDA_DDS_VAL( amp_d, main_d, ipst_d, ipre_d, \ - amp_s, main_s, ipst_s, ipre_s ) \ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 9, 0x00 ), \ - ( ( ( amp_d & 0x1f ) << 1 ) | 1 ), 0xff }, \ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 9, 0x01 ), \ - ( ( ( amp_s & 0x1f ) << 1 ) | 1 ), 0xff }, \ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 9, 0x09 ), \ - ( ( main_d << 3 ) | 4 | ( ipre_d >> 2 ) ), 0xff }, \ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 9, 0x0a ), \ - ( ( main_s << 3 ) | 4 | ( ipre_s >> 2 ) ), 0xff }, \ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 9, 0x06 ), \ - ( ( ( ipst_d & 0xf ) << 1 ) | \ - ( ( ipre_d & 3 ) << 6 ) | 0x21 ), 0xff }, \ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 9, 0x07 ), \ - ( ( ( ipst_s & 0xf ) << 1 ) | \ - ( ( ipre_s & 3 ) << 6) | 0x21 ), 0xff } - -/** - * Linda SerDes default parameters - * - * These magic start-of-day values are taken from the Linux driver. - */ -static struct linda_serdes_param linda_serdes_defaults1[] = { - /* RXHSCTRL0 */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 6, 0x00 ), 0xd4, 0xff }, - /* VCDL_DAC2 */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 6, 0x05 ), 0x2d, 0xff }, - /* VCDL_CTRL2 */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 6, 0x08 ), 0x03, 0x0f }, - /* START_EQ1 */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x27 ), 0x10, 0xff }, - /* START_EQ2 */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x28 ), 0x30, 0xff }, - /* BACTRL */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 6, 0x0e ), 0x40, 0xff }, - /* LDOUTCTRL1 */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x06 ), 0x04, 0xff }, - /* RXHSSTATUS */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 6, 0x0f ), 0x04, 0xff }, - /* End of this block */ - LINDA_SERDES_PARAM_END -}; -static struct linda_serdes_param linda_serdes_defaults2[] = { - /* LDOUTCTRL1 */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x06 ), 0x00, 0xff }, - /* DDS values */ - LINDA_DDS_VAL ( 31, 19, 12, 0, 29, 22, 9, 0 ), - /* Set Rcv Eq. to Preset node */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x27 ), 0x10, 0xff }, - /* DFELTHFDR */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x08 ), 0x00, 0xff }, - /* DFELTHHDR */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x21 ), 0x00, 0xff }, - /* TLTHFDR */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x09 ), 0x02, 0xff }, - /* TLTHHDR */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x23 ), 0x02, 0xff }, - /* ZFR */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x1b ), 0x0c, 0xff }, - /* ZCNT) */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x1c ), 0x0c, 0xff }, - /* GFR */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x1e ), 0x10, 0xff }, - /* GHR */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x1f ), 0x10, 0xff }, - /* VCDL_CTRL0 toggle */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 6, 0x06 ), 0x20, 0xff }, - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 6, 0x06 ), 0x00, 0xff }, - /* CMUCTRL5 */ - { LINDA_EPB_ADDRESS ( 7, 0, 0x15 ), 0x80, 0xff }, - /* End of this block */ - LINDA_SERDES_PARAM_END -}; -static struct linda_serdes_param linda_serdes_defaults3[] = { - /* START_EQ1 */ - { LINDA_EPB_ADDRESS ( LINDA_EPB_ALL_CHANNELS, 7, 0x27 ), 0x00, 0x38 }, - /* End of this block */ - LINDA_SERDES_PARAM_END -}; - -/** - * Program the microcontroller RAM - * - * @v linda Linda device - * @ret rc Return status code - */ -static int linda_program_uc_ram ( struct linda *linda ) { - int rc; - - if ( ( rc = linda_ib_epb_ram_xfer ( linda, 0, linda_ib_fw, NULL, - sizeof ( linda_ib_fw ) ) ) != 0 ){ - DBGC ( linda, "Linda %p could not load IB firmware: %s\n", - linda, strerror ( rc ) ); - return rc; - } - - return 0; -} - -/** - * Verify the microcontroller RAM - * - * @v linda Linda device - * @ret rc Return status code - */ -static int linda_verify_uc_ram ( struct linda *linda ) { - uint8_t verify[LINDA_EPB_UC_CHUNK_SIZE]; - unsigned int offset; - int rc; - - for ( offset = 0 ; offset < sizeof ( linda_ib_fw ); - offset += sizeof ( verify ) ) { - if ( ( rc = linda_ib_epb_ram_xfer ( linda, offset, - NULL, verify, - sizeof (verify) )) != 0 ){ - DBGC ( linda, "Linda %p could not read back IB " - "firmware: %s\n", linda, strerror ( rc ) ); - return rc; - } - if ( memcmp ( ( linda_ib_fw + offset ), verify, - sizeof ( verify ) ) != 0 ) { - DBGC ( linda, "Linda %p firmware verification failed " - "at offset %#x\n", linda, offset ); - DBGC_HDA ( linda, offset, ( linda_ib_fw + offset ), - sizeof ( verify ) ); - DBGC_HDA ( linda, offset, verify, sizeof ( verify ) ); - return -EIO; - } - } - - DBGC2 ( linda, "Linda %p firmware verified ok\n", linda ); - return 0; -} - -/** - * Use the microcontroller to trim the IB link - * - * @v linda Linda device - * @ret rc Return status code - */ -static int linda_trim_ib ( struct linda *linda ) { - struct QIB_7220_IBSerDesCtrl ctrl; - struct QIB_7220_IntStatus intstatus; - unsigned int i; - int rc; - - /* Bring the microcontroller out of reset */ - linda_readq ( linda, &ctrl, QIB_7220_IBSerDesCtrl_offset ); - BIT_SET ( &ctrl, ResetIB_uC_Core, 0 ); - linda_writeq ( linda, &ctrl, QIB_7220_IBSerDesCtrl_offset ); - - /* Wait for the "trim done" signal */ - for ( i = 0 ; i < LINDA_TRIM_DONE_MAX_WAIT_MS ; i++ ) { - linda_readq ( linda, &intstatus, QIB_7220_IntStatus_offset ); - if ( BIT_GET ( &intstatus, IBSerdesTrimDone ) ) { - rc = 0; - goto out_reset; - } - mdelay ( 1 ); - } - - DBGC ( linda, "Linda %p timed out waiting for trim done\n", linda ); - rc = -ETIMEDOUT; - out_reset: - /* Put the microcontroller back into reset */ - BIT_SET ( &ctrl, ResetIB_uC_Core, 1 ); - linda_writeq ( linda, &ctrl, QIB_7220_IBSerDesCtrl_offset ); - - return rc; -} - -/** - * Initialise the IB SerDes - * - * @v linda Linda device - * @ret rc Return status code - */ -static int linda_init_ib_serdes ( struct linda *linda ) { - struct QIB_7220_Control control; - struct QIB_7220_IBCCtrl ibcctrl; - struct QIB_7220_IBCDDRCtrl ibcddrctrl; - struct QIB_7220_XGXSCfg xgxscfg; - int rc; - - /* Disable link */ - linda_readq ( linda, &control, QIB_7220_Control_offset ); - BIT_SET ( &control, LinkEn, 0 ); - linda_writeq ( linda, &control, QIB_7220_Control_offset ); - - /* Configure sensible defaults for IBC */ - memset ( &ibcctrl, 0, sizeof ( ibcctrl ) ); - BIT_FILL_6 ( &ibcctrl, /* Tuning values taken from Linux driver */ - FlowCtrlPeriod, 0x03, - FlowCtrlWaterMark, 0x05, - MaxPktLen, ( ( LINDA_RECV_HEADER_SIZE + - LINDA_RECV_PAYLOAD_SIZE + - 4 /* ICRC */ ) >> 2 ), - PhyerrThreshold, 0xf, - OverrunThreshold, 0xf, - CreditScale, 0x4 ); - linda_writeq ( linda, &ibcctrl, QIB_7220_IBCCtrl_offset ); - - /* Force SDR only to avoid needing all the DDR tuning, - * Mellanox compatibility hacks etc. SDR is plenty for - * boot-time operation. - */ - linda_readq ( linda, &ibcddrctrl, QIB_7220_IBCDDRCtrl_offset ); - BIT_SET ( &ibcddrctrl, IB_ENHANCED_MODE, 0 ); - BIT_SET ( &ibcddrctrl, SD_SPEED_SDR, 1 ); - BIT_SET ( &ibcddrctrl, SD_SPEED_DDR, 0 ); - BIT_SET ( &ibcddrctrl, SD_SPEED_QDR, 0 ); - BIT_SET ( &ibcddrctrl, HRTBT_ENB, 0 ); - BIT_SET ( &ibcddrctrl, HRTBT_AUTO, 0 ); - linda_writeq ( linda, &ibcddrctrl, QIB_7220_IBCDDRCtrl_offset ); - - /* Set default SerDes parameters */ - if ( ( rc = linda_set_serdes_params ( linda, - linda_serdes_defaults1 ) ) != 0 ) - return rc; - udelay ( 415 ); /* Magic delay while SerDes sorts itself out */ - if ( ( rc = linda_set_serdes_params ( linda, - linda_serdes_defaults2 ) ) != 0 ) - return rc; - - /* Program the microcontroller RAM */ - if ( ( rc = linda_program_uc_ram ( linda ) ) != 0 ) - return rc; - - /* Verify the microcontroller RAM contents */ - if ( DBGLVL_LOG ) { - if ( ( rc = linda_verify_uc_ram ( linda ) ) != 0 ) - return rc; - } - - /* More SerDes tuning */ - if ( ( rc = linda_set_serdes_params ( linda, - linda_serdes_defaults3 ) ) != 0 ) - return rc; - - /* Use the microcontroller to trim the IB link */ - if ( ( rc = linda_trim_ib ( linda ) ) != 0 ) - return rc; - - /* Bring XGXS out of reset */ - linda_readq ( linda, &xgxscfg, QIB_7220_XGXSCfg_offset ); - BIT_SET ( &xgxscfg, tx_rx_reset, 0 ); - BIT_SET ( &xgxscfg, xcv_reset, 0 ); - linda_writeq ( linda, &xgxscfg, QIB_7220_XGXSCfg_offset ); - - return rc; -} - -/*************************************************************************** - * - * PCI layer interface - * - *************************************************************************** - */ - -/** - * Probe PCI device - * - * @v pci PCI device - * @v id PCI ID - * @ret rc Return status code - */ -static int linda_probe ( struct pci_device *pci, - const struct pci_device_id *id __unused ) { - struct ib_device *ibdev; - struct linda *linda; - struct QIB_7220_Revision revision; - int rc; - - /* Allocate Infiniband device */ - ibdev = alloc_ibdev ( sizeof ( *linda ) ); - if ( ! ibdev ) { - rc = -ENOMEM; - goto err_alloc_ibdev; - } - pci_set_drvdata ( pci, ibdev ); - linda = ib_get_drvdata ( ibdev ); - ibdev->op = &linda_ib_operations; - ibdev->dev = &pci->dev; - ibdev->port = 1; - - /* Fix up PCI device */ - adjust_pci_device ( pci ); - - /* Get PCI BARs */ - linda->regs = ioremap ( pci->membase, LINDA_BAR0_SIZE ); - DBGC2 ( linda, "Linda %p has BAR at %08lx\n", linda, pci->membase ); - - /* Print some general data */ - linda_readq ( linda, &revision, QIB_7220_Revision_offset ); - DBGC2 ( linda, "Linda %p board %02lx v%ld.%ld.%ld.%ld\n", linda, - BIT_GET ( &revision, BoardID ), - BIT_GET ( &revision, R_SW ), - BIT_GET ( &revision, R_Arch ), - BIT_GET ( &revision, R_ChipRevMajor ), - BIT_GET ( &revision, R_ChipRevMinor ) ); - - /* Record link capabilities. Note that we force SDR only to - * avoid having to carry extra code for DDR tuning etc. - */ - ibdev->link_width_enabled = ibdev->link_width_supported = - ( IB_LINK_WIDTH_4X | IB_LINK_WIDTH_1X ); - ibdev->link_speed_enabled = ibdev->link_speed_supported = - IB_LINK_SPEED_SDR; - - /* Initialise I2C subsystem */ - if ( ( rc = linda_init_i2c ( linda ) ) != 0 ) - goto err_init_i2c; - - /* Read EEPROM parameters */ - if ( ( rc = linda_read_eeprom ( linda, &ibdev->gid.u.half[1] ) ) != 0 ) - goto err_read_eeprom; - - /* Initialise send datapath */ - if ( ( rc = linda_init_send ( linda ) ) != 0 ) - goto err_init_send; - - /* Initialise receive datapath */ - if ( ( rc = linda_init_recv ( linda ) ) != 0 ) - goto err_init_recv; - - /* Initialise the IB SerDes */ - if ( ( rc = linda_init_ib_serdes ( linda ) ) != 0 ) - goto err_init_ib_serdes; - - /* Register Infiniband device */ - if ( ( rc = register_ibdev ( ibdev ) ) != 0 ) { - DBGC ( linda, "Linda %p could not register IB " - "device: %s\n", linda, strerror ( rc ) ); - goto err_register_ibdev; - } - - return 0; - - unregister_ibdev ( ibdev ); - err_register_ibdev: - linda_fini_recv ( linda ); - err_init_recv: - linda_fini_send ( linda ); - err_init_send: - err_init_ib_serdes: - err_read_eeprom: - err_init_i2c: - ibdev_put ( ibdev ); - err_alloc_ibdev: - return rc; -} - -/** - * Remove PCI device - * - * @v pci PCI device - */ -static void linda_remove ( struct pci_device *pci ) { - struct ib_device *ibdev = pci_get_drvdata ( pci ); - struct linda *linda = ib_get_drvdata ( ibdev ); - - unregister_ibdev ( ibdev ); - linda_fini_recv ( linda ); - linda_fini_send ( linda ); - ibdev_put ( ibdev ); -} - -static struct pci_device_id linda_nics[] = { - PCI_ROM ( 0x1077, 0x7220, "iba7220", "QLE7240/7280 HCA driver", 0 ), -}; - -struct pci_driver linda_driver __pci_driver = { - .ids = linda_nics, - .id_count = ( sizeof ( linda_nics ) / sizeof ( linda_nics[0] ) ), - .probe = linda_probe, - .remove = linda_remove, -}; diff --git a/gpxe/src/drivers/infiniband/linda.h b/gpxe/src/drivers/infiniband/linda.h deleted file mode 100644 index 3068421b..00000000 --- a/gpxe/src/drivers/infiniband/linda.h +++ /dev/null @@ -1,276 +0,0 @@ -#ifndef _LINDA_H -#define _LINDA_H - -/* - * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -FILE_LICENCE ( GPL2_OR_LATER ); - -/** - * @file - * - * QLogic Linda Infiniband HCA - * - */ - -#define BITOPS_LITTLE_ENDIAN -#include <gpxe/bitops.h> -#include "qib_7220_regs.h" - -struct ib_device; - -/** A Linda GPIO register */ -struct QIB_7220_GPIO_pb { - pseudo_bit_t GPIO[16]; - pseudo_bit_t Reserved[48]; -}; -struct QIB_7220_GPIO { - PSEUDO_BIT_STRUCT ( struct QIB_7220_GPIO_pb ); -}; - -/** A Linda general scalar register */ -struct QIB_7220_scalar_pb { - pseudo_bit_t Value[64]; -}; -struct QIB_7220_scalar { - PSEUDO_BIT_STRUCT ( struct QIB_7220_scalar_pb ); -}; - -/** Linda send per-buffer control word */ -struct QIB_7220_SendPbc_pb { - pseudo_bit_t LengthP1_toibc[11]; - pseudo_bit_t Reserved1[4]; - pseudo_bit_t LengthP1_trigger[11]; - pseudo_bit_t Reserved2[3]; - pseudo_bit_t TestEbp[1]; - pseudo_bit_t Test[1]; - pseudo_bit_t Intr[1]; - pseudo_bit_t Reserved3[31]; - pseudo_bit_t VL15[1]; -}; -struct QIB_7220_SendPbc { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendPbc_pb ); -}; - -/** Linda send buffer availability */ -struct QIB_7220_SendBufAvail_pb { - pseudo_bit_t InUseCheck[144][2]; - pseudo_bit_t Reserved[32]; -}; -struct QIB_7220_SendBufAvail { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvail_pb ); -}; - -/** DMA alignment for send buffer availability */ -#define LINDA_SENDBUFAVAIL_ALIGN 64 - -/** A Linda eager receive descriptor */ -struct QIB_7220_RcvEgr_pb { - pseudo_bit_t Addr[37]; - pseudo_bit_t BufSize[3]; - pseudo_bit_t Reserved[24]; -}; -struct QIB_7220_RcvEgr { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvEgr_pb ); -}; - -/** Linda receive header flags */ -struct QIB_7220_RcvHdrFlags_pb { - pseudo_bit_t PktLen[11]; - pseudo_bit_t RcvType[3]; - pseudo_bit_t SoftB[1]; - pseudo_bit_t SoftA[1]; - pseudo_bit_t EgrIndex[12]; - pseudo_bit_t Reserved1[3]; - pseudo_bit_t UseEgrBfr[1]; - pseudo_bit_t RcvSeq[4]; - pseudo_bit_t HdrqOffset[11]; - pseudo_bit_t Reserved2[8]; - pseudo_bit_t IBErr[1]; - pseudo_bit_t MKErr[1]; - pseudo_bit_t TIDErr[1]; - pseudo_bit_t KHdrErr[1]; - pseudo_bit_t MTUErr[1]; - pseudo_bit_t LenErr[1]; - pseudo_bit_t ParityErr[1]; - pseudo_bit_t VCRCErr[1]; - pseudo_bit_t ICRCErr[1]; -}; -struct QIB_7220_RcvHdrFlags { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrFlags_pb ); -}; - -/** Linda memory BAR size */ -#define LINDA_BAR0_SIZE 0x400000 - -/** Linda I2C SCL line GPIO number */ -#define LINDA_GPIO_SCL 0 - -/** Linda I2C SDA line GPIO number */ -#define LINDA_GPIO_SDA 1 - -/** GUID offset within EEPROM */ -#define LINDA_EEPROM_GUID_OFFSET 3 - -/** GUID size within EEPROM */ -#define LINDA_EEPROM_GUID_SIZE 8 - -/** Board serial number offset within EEPROM */ -#define LINDA_EEPROM_SERIAL_OFFSET 12 - -/** Board serial number size within EEPROM */ -#define LINDA_EEPROM_SERIAL_SIZE 12 - -/** Maximum number of send buffers used - * - * This is a policy decision. Must be less than or equal to the total - * number of send buffers supported by the hardware (128). - */ -#define LINDA_MAX_SEND_BUFS 32 - -/** Linda send buffer size */ -#define LINDA_SEND_BUF_SIZE 4096 - -/** Number of contexts (including kernel context) - * - * This is a policy decision. Must be 5, 9 or 17. - */ -#define LINDA_NUM_CONTEXTS 5 - -/** PortCfg values for different numbers of contexts */ -enum linda_portcfg { - LINDA_PORTCFG_5CTX = 0, - LINDA_PORTCFG_9CTX = 1, - LINDA_PORTCFG_17CTX = 2, -}; - -/** PortCfg values for different numbers of contexts */ -#define LINDA_EAGER_ARRAY_SIZE_5CTX_0 2048 -#define LINDA_EAGER_ARRAY_SIZE_5CTX_OTHER 4096 -#define LINDA_EAGER_ARRAY_SIZE_9CTX_0 2048 -#define LINDA_EAGER_ARRAY_SIZE_9CTX_OTHER 2048 -#define LINDA_EAGER_ARRAY_SIZE_17CTX_0 2048 -#define LINDA_EAGER_ARRAY_SIZE_17CTX_OTHER 1024 - -/** Eager buffer required alignment */ -#define LINDA_EAGER_BUFFER_ALIGN 2048 - -/** Eager buffer size encodings */ -enum linda_eager_buffer_size { - LINDA_EAGER_BUFFER_NONE = 0, - LINDA_EAGER_BUFFER_2K = 1, - LINDA_EAGER_BUFFER_4K = 2, - LINDA_EAGER_BUFFER_8K = 3, - LINDA_EAGER_BUFFER_16K = 4, - LINDA_EAGER_BUFFER_32K = 5, - LINDA_EAGER_BUFFER_64K = 6, -}; - -/** Number of RX headers per context - * - * This is a policy decision. - */ -#define LINDA_RECV_HEADER_COUNT 8 - -/** Maximum size of each RX header - * - * This is a policy decision. Must be divisible by 4. - */ -#define LINDA_RECV_HEADER_SIZE 96 - -/** Total size of an RX header ring */ -#define LINDA_RECV_HEADERS_SIZE \ - ( LINDA_RECV_HEADER_SIZE * LINDA_RECV_HEADER_COUNT ) - -/** RX header alignment */ -#define LINDA_RECV_HEADERS_ALIGN 64 - -/** RX payload size - * - * This is a policy decision. Must be a valid eager buffer size. - */ -#define LINDA_RECV_PAYLOAD_SIZE 2048 - -/** QPN used for Infinipath Packets - * - * This is a policy decision. Must have bit 0 clear. Must not be a - * QPN that we will use. - */ -#define LINDA_QP_IDETH 0xdead0 - -/** Maximum time for wait for external parallel bus request, in us */ -#define LINDA_EPB_REQUEST_MAX_WAIT_US 500 - -/** Maximum time for wait for external parallel bus transaction, in us */ -#define LINDA_EPB_XACT_MAX_WAIT_US 500 - -/** Linda external parallel bus chip selects */ -#define LINDA_EPB_CS_SERDES 1 -#define LINDA_EPB_CS_UC 2 - -/** Linda external parallel bus read/write operations */ -#define LINDA_EPB_WRITE 0 -#define LINDA_EPB_READ 1 - -/** Linda external parallel bus register addresses */ -#define LINDA_EPB_ADDRESS( _channel, _element, _reg ) \ - ( (_element) | ( (_channel) << 4 ) | ( (_reg) << 9 ) ) -#define LINDA_EPB_ADDRESS_CHANNEL( _address ) ( ( (_address) >> 4 ) & 0x1f ) -#define LINDA_EPB_ADDRESS_ELEMENT( _address ) ( ( (_address) >> 0 ) & 0x0f ) -#define LINDA_EPB_ADDRESS_REG( _address ) ( ( (_address) >> 9 ) & 0x3f ) - -/** Linda external parallel bus locations - * - * The location is used by the driver to encode both the chip select - * and the EPB address. - */ -#define LINDA_EPB_LOC( _cs, _channel, _element, _reg) \ - ( ( (_cs) << 16 ) | LINDA_EPB_ADDRESS ( _channel, _element, _reg ) ) -#define LINDA_EPB_LOC_ADDRESS( _loc ) ( (_loc) & 0xffff ) -#define LINDA_EPB_LOC_CS( _loc ) ( (_loc) >> 16 ) - -/** Linda external parallel bus microcontroller register addresses */ -#define LINDA_EPB_UC_CHANNEL 6 -#define LINDA_EPB_UC_LOC( _reg ) \ - LINDA_EPB_LOC ( LINDA_EPB_CS_UC, LINDA_EPB_UC_CHANNEL, 0, (_reg) ) -#define LINDA_EPB_UC_CTL LINDA_EPB_UC_LOC ( 0 ) -#define LINDA_EPB_UC_CTL_WRITE 1 -#define LINDA_EPB_UC_CTL_READ 2 -#define LINDA_EPB_UC_ADDR_LO LINDA_EPB_UC_LOC ( 2 ) -#define LINDA_EPB_UC_ADDR_HI LINDA_EPB_UC_LOC ( 3 ) -#define LINDA_EPB_UC_DATA LINDA_EPB_UC_LOC ( 4 ) -#define LINDA_EPB_UC_CHUNK_SIZE 64 - -extern uint8_t linda_ib_fw[8192]; - -/** Maximum time to wait for "trim done" signal, in ms */ -#define LINDA_TRIM_DONE_MAX_WAIT_MS 1000 - -/** Linda link states */ -enum linda_link_state { - LINDA_LINK_STATE_DOWN = 0, - LINDA_LINK_STATE_INIT = 1, - LINDA_LINK_STATE_ARM = 2, - LINDA_LINK_STATE_ACTIVE = 3, - LINDA_LINK_STATE_ACT_DEFER = 4, -}; - -/** Maximum time to wait for link state changes, in us */ -#define LINDA_LINK_STATE_MAX_WAIT_US 20 - -#endif /* _LINDA_H */ diff --git a/gpxe/src/drivers/infiniband/linda_fw.c b/gpxe/src/drivers/infiniband/linda_fw.c deleted file mode 100644 index 968a5f8d..00000000 --- a/gpxe/src/drivers/infiniband/linda_fw.c +++ /dev/null @@ -1,1069 +0,0 @@ -/* - * Copyright (c) 2007, 2008 QLogic Corporation. All rights reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -FILE_LICENCE ( GPL2_ONLY ); - -/* - * This file contains the memory image from the vendor, to be copied into - * the IB SERDES of the IBA7220 during initialization. - * The file also includes the two functions which use this image. - */ - -#include <stdint.h> -#include "linda.h" - -uint8_t linda_ib_fw[8192] = { -/*0000*/0x02, 0x0A, 0x29, 0x02, 0x0A, 0x87, 0xE5, 0xE6, - 0x30, 0xE6, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, -/*0010*/0x00, 0xE5, 0xE2, 0x30, 0xE4, 0x04, 0x7E, 0x01, - 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x5F, 0x60, 0x08, -/*0020*/0x53, 0xF9, 0xF7, 0xE4, 0xF5, 0xFE, 0x80, 0x08, - 0x7F, 0x0A, 0x12, 0x17, 0x31, 0x12, 0x0E, 0xA2, -/*0030*/0x75, 0xFC, 0x08, 0xE4, 0xF5, 0xFD, 0xE5, 0xE7, - 0x20, 0xE7, 0x03, 0x43, 0xF9, 0x08, 0x22, 0x00, -/*0040*/0x01, 0x20, 0x11, 0x00, 0x04, 0x20, 0x00, 0x75, - 0x51, 0x01, 0xE4, 0xF5, 0x52, 0xF5, 0x53, 0xF5, -/*0050*/0x52, 0xF5, 0x7E, 0x7F, 0x04, 0x02, 0x04, 0x38, - 0xC2, 0x36, 0x05, 0x52, 0xE5, 0x52, 0xD3, 0x94, -/*0060*/0x0C, 0x40, 0x05, 0x75, 0x52, 0x01, 0xD2, 0x36, - 0x90, 0x07, 0x0C, 0x74, 0x07, 0xF0, 0xA3, 0x74, -/*0070*/0xFF, 0xF0, 0xE4, 0xF5, 0x0C, 0xA3, 0xF0, 0x90, - 0x07, 0x14, 0xF0, 0xA3, 0xF0, 0x75, 0x0B, 0x20, -/*0080*/0xF5, 0x09, 0xE4, 0xF5, 0x08, 0xE5, 0x08, 0xD3, - 0x94, 0x30, 0x40, 0x03, 0x02, 0x04, 0x04, 0x12, -/*0090*/0x00, 0x06, 0x15, 0x0B, 0xE5, 0x08, 0x70, 0x04, - 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5, 0x09, -/*00A0*/0x70, 0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, - 0xEE, 0x5F, 0x60, 0x05, 0x12, 0x18, 0x71, 0xD2, -/*00B0*/0x35, 0x53, 0xE1, 0xF7, 0xE5, 0x08, 0x45, 0x09, - 0xFF, 0xE5, 0x0B, 0x25, 0xE0, 0x25, 0xE0, 0x24, -/*00C0*/0x83, 0xF5, 0x82, 0xE4, 0x34, 0x07, 0xF5, 0x83, - 0xEF, 0xF0, 0x85, 0xE2, 0x20, 0xE5, 0x52, 0xD3, -/*00D0*/0x94, 0x01, 0x40, 0x0D, 0x12, 0x19, 0xF3, 0xE0, - 0x54, 0xA0, 0x64, 0x40, 0x70, 0x03, 0x02, 0x03, -/*00E0*/0xFB, 0x53, 0xF9, 0xF8, 0x90, 0x94, 0x70, 0xE4, - 0xF0, 0xE0, 0xF5, 0x10, 0xAF, 0x09, 0x12, 0x1E, -/*00F0*/0xB3, 0xAF, 0x08, 0xEF, 0x44, 0x08, 0xF5, 0x82, - 0x75, 0x83, 0x80, 0xE0, 0xF5, 0x29, 0xEF, 0x44, -/*0100*/0x07, 0x12, 0x1A, 0x3C, 0xF5, 0x22, 0x54, 0x40, - 0xD3, 0x94, 0x00, 0x40, 0x1E, 0xE5, 0x29, 0x54, -/*0110*/0xF0, 0x70, 0x21, 0x12, 0x19, 0xF3, 0xE0, 0x44, - 0x80, 0xF0, 0xE5, 0x22, 0x54, 0x30, 0x65, 0x08, -/*0120*/0x70, 0x09, 0x12, 0x19, 0xF3, 0xE0, 0x54, 0xBF, - 0xF0, 0x80, 0x09, 0x12, 0x19, 0xF3, 0x74, 0x40, -/*0130*/0xF0, 0x02, 0x03, 0xFB, 0x12, 0x1A, 0x12, 0x75, - 0x83, 0xAE, 0x74, 0xFF, 0xF0, 0xAF, 0x08, 0x7E, -/*0140*/0x00, 0xEF, 0x44, 0x07, 0xF5, 0x82, 0xE0, 0xFD, - 0xE5, 0x0B, 0x25, 0xE0, 0x25, 0xE0, 0x24, 0x81, -/*0150*/0xF5, 0x82, 0xE4, 0x34, 0x07, 0xF5, 0x83, 0xED, - 0xF0, 0x90, 0x07, 0x0E, 0xE0, 0x04, 0xF0, 0xEF, -/*0160*/0x44, 0x07, 0xF5, 0x82, 0x75, 0x83, 0x98, 0xE0, - 0xF5, 0x28, 0x12, 0x1A, 0x23, 0x40, 0x0C, 0x12, -/*0170*/0x19, 0xF3, 0xE0, 0x44, 0x01, 0x12, 0x1A, 0x32, - 0x02, 0x03, 0xF6, 0xAF, 0x08, 0x7E, 0x00, 0x74, -/*0180*/0x80, 0xCD, 0xEF, 0xCD, 0x8D, 0x82, 0xF5, 0x83, - 0xE0, 0x30, 0xE0, 0x0A, 0x12, 0x19, 0xF3, 0xE0, -/*0190*/0x44, 0x20, 0xF0, 0x02, 0x03, 0xFB, 0x12, 0x19, - 0xF3, 0xE0, 0x54, 0xDF, 0xF0, 0xEE, 0x44, 0xAE, -/*01A0*/0x12, 0x1A, 0x43, 0x30, 0xE4, 0x03, 0x02, 0x03, - 0xFB, 0x74, 0x9E, 0x12, 0x1A, 0x05, 0x20, 0xE0, -/*01B0*/0x03, 0x02, 0x03, 0xFB, 0x8F, 0x82, 0x8E, 0x83, - 0xE0, 0x20, 0xE0, 0x03, 0x02, 0x03, 0xFB, 0x12, -/*01C0*/0x19, 0xF3, 0xE0, 0x44, 0x10, 0xF0, 0xE5, 0xE3, - 0x20, 0xE7, 0x08, 0xE5, 0x08, 0x12, 0x1A, 0x3A, -/*01D0*/0x44, 0x04, 0xF0, 0xAF, 0x08, 0x7E, 0x00, 0xEF, - 0x12, 0x1A, 0x3A, 0x20, 0xE2, 0x34, 0x12, 0x19, -/*01E0*/0xF3, 0xE0, 0x44, 0x08, 0xF0, 0xE5, 0xE4, 0x30, - 0xE6, 0x04, 0x7D, 0x01, 0x80, 0x02, 0x7D, 0x00, -/*01F0*/0xE5, 0x7E, 0xC3, 0x94, 0x04, 0x50, 0x04, 0x7C, - 0x01, 0x80, 0x02, 0x7C, 0x00, 0xEC, 0x4D, 0x60, -/*0200*/0x05, 0xC2, 0x35, 0x02, 0x03, 0xFB, 0xEE, 0x44, - 0xD2, 0x12, 0x1A, 0x43, 0x44, 0x40, 0xF0, 0x02, -/*0210*/0x03, 0xFB, 0x12, 0x19, 0xF3, 0xE0, 0x54, 0xF7, - 0xF0, 0x12, 0x1A, 0x12, 0x75, 0x83, 0xD2, 0xE0, -/*0220*/0x54, 0xBF, 0xF0, 0x90, 0x07, 0x14, 0xE0, 0x04, - 0xF0, 0xE5, 0x7E, 0x70, 0x03, 0x75, 0x7E, 0x01, -/*0230*/0xAF, 0x08, 0x7E, 0x00, 0x12, 0x1A, 0x23, 0x40, - 0x12, 0x12, 0x19, 0xF3, 0xE0, 0x44, 0x01, 0x12, -/*0240*/0x19, 0xF2, 0xE0, 0x54, 0x02, 0x12, 0x1A, 0x32, - 0x02, 0x03, 0xFB, 0x12, 0x19, 0xF3, 0xE0, 0x44, -/*0250*/0x02, 0x12, 0x19, 0xF2, 0xE0, 0x54, 0xFE, 0xF0, - 0xC2, 0x35, 0xEE, 0x44, 0x8A, 0x8F, 0x82, 0xF5, -/*0260*/0x83, 0xE0, 0xF5, 0x17, 0x54, 0x8F, 0x44, 0x40, - 0xF0, 0x74, 0x90, 0xFC, 0xE5, 0x08, 0x44, 0x07, -/*0270*/0xFD, 0xF5, 0x82, 0x8C, 0x83, 0xE0, 0x54, 0x3F, - 0x90, 0x07, 0x02, 0xF0, 0xE0, 0x54, 0xC0, 0x8D, -/*0280*/0x82, 0x8C, 0x83, 0xF0, 0x74, 0x92, 0x12, 0x1A, - 0x05, 0x90, 0x07, 0x03, 0x12, 0x1A, 0x19, 0x74, -/*0290*/0x82, 0x12, 0x1A, 0x05, 0x90, 0x07, 0x04, 0x12, - 0x1A, 0x19, 0x74, 0xB4, 0x12, 0x1A, 0x05, 0x90, -/*02A0*/0x07, 0x05, 0x12, 0x1A, 0x19, 0x74, 0x94, 0xFE, - 0xE5, 0x08, 0x44, 0x06, 0x12, 0x1A, 0x0A, 0xF5, -/*02B0*/0x10, 0x30, 0xE0, 0x04, 0xD2, 0x37, 0x80, 0x02, - 0xC2, 0x37, 0xE5, 0x10, 0x54, 0x7F, 0x8F, 0x82, -/*02C0*/0x8E, 0x83, 0xF0, 0x30, 0x44, 0x30, 0x12, 0x1A, - 0x03, 0x54, 0x80, 0xD3, 0x94, 0x00, 0x40, 0x04, -/*02D0*/0xD2, 0x39, 0x80, 0x02, 0xC2, 0x39, 0x8F, 0x82, - 0x8E, 0x83, 0xE0, 0x44, 0x80, 0xF0, 0x12, 0x1A, -/*02E0*/0x03, 0x54, 0x40, 0xD3, 0x94, 0x00, 0x40, 0x04, - 0xD2, 0x3A, 0x80, 0x02, 0xC2, 0x3A, 0x8F, 0x82, -/*02F0*/0x8E, 0x83, 0xE0, 0x44, 0x40, 0xF0, 0x74, 0x92, - 0xFE, 0xE5, 0x08, 0x44, 0x06, 0x12, 0x1A, 0x0A, -/*0300*/0x30, 0xE7, 0x04, 0xD2, 0x38, 0x80, 0x02, 0xC2, - 0x38, 0x8F, 0x82, 0x8E, 0x83, 0xE0, 0x54, 0x7F, -/*0310*/0xF0, 0x12, 0x1E, 0x46, 0xE4, 0xF5, 0x0A, 0x20, - 0x03, 0x02, 0x80, 0x03, 0x30, 0x43, 0x03, 0x12, -/*0320*/0x19, 0x95, 0x20, 0x02, 0x02, 0x80, 0x03, 0x30, - 0x42, 0x03, 0x12, 0x0C, 0x8F, 0x30, 0x30, 0x06, -/*0330*/0x12, 0x19, 0x95, 0x12, 0x0C, 0x8F, 0x12, 0x0D, - 0x47, 0x12, 0x19, 0xF3, 0xE0, 0x54, 0xFB, 0xF0, -/*0340*/0xE5, 0x0A, 0xC3, 0x94, 0x01, 0x40, 0x46, 0x43, - 0xE1, 0x08, 0x12, 0x19, 0xF3, 0xE0, 0x44, 0x04, -/*0350*/0xF0, 0xE5, 0xE4, 0x20, 0xE7, 0x2A, 0x12, 0x1A, - 0x12, 0x75, 0x83, 0xD2, 0xE0, 0x54, 0x08, 0xD3, -/*0360*/0x94, 0x00, 0x40, 0x04, 0x7F, 0x01, 0x80, 0x02, - 0x7F, 0x00, 0xE5, 0x0A, 0xC3, 0x94, 0x01, 0x40, -/*0370*/0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEF, - 0x5E, 0x60, 0x05, 0x12, 0x1D, 0xD7, 0x80, 0x17, -/*0380*/0x12, 0x1A, 0x12, 0x75, 0x83, 0xD2, 0xE0, 0x44, - 0x08, 0xF0, 0x02, 0x03, 0xFB, 0x12, 0x1A, 0x12, -/*0390*/0x75, 0x83, 0xD2, 0xE0, 0x54, 0xF7, 0xF0, 0x12, - 0x1E, 0x46, 0x7F, 0x08, 0x12, 0x17, 0x31, 0x74, -/*03A0*/0x8E, 0xFE, 0x12, 0x1A, 0x12, 0x8E, 0x83, 0xE0, - 0xF5, 0x10, 0x54, 0xFE, 0xF0, 0xE5, 0x10, 0x44, -/*03B0*/0x01, 0xFF, 0xE5, 0x08, 0xFD, 0xED, 0x44, 0x07, - 0xF5, 0x82, 0xEF, 0xF0, 0xE5, 0x10, 0x54, 0xFE, -/*03C0*/0xFF, 0xED, 0x44, 0x07, 0xF5, 0x82, 0xEF, 0x12, - 0x1A, 0x11, 0x75, 0x83, 0x86, 0xE0, 0x44, 0x10, -/*03D0*/0x12, 0x1A, 0x11, 0xE0, 0x44, 0x10, 0xF0, 0x12, - 0x19, 0xF3, 0xE0, 0x54, 0xFD, 0x44, 0x01, 0xFF, -/*03E0*/0x12, 0x19, 0xF3, 0xEF, 0x12, 0x1A, 0x32, 0x30, - 0x32, 0x0C, 0xE5, 0x08, 0x44, 0x08, 0xF5, 0x82, -/*03F0*/0x75, 0x83, 0x82, 0x74, 0x05, 0xF0, 0xAF, 0x0B, - 0x12, 0x18, 0xD7, 0x74, 0x10, 0x25, 0x08, 0xF5, -/*0400*/0x08, 0x02, 0x00, 0x85, 0x05, 0x09, 0xE5, 0x09, - 0xD3, 0x94, 0x07, 0x50, 0x03, 0x02, 0x00, 0x82, -/*0410*/0xE5, 0x7E, 0xD3, 0x94, 0x00, 0x40, 0x04, 0x7F, - 0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5, 0x7E, 0xC3, -/*0420*/0x94, 0xFA, 0x50, 0x04, 0x7E, 0x01, 0x80, 0x02, - 0x7E, 0x00, 0xEE, 0x5F, 0x60, 0x02, 0x05, 0x7E, -/*0430*/0x30, 0x35, 0x0B, 0x43, 0xE1, 0x01, 0x7F, 0x09, - 0x12, 0x17, 0x31, 0x02, 0x00, 0x58, 0x53, 0xE1, -/*0440*/0xFE, 0x02, 0x00, 0x58, 0x8E, 0x6A, 0x8F, 0x6B, - 0x8C, 0x6C, 0x8D, 0x6D, 0x75, 0x6E, 0x01, 0x75, -/*0450*/0x6F, 0x01, 0x75, 0x70, 0x01, 0xE4, 0xF5, 0x73, - 0xF5, 0x74, 0xF5, 0x75, 0x90, 0x07, 0x2F, 0xF0, -/*0460*/0xF5, 0x3C, 0xF5, 0x3E, 0xF5, 0x46, 0xF5, 0x47, - 0xF5, 0x3D, 0xF5, 0x3F, 0xF5, 0x6F, 0xE5, 0x6F, -/*0470*/0x70, 0x0F, 0xE5, 0x6B, 0x45, 0x6A, 0x12, 0x07, - 0x2A, 0x75, 0x83, 0x80, 0x74, 0x3A, 0xF0, 0x80, -/*0480*/0x09, 0x12, 0x07, 0x2A, 0x75, 0x83, 0x80, 0x74, - 0x1A, 0xF0, 0xE4, 0xF5, 0x6E, 0xC3, 0x74, 0x3F, -/*0490*/0x95, 0x6E, 0xFF, 0x12, 0x08, 0x65, 0x75, 0x83, - 0x82, 0xEF, 0xF0, 0x12, 0x1A, 0x4D, 0x12, 0x08, -/*04A0*/0xC6, 0xE5, 0x33, 0xF0, 0x12, 0x08, 0xFA, 0x12, - 0x08, 0xB1, 0x40, 0xE1, 0xE5, 0x6F, 0x70, 0x0B, -/*04B0*/0x12, 0x07, 0x2A, 0x75, 0x83, 0x80, 0x74, 0x36, - 0xF0, 0x80, 0x09, 0x12, 0x07, 0x2A, 0x75, 0x83, -/*04C0*/0x80, 0x74, 0x16, 0xF0, 0x75, 0x6E, 0x01, 0x12, - 0x07, 0x2A, 0x75, 0x83, 0xB4, 0xE5, 0x6E, 0xF0, -/*04D0*/0x12, 0x1A, 0x4D, 0x74, 0x3F, 0x25, 0x6E, 0xF5, - 0x82, 0xE4, 0x34, 0x00, 0xF5, 0x83, 0xE5, 0x33, -/*04E0*/0xF0, 0x74, 0xBF, 0x25, 0x6E, 0xF5, 0x82, 0xE4, - 0x34, 0x00, 0x12, 0x08, 0xB1, 0x40, 0xD8, 0xE4, -/*04F0*/0xF5, 0x70, 0xF5, 0x46, 0xF5, 0x47, 0xF5, 0x6E, - 0x12, 0x08, 0xFA, 0xF5, 0x83, 0xE0, 0xFE, 0x12, -/*0500*/0x08, 0xC6, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, - 0xEC, 0x3E, 0xFE, 0xAD, 0x3B, 0xD3, 0xEF, 0x9D, -/*0510*/0xEE, 0x9C, 0x50, 0x04, 0x7B, 0x01, 0x80, 0x02, - 0x7B, 0x00, 0xE5, 0x70, 0x70, 0x04, 0x7A, 0x01, -/*0520*/0x80, 0x02, 0x7A, 0x00, 0xEB, 0x5A, 0x60, 0x06, - 0x85, 0x6E, 0x46, 0x75, 0x70, 0x01, 0xD3, 0xEF, -/*0530*/0x9D, 0xEE, 0x9C, 0x50, 0x04, 0x7F, 0x01, 0x80, - 0x02, 0x7F, 0x00, 0xE5, 0x70, 0xB4, 0x01, 0x04, -/*0540*/0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEF, 0x5E, - 0x60, 0x03, 0x85, 0x6E, 0x47, 0x05, 0x6E, 0xE5, -/*0550*/0x6E, 0x64, 0x7F, 0x70, 0xA3, 0xE5, 0x46, 0x60, - 0x05, 0xE5, 0x47, 0xB4, 0x7E, 0x03, 0x85, 0x46, -/*0560*/0x47, 0xE5, 0x6F, 0x70, 0x08, 0x85, 0x46, 0x76, - 0x85, 0x47, 0x77, 0x80, 0x0E, 0xC3, 0x74, 0x7F, -/*0570*/0x95, 0x46, 0xF5, 0x78, 0xC3, 0x74, 0x7F, 0x95, - 0x47, 0xF5, 0x79, 0xE5, 0x6F, 0x70, 0x37, 0xE5, -/*0580*/0x46, 0x65, 0x47, 0x70, 0x0C, 0x75, 0x73, 0x01, - 0x75, 0x74, 0x01, 0xF5, 0x3C, 0xF5, 0x3D, 0x80, -/*0590*/0x35, 0xE4, 0xF5, 0x4E, 0xC3, 0xE5, 0x47, 0x95, - 0x46, 0xF5, 0x3C, 0xC3, 0x13, 0xF5, 0x71, 0x25, -/*05A0*/0x46, 0xF5, 0x72, 0xC3, 0x94, 0x3F, 0x40, 0x05, - 0xE4, 0xF5, 0x3D, 0x80, 0x40, 0xC3, 0x74, 0x3F, -/*05B0*/0x95, 0x72, 0xF5, 0x3D, 0x80, 0x37, 0xE5, 0x46, - 0x65, 0x47, 0x70, 0x0F, 0x75, 0x73, 0x01, 0x75, -/*05C0*/0x75, 0x01, 0xF5, 0x3E, 0xF5, 0x3F, 0x75, 0x4E, - 0x01, 0x80, 0x22, 0xE4, 0xF5, 0x4E, 0xC3, 0xE5, -/*05D0*/0x47, 0x95, 0x46, 0xF5, 0x3E, 0xC3, 0x13, 0xF5, - 0x71, 0x25, 0x46, 0xF5, 0x72, 0xD3, 0x94, 0x3F, -/*05E0*/0x50, 0x05, 0xE4, 0xF5, 0x3F, 0x80, 0x06, 0xE5, - 0x72, 0x24, 0xC1, 0xF5, 0x3F, 0x05, 0x6F, 0xE5, -/*05F0*/0x6F, 0xC3, 0x94, 0x02, 0x50, 0x03, 0x02, 0x04, - 0x6E, 0xE5, 0x6D, 0x45, 0x6C, 0x70, 0x02, 0x80, -/*0600*/0x04, 0xE5, 0x74, 0x45, 0x75, 0x90, 0x07, 0x2F, - 0xF0, 0x7F, 0x01, 0xE5, 0x3E, 0x60, 0x04, 0xE5, -/*0610*/0x3C, 0x70, 0x14, 0xE4, 0xF5, 0x3C, 0xF5, 0x3D, - 0xF5, 0x3E, 0xF5, 0x3F, 0x12, 0x08, 0xD2, 0x70, -/*0620*/0x04, 0xF0, 0x02, 0x06, 0xA4, 0x80, 0x7A, 0xE5, - 0x3C, 0xC3, 0x95, 0x3E, 0x40, 0x07, 0xE5, 0x3C, -/*0630*/0x95, 0x3E, 0xFF, 0x80, 0x06, 0xC3, 0xE5, 0x3E, - 0x95, 0x3C, 0xFF, 0xE5, 0x76, 0xD3, 0x95, 0x79, -/*0640*/0x40, 0x05, 0x85, 0x76, 0x7A, 0x80, 0x03, 0x85, - 0x79, 0x7A, 0xE5, 0x77, 0xC3, 0x95, 0x78, 0x50, -/*0650*/0x05, 0x85, 0x77, 0x7B, 0x80, 0x03, 0x85, 0x78, - 0x7B, 0xE5, 0x7B, 0xD3, 0x95, 0x7A, 0x40, 0x30, -/*0660*/0xE5, 0x7B, 0x95, 0x7A, 0xF5, 0x3C, 0xF5, 0x3E, - 0xC3, 0xE5, 0x7B, 0x95, 0x7A, 0x90, 0x07, 0x19, -/*0670*/0xF0, 0xE5, 0x3C, 0xC3, 0x13, 0xF5, 0x71, 0x25, - 0x7A, 0xF5, 0x72, 0xC3, 0x94, 0x3F, 0x40, 0x05, -/*0680*/0xE4, 0xF5, 0x3D, 0x80, 0x1F, 0xC3, 0x74, 0x3F, - 0x95, 0x72, 0xF5, 0x3D, 0xF5, 0x3F, 0x80, 0x14, -/*0690*/0xE4, 0xF5, 0x3C, 0xF5, 0x3E, 0x90, 0x07, 0x19, - 0xF0, 0x12, 0x08, 0xD2, 0x70, 0x03, 0xF0, 0x80, -/*06A0*/0x03, 0x74, 0x01, 0xF0, 0x12, 0x08, 0x65, 0x75, - 0x83, 0xD0, 0xE0, 0x54, 0x0F, 0xFE, 0xAD, 0x3C, -/*06B0*/0x70, 0x02, 0x7E, 0x07, 0xBE, 0x0F, 0x02, 0x7E, - 0x80, 0xEE, 0xFB, 0xEF, 0xD3, 0x9B, 0x74, 0x80, -/*06C0*/0xF8, 0x98, 0x40, 0x1F, 0xE4, 0xF5, 0x3C, 0xF5, - 0x3E, 0x12, 0x08, 0xD2, 0x70, 0x03, 0xF0, 0x80, -/*06D0*/0x12, 0x74, 0x01, 0xF0, 0xE5, 0x08, 0xFB, 0xEB, - 0x44, 0x07, 0xF5, 0x82, 0x75, 0x83, 0xD2, 0xE0, -/*06E0*/0x44, 0x10, 0xF0, 0xE5, 0x08, 0xFB, 0xEB, 0x44, - 0x09, 0xF5, 0x82, 0x75, 0x83, 0x9E, 0xED, 0xF0, -/*06F0*/0xEB, 0x44, 0x07, 0xF5, 0x82, 0x75, 0x83, 0xCA, - 0xED, 0xF0, 0x12, 0x08, 0x65, 0x75, 0x83, 0xCC, -/*0700*/0xEF, 0xF0, 0x22, 0xE5, 0x08, 0x44, 0x07, 0xF5, - 0x82, 0x75, 0x83, 0xBC, 0xE0, 0x54, 0xF0, 0xF0, -/*0710*/0xE5, 0x08, 0x44, 0x07, 0xF5, 0x82, 0x75, 0x83, - 0xBE, 0xE0, 0x54, 0xF0, 0xF0, 0xE5, 0x08, 0x44, -/*0720*/0x07, 0xF5, 0x82, 0x75, 0x83, 0xC0, 0xE0, 0x54, - 0xF0, 0xF0, 0xE5, 0x08, 0x44, 0x07, 0xF5, 0x82, -/*0730*/0x22, 0xF0, 0x90, 0x07, 0x28, 0xE0, 0xFE, 0xA3, - 0xE0, 0xF5, 0x82, 0x8E, 0x83, 0x22, 0x85, 0x42, -/*0740*/0x42, 0x85, 0x41, 0x41, 0x85, 0x40, 0x40, 0x74, - 0xC0, 0x2F, 0xF5, 0x82, 0x74, 0x02, 0x3E, 0xF5, -/*0750*/0x83, 0xE5, 0x42, 0xF0, 0x74, 0xE0, 0x2F, 0xF5, - 0x82, 0x74, 0x02, 0x3E, 0xF5, 0x83, 0x22, 0xE5, -/*0760*/0x42, 0x29, 0xFD, 0xE4, 0x33, 0xFC, 0xE5, 0x3C, - 0xC3, 0x9D, 0xEC, 0x64, 0x80, 0xF8, 0x74, 0x80, -/*0770*/0x98, 0x22, 0xF5, 0x83, 0xE0, 0x90, 0x07, 0x22, - 0x54, 0x1F, 0xFD, 0xE0, 0xFA, 0xA3, 0xE0, 0xF5, -/*0780*/0x82, 0x8A, 0x83, 0xED, 0xF0, 0x22, 0x90, 0x07, - 0x22, 0xE0, 0xFC, 0xA3, 0xE0, 0xF5, 0x82, 0x8C, -/*0790*/0x83, 0x22, 0x90, 0x07, 0x24, 0xFF, 0xED, 0x44, - 0x07, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x85, -/*07A0*/0x38, 0x38, 0x85, 0x39, 0x39, 0x85, 0x3A, 0x3A, - 0x74, 0xC0, 0x2F, 0xF5, 0x82, 0x74, 0x02, 0x3E, -/*07B0*/0xF5, 0x83, 0x22, 0x90, 0x07, 0x26, 0xFF, 0xED, - 0x44, 0x07, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, -/*07C0*/0xF0, 0x74, 0xA0, 0x2F, 0xF5, 0x82, 0x74, 0x02, - 0x3E, 0xF5, 0x83, 0x22, 0x74, 0xC0, 0x25, 0x11, -/*07D0*/0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0x22, - 0x74, 0x00, 0x25, 0x11, 0xF5, 0x82, 0xE4, 0x34, -/*07E0*/0x02, 0xF5, 0x83, 0x22, 0x74, 0x60, 0x25, 0x11, - 0xF5, 0x82, 0xE4, 0x34, 0x03, 0xF5, 0x83, 0x22, -/*07F0*/0x74, 0x80, 0x25, 0x11, 0xF5, 0x82, 0xE4, 0x34, - 0x03, 0xF5, 0x83, 0x22, 0x74, 0xE0, 0x25, 0x11, -/*0800*/0xF5, 0x82, 0xE4, 0x34, 0x03, 0xF5, 0x83, 0x22, - 0x74, 0x40, 0x25, 0x11, 0xF5, 0x82, 0xE4, 0x34, -/*0810*/0x06, 0xF5, 0x83, 0x22, 0x74, 0x80, 0x2F, 0xF5, - 0x82, 0x74, 0x02, 0x3E, 0xF5, 0x83, 0x22, 0xAF, -/*0820*/0x08, 0x7E, 0x00, 0xEF, 0x44, 0x07, 0xF5, 0x82, - 0x22, 0xF5, 0x83, 0xE5, 0x82, 0x44, 0x07, 0xF5, -/*0830*/0x82, 0xE5, 0x40, 0xF0, 0x22, 0x74, 0x40, 0x25, - 0x11, 0xF5, 0x82, 0xE4, 0x34, 0x02, 0xF5, 0x83, -/*0840*/0x22, 0x74, 0xC0, 0x25, 0x11, 0xF5, 0x82, 0xE4, - 0x34, 0x03, 0xF5, 0x83, 0x22, 0x74, 0x00, 0x25, -/*0850*/0x11, 0xF5, 0x82, 0xE4, 0x34, 0x06, 0xF5, 0x83, - 0x22, 0x74, 0x20, 0x25, 0x11, 0xF5, 0x82, 0xE4, -/*0860*/0x34, 0x06, 0xF5, 0x83, 0x22, 0xE5, 0x08, 0xFD, - 0xED, 0x44, 0x07, 0xF5, 0x82, 0x22, 0xE5, 0x41, -/*0870*/0xF0, 0xE5, 0x65, 0x64, 0x01, 0x45, 0x64, 0x22, - 0x7E, 0x00, 0xFB, 0x7A, 0x00, 0xFD, 0x7C, 0x00, -/*0880*/0x22, 0x74, 0x20, 0x25, 0x11, 0xF5, 0x82, 0xE4, - 0x34, 0x02, 0x22, 0x74, 0xA0, 0x25, 0x11, 0xF5, -/*0890*/0x82, 0xE4, 0x34, 0x03, 0x22, 0x85, 0x3E, 0x42, - 0x85, 0x3F, 0x41, 0x8F, 0x40, 0x22, 0x85, 0x3C, -/*08A0*/0x42, 0x85, 0x3D, 0x41, 0x8F, 0x40, 0x22, 0x75, - 0x45, 0x3F, 0x90, 0x07, 0x20, 0xE4, 0xF0, 0xA3, -/*08B0*/0x22, 0xF5, 0x83, 0xE5, 0x32, 0xF0, 0x05, 0x6E, - 0xE5, 0x6E, 0xC3, 0x94, 0x40, 0x22, 0xF0, 0xE5, -/*08C0*/0x08, 0x44, 0x06, 0xF5, 0x82, 0x22, 0x74, 0x00, - 0x25, 0x6E, 0xF5, 0x82, 0xE4, 0x34, 0x00, 0xF5, -/*08D0*/0x83, 0x22, 0xE5, 0x6D, 0x45, 0x6C, 0x90, 0x07, - 0x2F, 0x22, 0xE4, 0xF9, 0xE5, 0x3C, 0xD3, 0x95, -/*08E0*/0x3E, 0x22, 0x74, 0x80, 0x2E, 0xF5, 0x82, 0xE4, - 0x34, 0x02, 0xF5, 0x83, 0xE0, 0x22, 0x74, 0xA0, -/*08F0*/0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x02, 0xF5, 0x83, - 0xE0, 0x22, 0x74, 0x80, 0x25, 0x6E, 0xF5, 0x82, -/*0900*/0xE4, 0x34, 0x00, 0x22, 0x25, 0x42, 0xFD, 0xE4, - 0x33, 0xFC, 0x22, 0x85, 0x42, 0x42, 0x85, 0x41, -/*0910*/0x41, 0x85, 0x40, 0x40, 0x22, 0xED, 0x4C, 0x60, - 0x03, 0x02, 0x09, 0xE5, 0xEF, 0x4E, 0x70, 0x37, -/*0920*/0x90, 0x07, 0x26, 0x12, 0x07, 0x89, 0xE0, 0xFD, - 0x12, 0x07, 0xCC, 0xED, 0xF0, 0x90, 0x07, 0x28, -/*0930*/0x12, 0x07, 0x89, 0xE0, 0xFD, 0x12, 0x07, 0xD8, - 0xED, 0xF0, 0x12, 0x07, 0x86, 0xE0, 0x54, 0x1F, -/*0940*/0xFD, 0x12, 0x08, 0x81, 0xF5, 0x83, 0xED, 0xF0, - 0x90, 0x07, 0x24, 0x12, 0x07, 0x89, 0xE0, 0x54, -/*0950*/0x1F, 0xFD, 0x12, 0x08, 0x35, 0xED, 0xF0, 0xEF, - 0x64, 0x04, 0x4E, 0x70, 0x37, 0x90, 0x07, 0x26, -/*0960*/0x12, 0x07, 0x89, 0xE0, 0xFD, 0x12, 0x07, 0xE4, - 0xED, 0xF0, 0x90, 0x07, 0x28, 0x12, 0x07, 0x89, -/*0970*/0xE0, 0xFD, 0x12, 0x07, 0xF0, 0xED, 0xF0, 0x12, - 0x07, 0x86, 0xE0, 0x54, 0x1F, 0xFD, 0x12, 0x08, -/*0980*/0x8B, 0xF5, 0x83, 0xED, 0xF0, 0x90, 0x07, 0x24, - 0x12, 0x07, 0x89, 0xE0, 0x54, 0x1F, 0xFD, 0x12, -/*0990*/0x08, 0x41, 0xED, 0xF0, 0xEF, 0x64, 0x01, 0x4E, - 0x70, 0x04, 0x7D, 0x01, 0x80, 0x02, 0x7D, 0x00, -/*09A0*/0xEF, 0x64, 0x02, 0x4E, 0x70, 0x04, 0x7F, 0x01, - 0x80, 0x02, 0x7F, 0x00, 0xEF, 0x4D, 0x60, 0x78, -/*09B0*/0x90, 0x07, 0x26, 0x12, 0x07, 0x35, 0xE0, 0xFF, - 0x12, 0x07, 0xFC, 0xEF, 0x12, 0x07, 0x31, 0xE0, -/*09C0*/0xFF, 0x12, 0x08, 0x08, 0xEF, 0xF0, 0x90, 0x07, - 0x22, 0x12, 0x07, 0x35, 0xE0, 0x54, 0x1F, 0xFF, -/*09D0*/0x12, 0x08, 0x4D, 0xEF, 0xF0, 0x90, 0x07, 0x24, - 0x12, 0x07, 0x35, 0xE0, 0x54, 0x1F, 0xFF, 0x12, -/*09E0*/0x08, 0x59, 0xEF, 0xF0, 0x22, 0x12, 0x07, 0xCC, - 0xE4, 0xF0, 0x12, 0x07, 0xD8, 0xE4, 0xF0, 0x12, -/*09F0*/0x08, 0x81, 0xF5, 0x83, 0xE4, 0xF0, 0x12, 0x08, - 0x35, 0x74, 0x14, 0xF0, 0x12, 0x07, 0xE4, 0xE4, -/*0A00*/0xF0, 0x12, 0x07, 0xF0, 0xE4, 0xF0, 0x12, 0x08, - 0x8B, 0xF5, 0x83, 0xE4, 0xF0, 0x12, 0x08, 0x41, -/*0A10*/0x74, 0x14, 0xF0, 0x12, 0x07, 0xFC, 0xE4, 0xF0, - 0x12, 0x08, 0x08, 0xE4, 0xF0, 0x12, 0x08, 0x4D, -/*0A20*/0xE4, 0xF0, 0x12, 0x08, 0x59, 0x74, 0x14, 0xF0, - 0x22, 0x53, 0xF9, 0xF7, 0x75, 0xFC, 0x10, 0xE4, -/*0A30*/0xF5, 0xFD, 0x75, 0xFE, 0x30, 0xF5, 0xFF, 0xE5, - 0xE7, 0x20, 0xE7, 0x03, 0x43, 0xF9, 0x08, 0xE5, -/*0A40*/0xE6, 0x20, 0xE7, 0x0B, 0x78, 0xFF, 0xE4, 0xF6, - 0xD8, 0xFD, 0x53, 0xE6, 0xFE, 0x80, 0x09, 0x78, -/*0A50*/0x08, 0xE4, 0xF6, 0xD8, 0xFD, 0x53, 0xE6, 0xFE, - 0x75, 0x81, 0x80, 0xE4, 0xF5, 0xA8, 0xD2, 0xA8, -/*0A60*/0xC2, 0xA9, 0xD2, 0xAF, 0xE5, 0xE2, 0x20, 0xE5, - 0x05, 0x20, 0xE6, 0x02, 0x80, 0x03, 0x43, 0xE1, -/*0A70*/0x02, 0xE5, 0xE2, 0x20, 0xE0, 0x0E, 0x90, 0x00, - 0x00, 0x7F, 0x00, 0x7E, 0x08, 0xE4, 0xF0, 0xA3, -/*0A80*/0xDF, 0xFC, 0xDE, 0xFA, 0x02, 0x0A, 0xDB, 0x43, - 0xFA, 0x01, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, -/*0A90*/0xC0, 0x82, 0xC0, 0xD0, 0x12, 0x1C, 0xE7, 0xD0, - 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0, -/*0AA0*/0xE0, 0x53, 0xFA, 0xFE, 0x32, 0x02, 0x1B, 0x55, - 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0xF6, -/*0AB0*/0x08, 0xDF, 0xF9, 0x80, 0x29, 0xE4, 0x93, 0xA3, - 0xF8, 0x54, 0x07, 0x24, 0x0C, 0xC8, 0xC3, 0x33, -/*0AC0*/0xC4, 0x54, 0x0F, 0x44, 0x20, 0xC8, 0x83, 0x40, - 0x04, 0xF4, 0x56, 0x80, 0x01, 0x46, 0xF6, 0xDF, -/*0AD0*/0xE4, 0x80, 0x0B, 0x01, 0x02, 0x04, 0x08, 0x10, - 0x20, 0x40, 0x80, 0x90, 0x00, 0x3F, 0xE4, 0x7E, -/*0AE0*/0x01, 0x93, 0x60, 0xC1, 0xA3, 0xFF, 0x54, 0x3F, - 0x30, 0xE5, 0x09, 0x54, 0x1F, 0xFE, 0xE4, 0x93, -/*0AF0*/0xA3, 0x60, 0x01, 0x0E, 0xCF, 0x54, 0xC0, 0x25, - 0xE0, 0x60, 0xAD, 0x40, 0xB8, 0x80, 0xFE, 0x8C, -/*0B00*/0x64, 0x8D, 0x65, 0x8A, 0x66, 0x8B, 0x67, 0xE4, - 0xF5, 0x69, 0xEF, 0x4E, 0x70, 0x03, 0x02, 0x1D, -/*0B10*/0x55, 0xE4, 0xF5, 0x68, 0xE5, 0x67, 0x45, 0x66, - 0x70, 0x32, 0x12, 0x07, 0x2A, 0x75, 0x83, 0x90, -/*0B20*/0xE4, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC2, 0xE4, - 0x12, 0x07, 0x29, 0x75, 0x83, 0xC4, 0xE4, 0x12, -/*0B30*/0x08, 0x70, 0x70, 0x29, 0x12, 0x07, 0x2A, 0x75, - 0x83, 0x92, 0xE4, 0x12, 0x07, 0x29, 0x75, 0x83, -/*0B40*/0xC6, 0xE4, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC8, - 0xE4, 0xF0, 0x80, 0x11, 0x90, 0x07, 0x26, 0x12, -/*0B50*/0x07, 0x35, 0xE4, 0x12, 0x08, 0x70, 0x70, 0x05, - 0x12, 0x07, 0x32, 0xE4, 0xF0, 0x12, 0x1D, 0x55, -/*0B60*/0x12, 0x1E, 0xBF, 0xE5, 0x67, 0x45, 0x66, 0x70, - 0x33, 0x12, 0x07, 0x2A, 0x75, 0x83, 0x90, 0xE5, -/*0B70*/0x41, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC2, 0xE5, - 0x41, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC4, 0x12, -/*0B80*/0x08, 0x6E, 0x70, 0x29, 0x12, 0x07, 0x2A, 0x75, - 0x83, 0x92, 0xE5, 0x40, 0x12, 0x07, 0x29, 0x75, -/*0B90*/0x83, 0xC6, 0xE5, 0x40, 0x12, 0x07, 0x29, 0x75, - 0x83, 0xC8, 0x80, 0x0E, 0x90, 0x07, 0x26, 0x12, -/*0BA0*/0x07, 0x35, 0x12, 0x08, 0x6E, 0x70, 0x06, 0x12, - 0x07, 0x32, 0xE5, 0x40, 0xF0, 0xAF, 0x69, 0x7E, -/*0BB0*/0x00, 0xAD, 0x67, 0xAC, 0x66, 0x12, 0x04, 0x44, - 0x12, 0x07, 0x2A, 0x75, 0x83, 0xCA, 0xE0, 0xD3, -/*0BC0*/0x94, 0x00, 0x50, 0x0C, 0x05, 0x68, 0xE5, 0x68, - 0xC3, 0x94, 0x05, 0x50, 0x03, 0x02, 0x0B, 0x14, -/*0BD0*/0x22, 0x8C, 0x60, 0x8D, 0x61, 0x12, 0x08, 0xDA, - 0x74, 0x20, 0x40, 0x0D, 0x2F, 0xF5, 0x82, 0x74, -/*0BE0*/0x03, 0x3E, 0xF5, 0x83, 0xE5, 0x3E, 0xF0, 0x80, - 0x0B, 0x2F, 0xF5, 0x82, 0x74, 0x03, 0x3E, 0xF5, -/*0BF0*/0x83, 0xE5, 0x3C, 0xF0, 0xE5, 0x3C, 0xD3, 0x95, - 0x3E, 0x40, 0x3C, 0xE5, 0x61, 0x45, 0x60, 0x70, -/*0C00*/0x10, 0xE9, 0x12, 0x09, 0x04, 0xE5, 0x3E, 0x12, - 0x07, 0x68, 0x40, 0x3B, 0x12, 0x08, 0x95, 0x80, -/*0C10*/0x18, 0xE5, 0x3E, 0xC3, 0x95, 0x38, 0x40, 0x1D, - 0x85, 0x3E, 0x38, 0xE5, 0x3E, 0x60, 0x05, 0x85, -/*0C20*/0x3F, 0x39, 0x80, 0x03, 0x85, 0x39, 0x39, 0x8F, - 0x3A, 0x12, 0x08, 0x14, 0xE5, 0x3E, 0x12, 0x07, -/*0C30*/0xC0, 0xE5, 0x3F, 0xF0, 0x22, 0x80, 0x43, 0xE5, - 0x61, 0x45, 0x60, 0x70, 0x19, 0x12, 0x07, 0x5F, -/*0C40*/0x40, 0x05, 0x12, 0x08, 0x9E, 0x80, 0x27, 0x12, - 0x09, 0x0B, 0x12, 0x08, 0x14, 0xE5, 0x42, 0x12, -/*0C50*/0x07, 0xC0, 0xE5, 0x41, 0xF0, 0x22, 0xE5, 0x3C, - 0xC3, 0x95, 0x38, 0x40, 0x1D, 0x85, 0x3C, 0x38, -/*0C60*/0xE5, 0x3C, 0x60, 0x05, 0x85, 0x3D, 0x39, 0x80, - 0x03, 0x85, 0x39, 0x39, 0x8F, 0x3A, 0x12, 0x08, -/*0C70*/0x14, 0xE5, 0x3C, 0x12, 0x07, 0xC0, 0xE5, 0x3D, - 0xF0, 0x22, 0x85, 0x38, 0x38, 0x85, 0x39, 0x39, -/*0C80*/0x85, 0x3A, 0x3A, 0x12, 0x08, 0x14, 0xE5, 0x38, - 0x12, 0x07, 0xC0, 0xE5, 0x39, 0xF0, 0x22, 0x7F, -/*0C90*/0x06, 0x12, 0x17, 0x31, 0x12, 0x1D, 0x23, 0x12, - 0x0E, 0x04, 0x12, 0x0E, 0x33, 0xE0, 0x44, 0x0A, -/*0CA0*/0xF0, 0x74, 0x8E, 0xFE, 0x12, 0x0E, 0x04, 0x12, - 0x0E, 0x0B, 0xEF, 0xF0, 0xE5, 0x28, 0x30, 0xE5, -/*0CB0*/0x03, 0xD3, 0x80, 0x01, 0xC3, 0x40, 0x05, 0x75, - 0x14, 0x20, 0x80, 0x03, 0x75, 0x14, 0x08, 0x12, -/*0CC0*/0x0E, 0x04, 0x75, 0x83, 0x8A, 0xE5, 0x14, 0xF0, - 0xB4, 0xFF, 0x05, 0x75, 0x12, 0x80, 0x80, 0x06, -/*0CD0*/0xE5, 0x14, 0xC3, 0x13, 0xF5, 0x12, 0xE4, 0xF5, - 0x16, 0xF5, 0x7F, 0x12, 0x19, 0x36, 0x12, 0x13, -/*0CE0*/0xA3, 0xE5, 0x0A, 0xC3, 0x94, 0x01, 0x50, 0x09, - 0x05, 0x16, 0xE5, 0x16, 0xC3, 0x94, 0x14, 0x40, -/*0CF0*/0xEA, 0xE5, 0xE4, 0x20, 0xE7, 0x28, 0x12, 0x0E, - 0x04, 0x75, 0x83, 0xD2, 0xE0, 0x54, 0x08, 0xD3, -/*0D00*/0x94, 0x00, 0x40, 0x04, 0x7F, 0x01, 0x80, 0x02, - 0x7F, 0x00, 0xE5, 0x0A, 0xC3, 0x94, 0x01, 0x40, -/*0D10*/0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEF, - 0x5E, 0x60, 0x03, 0x12, 0x1D, 0xD7, 0xE5, 0x7F, -/*0D20*/0xC3, 0x94, 0x11, 0x40, 0x14, 0x12, 0x0E, 0x04, - 0x75, 0x83, 0xD2, 0xE0, 0x44, 0x80, 0xF0, 0xE5, -/*0D30*/0xE4, 0x20, 0xE7, 0x0F, 0x12, 0x1D, 0xD7, 0x80, - 0x0A, 0x12, 0x0E, 0x04, 0x75, 0x83, 0xD2, 0xE0, -/*0D40*/0x54, 0x7F, 0xF0, 0x12, 0x1D, 0x23, 0x22, 0x74, - 0x8A, 0x85, 0x08, 0x82, 0xF5, 0x83, 0xE5, 0x17, -/*0D50*/0xF0, 0x12, 0x0E, 0x3A, 0xE4, 0xF0, 0x90, 0x07, - 0x02, 0xE0, 0x12, 0x0E, 0x17, 0x75, 0x83, 0x90, -/*0D60*/0xEF, 0xF0, 0x74, 0x92, 0xFE, 0xE5, 0x08, 0x44, - 0x07, 0xFF, 0xF5, 0x82, 0x8E, 0x83, 0xE0, 0x54, -/*0D70*/0xC0, 0xFD, 0x90, 0x07, 0x03, 0xE0, 0x54, 0x3F, - 0x4D, 0x8F, 0x82, 0x8E, 0x83, 0xF0, 0x90, 0x07, -/*0D80*/0x04, 0xE0, 0x12, 0x0E, 0x17, 0x75, 0x83, 0x82, - 0xEF, 0xF0, 0x90, 0x07, 0x05, 0xE0, 0xFF, 0xED, -/*0D90*/0x44, 0x07, 0xF5, 0x82, 0x75, 0x83, 0xB4, 0xEF, - 0x12, 0x0E, 0x03, 0x75, 0x83, 0x80, 0xE0, 0x54, -/*0DA0*/0xBF, 0xF0, 0x30, 0x37, 0x0A, 0x12, 0x0E, 0x91, - 0x75, 0x83, 0x94, 0xE0, 0x44, 0x80, 0xF0, 0x30, -/*0DB0*/0x38, 0x0A, 0x12, 0x0E, 0x91, 0x75, 0x83, 0x92, - 0xE0, 0x44, 0x80, 0xF0, 0xE5, 0x28, 0x30, 0xE4, -/*0DC0*/0x1A, 0x20, 0x39, 0x0A, 0x12, 0x0E, 0x04, 0x75, - 0x83, 0x88, 0xE0, 0x54, 0x7F, 0xF0, 0x20, 0x3A, -/*0DD0*/0x0A, 0x12, 0x0E, 0x04, 0x75, 0x83, 0x88, 0xE0, - 0x54, 0xBF, 0xF0, 0x74, 0x8C, 0xFE, 0x12, 0x0E, -/*0DE0*/0x04, 0x8E, 0x83, 0xE0, 0x54, 0x0F, 0x12, 0x0E, - 0x03, 0x75, 0x83, 0x86, 0xE0, 0x54, 0xBF, 0xF0, -/*0DF0*/0xE5, 0x08, 0x44, 0x06, 0x12, 0x0D, 0xFD, 0x75, - 0x83, 0x8A, 0xE4, 0xF0, 0x22, 0xF5, 0x82, 0x75, -/*0E00*/0x83, 0x82, 0xE4, 0xF0, 0xE5, 0x08, 0x44, 0x07, - 0xF5, 0x82, 0x22, 0x8E, 0x83, 0xE0, 0xF5, 0x10, -/*0E10*/0x54, 0xFE, 0xF0, 0xE5, 0x10, 0x44, 0x01, 0xFF, - 0xE5, 0x08, 0xFD, 0xED, 0x44, 0x07, 0xF5, 0x82, -/*0E20*/0x22, 0xE5, 0x15, 0xC4, 0x54, 0x07, 0xFF, 0xE5, - 0x08, 0xFD, 0xED, 0x44, 0x08, 0xF5, 0x82, 0x75, -/*0E30*/0x83, 0x82, 0x22, 0x75, 0x83, 0x80, 0xE0, 0x44, - 0x40, 0xF0, 0xE5, 0x08, 0x44, 0x08, 0xF5, 0x82, -/*0E40*/0x75, 0x83, 0x8A, 0x22, 0xE5, 0x16, 0x25, 0xE0, - 0x25, 0xE0, 0x24, 0xAF, 0xF5, 0x82, 0xE4, 0x34, -/*0E50*/0x1A, 0xF5, 0x83, 0xE4, 0x93, 0xF5, 0x0D, 0x22, - 0x43, 0xE1, 0x10, 0x43, 0xE1, 0x80, 0x53, 0xE1, -/*0E60*/0xFD, 0x85, 0xE1, 0x10, 0x22, 0xE5, 0x16, 0x25, - 0xE0, 0x25, 0xE0, 0x24, 0xB2, 0xF5, 0x82, 0xE4, -/*0E70*/0x34, 0x1A, 0xF5, 0x83, 0xE4, 0x93, 0x22, 0x85, - 0x55, 0x82, 0x85, 0x54, 0x83, 0xE5, 0x15, 0xF0, -/*0E80*/0x22, 0xE5, 0xE2, 0x54, 0x20, 0xD3, 0x94, 0x00, - 0x22, 0xE5, 0xE2, 0x54, 0x40, 0xD3, 0x94, 0x00, -/*0E90*/0x22, 0xE5, 0x08, 0x44, 0x06, 0xF5, 0x82, 0x22, - 0xFD, 0xE5, 0x08, 0xFB, 0xEB, 0x44, 0x07, 0xF5, -/*0EA0*/0x82, 0x22, 0x53, 0xF9, 0xF7, 0x75, 0xFE, 0x30, - 0x22, 0xEF, 0x4E, 0x70, 0x26, 0x12, 0x07, 0xCC, -/*0EB0*/0xE0, 0xFD, 0x90, 0x07, 0x26, 0x12, 0x07, 0x7B, - 0x12, 0x07, 0xD8, 0xE0, 0xFD, 0x90, 0x07, 0x28, -/*0EC0*/0x12, 0x07, 0x7B, 0x12, 0x08, 0x81, 0x12, 0x07, - 0x72, 0x12, 0x08, 0x35, 0xE0, 0x90, 0x07, 0x24, -/*0ED0*/0x12, 0x07, 0x78, 0xEF, 0x64, 0x04, 0x4E, 0x70, - 0x29, 0x12, 0x07, 0xE4, 0xE0, 0xFD, 0x90, 0x07, -/*0EE0*/0x26, 0x12, 0x07, 0x7B, 0x12, 0x07, 0xF0, 0xE0, - 0xFD, 0x90, 0x07, 0x28, 0x12, 0x07, 0x7B, 0x12, -/*0EF0*/0x08, 0x8B, 0x12, 0x07, 0x72, 0x12, 0x08, 0x41, - 0xE0, 0x54, 0x1F, 0xFD, 0x90, 0x07, 0x24, 0x12, -/*0F00*/0x07, 0x7B, 0xEF, 0x64, 0x01, 0x4E, 0x70, 0x04, - 0x7D, 0x01, 0x80, 0x02, 0x7D, 0x00, 0xEF, 0x64, -/*0F10*/0x02, 0x4E, 0x70, 0x04, 0x7F, 0x01, 0x80, 0x02, - 0x7F, 0x00, 0xEF, 0x4D, 0x60, 0x35, 0x12, 0x07, -/*0F20*/0xFC, 0xE0, 0xFF, 0x90, 0x07, 0x26, 0x12, 0x07, - 0x89, 0xEF, 0xF0, 0x12, 0x08, 0x08, 0xE0, 0xFF, -/*0F30*/0x90, 0x07, 0x28, 0x12, 0x07, 0x89, 0xEF, 0xF0, - 0x12, 0x08, 0x4D, 0xE0, 0x54, 0x1F, 0xFF, 0x12, -/*0F40*/0x07, 0x86, 0xEF, 0xF0, 0x12, 0x08, 0x59, 0xE0, - 0x54, 0x1F, 0xFF, 0x90, 0x07, 0x24, 0x12, 0x07, -/*0F50*/0x89, 0xEF, 0xF0, 0x22, 0xE4, 0xF5, 0x53, 0x12, - 0x0E, 0x81, 0x40, 0x04, 0x7F, 0x01, 0x80, 0x02, -/*0F60*/0x7F, 0x00, 0x12, 0x0E, 0x89, 0x40, 0x04, 0x7E, - 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x4F, 0x70, -/*0F70*/0x03, 0x02, 0x0F, 0xF6, 0x85, 0xE1, 0x10, 0x43, - 0xE1, 0x02, 0x53, 0xE1, 0x0F, 0x85, 0xE1, 0x10, -/*0F80*/0xE4, 0xF5, 0x51, 0xE5, 0xE3, 0x54, 0x3F, 0xF5, - 0x52, 0x12, 0x0E, 0x89, 0x40, 0x1D, 0xAD, 0x52, -/*0F90*/0xAF, 0x51, 0x12, 0x11, 0x18, 0xEF, 0x60, 0x08, - 0x85, 0xE1, 0x10, 0x43, 0xE1, 0x40, 0x80, 0x0B, -/*0FA0*/0x53, 0xE1, 0xBF, 0x12, 0x0E, 0x58, 0x12, 0x00, - 0x06, 0x80, 0xFB, 0xE5, 0xE3, 0x54, 0x3F, 0xF5, -/*0FB0*/0x51, 0xE5, 0xE4, 0x54, 0x3F, 0xF5, 0x52, 0x12, - 0x0E, 0x81, 0x40, 0x1D, 0xAD, 0x52, 0xAF, 0x51, -/*0FC0*/0x12, 0x11, 0x18, 0xEF, 0x60, 0x08, 0x85, 0xE1, - 0x10, 0x43, 0xE1, 0x20, 0x80, 0x0B, 0x53, 0xE1, -/*0FD0*/0xDF, 0x12, 0x0E, 0x58, 0x12, 0x00, 0x06, 0x80, - 0xFB, 0x12, 0x0E, 0x81, 0x40, 0x04, 0x7F, 0x01, -/*0FE0*/0x80, 0x02, 0x7F, 0x00, 0x12, 0x0E, 0x89, 0x40, - 0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, -/*0FF0*/0x4F, 0x60, 0x03, 0x12, 0x0E, 0x5B, 0x22, 0x12, - 0x0E, 0x21, 0xEF, 0xF0, 0x12, 0x10, 0x91, 0x22, -/*1000*/0x02, 0x11, 0x00, 0x02, 0x10, 0x40, 0x02, 0x10, - 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1010*/0x01, 0x20, 0x01, 0x20, 0xE4, 0xF5, 0x57, 0x12, - 0x16, 0xBD, 0x12, 0x16, 0x44, 0xE4, 0x12, 0x10, -/*1020*/0x56, 0x12, 0x14, 0xB7, 0x90, 0x07, 0x26, 0x12, - 0x07, 0x35, 0xE4, 0x12, 0x07, 0x31, 0xE4, 0xF0, -/*1030*/0x12, 0x10, 0x56, 0x12, 0x14, 0xB7, 0x90, 0x07, - 0x26, 0x12, 0x07, 0x35, 0xE5, 0x41, 0x12, 0x07, -/*1040*/0x31, 0xE5, 0x40, 0xF0, 0xAF, 0x57, 0x7E, 0x00, - 0xAD, 0x56, 0x7C, 0x00, 0x12, 0x04, 0x44, 0xAF, -/*1050*/0x56, 0x7E, 0x00, 0x02, 0x11, 0xEE, 0xFF, 0x90, - 0x07, 0x20, 0xA3, 0xE0, 0xFD, 0xE4, 0xF5, 0x56, -/*1060*/0xF5, 0x40, 0xFE, 0xFC, 0xAB, 0x56, 0xFA, 0x12, - 0x11, 0x51, 0x7F, 0x0F, 0x7D, 0x18, 0xE4, 0xF5, -/*1070*/0x56, 0xF5, 0x40, 0xFE, 0xFC, 0xAB, 0x56, 0xFA, - 0x12, 0x15, 0x41, 0xAF, 0x56, 0x7E, 0x00, 0x12, -/*1080*/0x1A, 0xFF, 0xE4, 0xFF, 0xF5, 0x56, 0x7D, 0x1F, - 0xF5, 0x40, 0xFE, 0xFC, 0xAB, 0x56, 0xFA, 0x22, -/*1090*/0x22, 0xE4, 0xF5, 0x55, 0xE5, 0x08, 0xFD, 0x74, - 0xA0, 0xF5, 0x56, 0xED, 0x44, 0x07, 0xF5, 0x57, -/*10A0*/0xE5, 0x28, 0x30, 0xE5, 0x03, 0xD3, 0x80, 0x01, - 0xC3, 0x40, 0x05, 0x7F, 0x28, 0xEF, 0x80, 0x04, -/*10B0*/0x7F, 0x14, 0xEF, 0xC3, 0x13, 0xF5, 0x54, 0xE4, - 0xF9, 0x12, 0x0E, 0x18, 0x75, 0x83, 0x8E, 0xE0, -/*10C0*/0xF5, 0x10, 0xCE, 0xEF, 0xCE, 0xEE, 0xD3, 0x94, - 0x00, 0x40, 0x26, 0xE5, 0x10, 0x54, 0xFE, 0x12, -/*10D0*/0x0E, 0x98, 0x75, 0x83, 0x8E, 0xED, 0xF0, 0xE5, - 0x10, 0x44, 0x01, 0xFD, 0xEB, 0x44, 0x07, 0xF5, -/*10E0*/0x82, 0xED, 0xF0, 0x85, 0x57, 0x82, 0x85, 0x56, - 0x83, 0xE0, 0x30, 0xE3, 0x01, 0x09, 0x1E, 0x80, -/*10F0*/0xD4, 0xC2, 0x34, 0xE9, 0xC3, 0x95, 0x54, 0x40, - 0x02, 0xD2, 0x34, 0x22, 0x02, 0x00, 0x06, 0x22, -/*1100*/0x30, 0x30, 0x11, 0x90, 0x10, 0x00, 0xE4, 0x93, - 0xF5, 0x10, 0x90, 0x10, 0x10, 0xE4, 0x93, 0xF5, -/*1110*/0x10, 0x12, 0x10, 0x90, 0x12, 0x11, 0x50, 0x22, - 0xE4, 0xFC, 0xC3, 0xED, 0x9F, 0xFA, 0xEF, 0xF5, -/*1120*/0x83, 0x75, 0x82, 0x00, 0x79, 0xFF, 0xE4, 0x93, - 0xCC, 0x6C, 0xCC, 0xA3, 0xD9, 0xF8, 0xDA, 0xF6, -/*1130*/0xE5, 0xE2, 0x30, 0xE4, 0x02, 0x8C, 0xE5, 0xED, - 0x24, 0xFF, 0xFF, 0xEF, 0x75, 0x82, 0xFF, 0xF5, -/*1140*/0x83, 0xE4, 0x93, 0x6C, 0x70, 0x03, 0x7F, 0x01, - 0x22, 0x7F, 0x00, 0x22, 0x22, 0x11, 0x00, 0x00, -/*1150*/0x22, 0x8E, 0x58, 0x8F, 0x59, 0x8C, 0x5A, 0x8D, - 0x5B, 0x8A, 0x5C, 0x8B, 0x5D, 0x75, 0x5E, 0x01, -/*1160*/0xE4, 0xF5, 0x5F, 0xF5, 0x60, 0xF5, 0x62, 0x12, - 0x07, 0x2A, 0x75, 0x83, 0xD0, 0xE0, 0xFF, 0xC4, -/*1170*/0x54, 0x0F, 0xF5, 0x61, 0x12, 0x1E, 0xA5, 0x85, - 0x59, 0x5E, 0xD3, 0xE5, 0x5E, 0x95, 0x5B, 0xE5, -/*1180*/0x5A, 0x12, 0x07, 0x6B, 0x50, 0x4B, 0x12, 0x07, - 0x03, 0x75, 0x83, 0xBC, 0xE0, 0x45, 0x5E, 0x12, -/*1190*/0x07, 0x29, 0x75, 0x83, 0xBE, 0xE0, 0x45, 0x5E, - 0x12, 0x07, 0x29, 0x75, 0x83, 0xC0, 0xE0, 0x45, -/*11A0*/0x5E, 0xF0, 0xAF, 0x5F, 0xE5, 0x60, 0x12, 0x08, - 0x78, 0x12, 0x0A, 0xFF, 0xAF, 0x62, 0x7E, 0x00, -/*11B0*/0xAD, 0x5D, 0xAC, 0x5C, 0x12, 0x04, 0x44, 0xE5, - 0x61, 0xAF, 0x5E, 0x7E, 0x00, 0xB4, 0x03, 0x05, -/*11C0*/0x12, 0x1E, 0x21, 0x80, 0x07, 0xAD, 0x5D, 0xAC, - 0x5C, 0x12, 0x13, 0x17, 0x05, 0x5E, 0x02, 0x11, -/*11D0*/0x7A, 0x12, 0x07, 0x03, 0x75, 0x83, 0xBC, 0xE0, - 0x45, 0x40, 0x12, 0x07, 0x29, 0x75, 0x83, 0xBE, -/*11E0*/0xE0, 0x45, 0x40, 0x12, 0x07, 0x29, 0x75, 0x83, - 0xC0, 0xE0, 0x45, 0x40, 0xF0, 0x22, 0x8E, 0x58, -/*11F0*/0x8F, 0x59, 0x75, 0x5A, 0x01, 0x79, 0x01, 0x75, - 0x5B, 0x01, 0xE4, 0xFB, 0x12, 0x07, 0x2A, 0x75, -/*1200*/0x83, 0xAE, 0xE0, 0x54, 0x1A, 0xFF, 0x12, 0x08, - 0x65, 0xE0, 0xC4, 0x13, 0x54, 0x07, 0xFE, 0xEF, -/*1210*/0x70, 0x0C, 0xEE, 0x65, 0x35, 0x70, 0x07, 0x90, - 0x07, 0x2F, 0xE0, 0xB4, 0x01, 0x0D, 0xAF, 0x35, -/*1220*/0x7E, 0x00, 0x12, 0x0E, 0xA9, 0xCF, 0xEB, 0xCF, - 0x02, 0x1E, 0x60, 0xE5, 0x59, 0x64, 0x02, 0x45, -/*1230*/0x58, 0x70, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, - 0x00, 0xE5, 0x59, 0x45, 0x58, 0x70, 0x04, 0x7E, -/*1240*/0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x4F, 0x60, - 0x23, 0x85, 0x41, 0x49, 0x85, 0x40, 0x4B, 0xE5, -/*1250*/0x59, 0x45, 0x58, 0x70, 0x2C, 0xAF, 0x5A, 0xFE, - 0xCD, 0xE9, 0xCD, 0xFC, 0xAB, 0x59, 0xAA, 0x58, -/*1260*/0x12, 0x0A, 0xFF, 0xAF, 0x5B, 0x7E, 0x00, 0x12, - 0x1E, 0x60, 0x80, 0x15, 0xAF, 0x5B, 0x7E, 0x00, -/*1270*/0x12, 0x1E, 0x60, 0x90, 0x07, 0x26, 0x12, 0x07, - 0x35, 0xE5, 0x49, 0x12, 0x07, 0x31, 0xE5, 0x4B, -/*1280*/0xF0, 0xE4, 0xFD, 0xAF, 0x35, 0xFE, 0xFC, 0x12, - 0x09, 0x15, 0x22, 0x8C, 0x64, 0x8D, 0x65, 0x12, -/*1290*/0x08, 0xDA, 0x40, 0x3C, 0xE5, 0x65, 0x45, 0x64, - 0x70, 0x10, 0x12, 0x09, 0x04, 0xC3, 0xE5, 0x3E, -/*12A0*/0x12, 0x07, 0x69, 0x40, 0x3B, 0x12, 0x08, 0x95, - 0x80, 0x18, 0xE5, 0x3E, 0xC3, 0x95, 0x38, 0x40, -/*12B0*/0x1D, 0x85, 0x3E, 0x38, 0xE5, 0x3E, 0x60, 0x05, - 0x85, 0x3F, 0x39, 0x80, 0x03, 0x85, 0x39, 0x39, -/*12C0*/0x8F, 0x3A, 0x12, 0x07, 0xA8, 0xE5, 0x3E, 0x12, - 0x07, 0x53, 0xE5, 0x3F, 0xF0, 0x22, 0x80, 0x3B, -/*12D0*/0xE5, 0x65, 0x45, 0x64, 0x70, 0x11, 0x12, 0x07, - 0x5F, 0x40, 0x05, 0x12, 0x08, 0x9E, 0x80, 0x1F, -/*12E0*/0x12, 0x07, 0x3E, 0xE5, 0x41, 0xF0, 0x22, 0xE5, - 0x3C, 0xC3, 0x95, 0x38, 0x40, 0x1D, 0x85, 0x3C, -/*12F0*/0x38, 0xE5, 0x3C, 0x60, 0x05, 0x85, 0x3D, 0x39, - 0x80, 0x03, 0x85, 0x39, 0x39, 0x8F, 0x3A, 0x12, -/*1300*/0x07, 0xA8, 0xE5, 0x3C, 0x12, 0x07, 0x53, 0xE5, - 0x3D, 0xF0, 0x22, 0x12, 0x07, 0x9F, 0xE5, 0x38, -/*1310*/0x12, 0x07, 0x53, 0xE5, 0x39, 0xF0, 0x22, 0x8C, - 0x63, 0x8D, 0x64, 0x12, 0x08, 0xDA, 0x40, 0x3C, -/*1320*/0xE5, 0x64, 0x45, 0x63, 0x70, 0x10, 0x12, 0x09, - 0x04, 0xC3, 0xE5, 0x3E, 0x12, 0x07, 0x69, 0x40, -/*1330*/0x3B, 0x12, 0x08, 0x95, 0x80, 0x18, 0xE5, 0x3E, - 0xC3, 0x95, 0x38, 0x40, 0x1D, 0x85, 0x3E, 0x38, -/*1340*/0xE5, 0x3E, 0x60, 0x05, 0x85, 0x3F, 0x39, 0x80, - 0x03, 0x85, 0x39, 0x39, 0x8F, 0x3A, 0x12, 0x07, -/*1350*/0xA8, 0xE5, 0x3E, 0x12, 0x07, 0x53, 0xE5, 0x3F, - 0xF0, 0x22, 0x80, 0x3B, 0xE5, 0x64, 0x45, 0x63, -/*1360*/0x70, 0x11, 0x12, 0x07, 0x5F, 0x40, 0x05, 0x12, - 0x08, 0x9E, 0x80, 0x1F, 0x12, 0x07, 0x3E, 0xE5, -/*1370*/0x41, 0xF0, 0x22, 0xE5, 0x3C, 0xC3, 0x95, 0x38, - 0x40, 0x1D, 0x85, 0x3C, 0x38, 0xE5, 0x3C, 0x60, -/*1380*/0x05, 0x85, 0x3D, 0x39, 0x80, 0x03, 0x85, 0x39, - 0x39, 0x8F, 0x3A, 0x12, 0x07, 0xA8, 0xE5, 0x3C, -/*1390*/0x12, 0x07, 0x53, 0xE5, 0x3D, 0xF0, 0x22, 0x12, - 0x07, 0x9F, 0xE5, 0x38, 0x12, 0x07, 0x53, 0xE5, -/*13A0*/0x39, 0xF0, 0x22, 0xE5, 0x0D, 0xFE, 0xE5, 0x08, - 0x8E, 0x54, 0x44, 0x05, 0xF5, 0x55, 0x75, 0x15, -/*13B0*/0x0F, 0xF5, 0x82, 0x12, 0x0E, 0x7A, 0x12, 0x17, - 0xA3, 0x20, 0x31, 0x05, 0x75, 0x15, 0x03, 0x80, -/*13C0*/0x03, 0x75, 0x15, 0x0B, 0xE5, 0x0A, 0xC3, 0x94, - 0x01, 0x50, 0x38, 0x12, 0x14, 0x20, 0x20, 0x31, -/*13D0*/0x06, 0x05, 0x15, 0x05, 0x15, 0x80, 0x04, 0x15, - 0x15, 0x15, 0x15, 0xE5, 0x0A, 0xC3, 0x94, 0x01, -/*13E0*/0x50, 0x21, 0x12, 0x14, 0x20, 0x20, 0x31, 0x04, - 0x05, 0x15, 0x80, 0x02, 0x15, 0x15, 0xE5, 0x0A, -/*13F0*/0xC3, 0x94, 0x01, 0x50, 0x0E, 0x12, 0x0E, 0x77, - 0x12, 0x17, 0xA3, 0x20, 0x31, 0x05, 0x05, 0x15, -/*1400*/0x12, 0x0E, 0x77, 0xE5, 0x15, 0xB4, 0x08, 0x04, - 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5, 0x15, -/*1410*/0xB4, 0x07, 0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, - 0x00, 0xEE, 0x4F, 0x60, 0x02, 0x05, 0x7F, 0x22, -/*1420*/0x85, 0x55, 0x82, 0x85, 0x54, 0x83, 0xE5, 0x15, - 0xF0, 0x12, 0x17, 0xA3, 0x22, 0x12, 0x07, 0x2A, -/*1430*/0x75, 0x83, 0xAE, 0x74, 0xFF, 0x12, 0x07, 0x29, - 0xE0, 0x54, 0x1A, 0xF5, 0x34, 0xE0, 0xC4, 0x13, -/*1440*/0x54, 0x07, 0xF5, 0x35, 0x24, 0xFE, 0x60, 0x24, - 0x24, 0xFE, 0x60, 0x3C, 0x24, 0x04, 0x70, 0x63, -/*1450*/0x75, 0x31, 0x2D, 0xE5, 0x08, 0xFD, 0x74, 0xB6, - 0x12, 0x07, 0x92, 0x74, 0xBC, 0x90, 0x07, 0x22, -/*1460*/0x12, 0x07, 0x95, 0x74, 0x90, 0x12, 0x07, 0xB3, - 0x74, 0x92, 0x80, 0x3C, 0x75, 0x31, 0x3A, 0xE5, -/*1470*/0x08, 0xFD, 0x74, 0xBA, 0x12, 0x07, 0x92, 0x74, - 0xC0, 0x90, 0x07, 0x22, 0x12, 0x07, 0xB6, 0x74, -/*1480*/0xC4, 0x12, 0x07, 0xB3, 0x74, 0xC8, 0x80, 0x20, - 0x75, 0x31, 0x35, 0xE5, 0x08, 0xFD, 0x74, 0xB8, -/*1490*/0x12, 0x07, 0x92, 0x74, 0xBE, 0xFF, 0xED, 0x44, - 0x07, 0x90, 0x07, 0x22, 0xCF, 0xF0, 0xA3, 0xEF, -/*14A0*/0xF0, 0x74, 0xC2, 0x12, 0x07, 0xB3, 0x74, 0xC6, - 0xFF, 0xED, 0x44, 0x07, 0xA3, 0xCF, 0xF0, 0xA3, -/*14B0*/0xEF, 0xF0, 0x22, 0x75, 0x34, 0x01, 0x22, 0x8E, - 0x58, 0x8F, 0x59, 0x8C, 0x5A, 0x8D, 0x5B, 0x8A, -/*14C0*/0x5C, 0x8B, 0x5D, 0x75, 0x5E, 0x01, 0xE4, 0xF5, - 0x5F, 0x12, 0x1E, 0xA5, 0x85, 0x59, 0x5E, 0xD3, -/*14D0*/0xE5, 0x5E, 0x95, 0x5B, 0xE5, 0x5A, 0x12, 0x07, - 0x6B, 0x50, 0x57, 0xE5, 0x5D, 0x45, 0x5C, 0x70, -/*14E0*/0x30, 0x12, 0x07, 0x2A, 0x75, 0x83, 0x92, 0xE5, - 0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC6, 0xE5, -/*14F0*/0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC8, 0xE5, - 0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0x90, 0xE5, -/*1500*/0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC2, 0xE5, - 0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC4, 0x80, -/*1510*/0x03, 0x12, 0x07, 0x32, 0xE5, 0x5E, 0xF0, 0xAF, - 0x5F, 0x7E, 0x00, 0xAD, 0x5D, 0xAC, 0x5C, 0x12, -/*1520*/0x04, 0x44, 0xAF, 0x5E, 0x7E, 0x00, 0xAD, 0x5D, - 0xAC, 0x5C, 0x12, 0x0B, 0xD1, 0x05, 0x5E, 0x02, -/*1530*/0x14, 0xCF, 0xAB, 0x5D, 0xAA, 0x5C, 0xAD, 0x5B, - 0xAC, 0x5A, 0xAF, 0x59, 0xAE, 0x58, 0x02, 0x1B, -/*1540*/0xFB, 0x8C, 0x5C, 0x8D, 0x5D, 0x8A, 0x5E, 0x8B, - 0x5F, 0x75, 0x60, 0x01, 0xE4, 0xF5, 0x61, 0xF5, -/*1550*/0x62, 0xF5, 0x63, 0x12, 0x1E, 0xA5, 0x8F, 0x60, - 0xD3, 0xE5, 0x60, 0x95, 0x5D, 0xE5, 0x5C, 0x12, -/*1560*/0x07, 0x6B, 0x50, 0x61, 0xE5, 0x5F, 0x45, 0x5E, - 0x70, 0x27, 0x12, 0x07, 0x2A, 0x75, 0x83, 0xB6, -/*1570*/0xE5, 0x60, 0x12, 0x07, 0x29, 0x75, 0x83, 0xB8, - 0xE5, 0x60, 0x12, 0x07, 0x29, 0x75, 0x83, 0xBA, -/*1580*/0xE5, 0x60, 0xF0, 0xAF, 0x61, 0x7E, 0x00, 0xE5, - 0x62, 0x12, 0x08, 0x7A, 0x12, 0x0A, 0xFF, 0x80, -/*1590*/0x19, 0x90, 0x07, 0x24, 0x12, 0x07, 0x35, 0xE5, - 0x60, 0x12, 0x07, 0x29, 0x75, 0x83, 0x8E, 0xE4, -/*15A0*/0x12, 0x07, 0x29, 0x74, 0x01, 0x12, 0x07, 0x29, - 0xE4, 0xF0, 0xAF, 0x63, 0x7E, 0x00, 0xAD, 0x5F, -/*15B0*/0xAC, 0x5E, 0x12, 0x04, 0x44, 0xAF, 0x60, 0x7E, - 0x00, 0xAD, 0x5F, 0xAC, 0x5E, 0x12, 0x12, 0x8B, -/*15C0*/0x05, 0x60, 0x02, 0x15, 0x58, 0x22, 0x90, 0x11, - 0x4D, 0xE4, 0x93, 0x90, 0x07, 0x2E, 0xF0, 0x12, -/*15D0*/0x08, 0x1F, 0x75, 0x83, 0xAE, 0xE0, 0x54, 0x1A, - 0xF5, 0x34, 0x70, 0x67, 0xEF, 0x44, 0x07, 0xF5, -/*15E0*/0x82, 0x75, 0x83, 0xCE, 0xE0, 0xFF, 0x13, 0x13, - 0x13, 0x54, 0x07, 0xF5, 0x36, 0x54, 0x0F, 0xD3, -/*15F0*/0x94, 0x00, 0x40, 0x06, 0x12, 0x14, 0x2D, 0x12, - 0x1B, 0xA9, 0xE5, 0x36, 0x54, 0x0F, 0x24, 0xFE, -/*1600*/0x60, 0x0C, 0x14, 0x60, 0x0C, 0x14, 0x60, 0x19, - 0x24, 0x03, 0x70, 0x37, 0x80, 0x10, 0x02, 0x1E, -/*1610*/0x91, 0x12, 0x1E, 0x91, 0x12, 0x07, 0x2A, 0x75, - 0x83, 0xCE, 0xE0, 0x54, 0xEF, 0xF0, 0x02, 0x1D, -/*1620*/0xAE, 0x12, 0x10, 0x14, 0xE4, 0xF5, 0x55, 0x12, - 0x1D, 0x85, 0x05, 0x55, 0xE5, 0x55, 0xC3, 0x94, -/*1630*/0x05, 0x40, 0xF4, 0x12, 0x07, 0x2A, 0x75, 0x83, - 0xCE, 0xE0, 0x54, 0xC7, 0x12, 0x07, 0x29, 0xE0, -/*1640*/0x44, 0x08, 0xF0, 0x22, 0xE4, 0xF5, 0x58, 0xF5, - 0x59, 0xAF, 0x08, 0xEF, 0x44, 0x07, 0xF5, 0x82, -/*1650*/0x75, 0x83, 0xD0, 0xE0, 0xFD, 0xC4, 0x54, 0x0F, - 0xF5, 0x5A, 0xEF, 0x44, 0x07, 0xF5, 0x82, 0x75, -/*1660*/0x83, 0x80, 0x74, 0x01, 0xF0, 0x12, 0x08, 0x21, - 0x75, 0x83, 0x82, 0xE5, 0x45, 0xF0, 0xEF, 0x44, -/*1670*/0x07, 0xF5, 0x82, 0x75, 0x83, 0x8A, 0x74, 0xFF, - 0xF0, 0x12, 0x1A, 0x4D, 0x12, 0x07, 0x2A, 0x75, -/*1680*/0x83, 0xBC, 0xE0, 0x54, 0xEF, 0x12, 0x07, 0x29, - 0x75, 0x83, 0xBE, 0xE0, 0x54, 0xEF, 0x12, 0x07, -/*1690*/0x29, 0x75, 0x83, 0xC0, 0xE0, 0x54, 0xEF, 0x12, - 0x07, 0x29, 0x75, 0x83, 0xBC, 0xE0, 0x44, 0x10, -/*16A0*/0x12, 0x07, 0x29, 0x75, 0x83, 0xBE, 0xE0, 0x44, - 0x10, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC0, 0xE0, -/*16B0*/0x44, 0x10, 0xF0, 0xAF, 0x58, 0xE5, 0x59, 0x12, - 0x08, 0x78, 0x02, 0x0A, 0xFF, 0xE4, 0xF5, 0x58, -/*16C0*/0x7D, 0x01, 0xF5, 0x59, 0xAF, 0x35, 0xFE, 0xFC, - 0x12, 0x09, 0x15, 0x12, 0x07, 0x2A, 0x75, 0x83, -/*16D0*/0xB6, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83, - 0xB8, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83, -/*16E0*/0xBA, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83, - 0xBC, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83, -/*16F0*/0xBE, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83, - 0xC0, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83, -/*1700*/0x90, 0xE4, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC2, - 0xE4, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC4, 0xE4, -/*1710*/0x12, 0x07, 0x29, 0x75, 0x83, 0x92, 0xE4, 0x12, - 0x07, 0x29, 0x75, 0x83, 0xC6, 0xE4, 0x12, 0x07, -/*1720*/0x29, 0x75, 0x83, 0xC8, 0xE4, 0xF0, 0xAF, 0x58, - 0xFE, 0xE5, 0x59, 0x12, 0x08, 0x7A, 0x02, 0x0A, -/*1730*/0xFF, 0xE5, 0xE2, 0x30, 0xE4, 0x6C, 0xE5, 0xE7, - 0x54, 0xC0, 0x64, 0x40, 0x70, 0x64, 0xE5, 0x09, -/*1740*/0xC4, 0x54, 0x30, 0xFE, 0xE5, 0x08, 0x25, 0xE0, - 0x25, 0xE0, 0x54, 0xC0, 0x4E, 0xFE, 0xEF, 0x54, -/*1750*/0x3F, 0x4E, 0xFD, 0xE5, 0x2B, 0xAE, 0x2A, 0x78, - 0x02, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, -/*1760*/0xF5, 0x82, 0x8E, 0x83, 0xED, 0xF0, 0xE5, 0x2B, - 0xAE, 0x2A, 0x78, 0x02, 0xC3, 0x33, 0xCE, 0x33, -/*1770*/0xCE, 0xD8, 0xF9, 0xFF, 0xF5, 0x82, 0x8E, 0x83, - 0xA3, 0xE5, 0xFE, 0xF0, 0x8F, 0x82, 0x8E, 0x83, -/*1780*/0xA3, 0xA3, 0xE5, 0xFD, 0xF0, 0x8F, 0x82, 0x8E, - 0x83, 0xA3, 0xA3, 0xA3, 0xE5, 0xFC, 0xF0, 0xC3, -/*1790*/0xE5, 0x2B, 0x94, 0xFA, 0xE5, 0x2A, 0x94, 0x00, - 0x50, 0x08, 0x05, 0x2B, 0xE5, 0x2B, 0x70, 0x02, -/*17A0*/0x05, 0x2A, 0x22, 0xE4, 0xFF, 0xE4, 0xF5, 0x58, - 0xF5, 0x56, 0xF5, 0x57, 0x74, 0x82, 0xFC, 0x12, -/*17B0*/0x0E, 0x04, 0x8C, 0x83, 0xE0, 0xF5, 0x10, 0x54, - 0x7F, 0xF0, 0xE5, 0x10, 0x44, 0x80, 0x12, 0x0E, -/*17C0*/0x98, 0xED, 0xF0, 0x7E, 0x0A, 0x12, 0x0E, 0x04, - 0x75, 0x83, 0xA0, 0xE0, 0x20, 0xE0, 0x26, 0xDE, -/*17D0*/0xF4, 0x05, 0x57, 0xE5, 0x57, 0x70, 0x02, 0x05, - 0x56, 0xE5, 0x14, 0x24, 0x01, 0xFD, 0xE4, 0x33, -/*17E0*/0xFC, 0xD3, 0xE5, 0x57, 0x9D, 0xE5, 0x56, 0x9C, - 0x40, 0xD9, 0xE5, 0x0A, 0x94, 0x20, 0x50, 0x02, -/*17F0*/0x05, 0x0A, 0x43, 0xE1, 0x08, 0xC2, 0x31, 0x12, - 0x0E, 0x04, 0x75, 0x83, 0xA6, 0xE0, 0x55, 0x12, -/*1800*/0x65, 0x12, 0x70, 0x03, 0xD2, 0x31, 0x22, 0xC2, - 0x31, 0x22, 0x90, 0x07, 0x26, 0xE0, 0xFA, 0xA3, -/*1810*/0xE0, 0xF5, 0x82, 0x8A, 0x83, 0xE0, 0xF5, 0x41, - 0xE5, 0x39, 0xC3, 0x95, 0x41, 0x40, 0x26, 0xE5, -/*1820*/0x39, 0x95, 0x41, 0xC3, 0x9F, 0xEE, 0x12, 0x07, - 0x6B, 0x40, 0x04, 0x7C, 0x01, 0x80, 0x02, 0x7C, -/*1830*/0x00, 0xE5, 0x41, 0x64, 0x3F, 0x60, 0x04, 0x7B, - 0x01, 0x80, 0x02, 0x7B, 0x00, 0xEC, 0x5B, 0x60, -/*1840*/0x29, 0x05, 0x41, 0x80, 0x28, 0xC3, 0xE5, 0x41, - 0x95, 0x39, 0xC3, 0x9F, 0xEE, 0x12, 0x07, 0x6B, -/*1850*/0x40, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, - 0xE5, 0x41, 0x60, 0x04, 0x7E, 0x01, 0x80, 0x02, -/*1860*/0x7E, 0x00, 0xEF, 0x5E, 0x60, 0x04, 0x15, 0x41, - 0x80, 0x03, 0x85, 0x39, 0x41, 0x85, 0x3A, 0x40, -/*1870*/0x22, 0xE5, 0xE2, 0x30, 0xE4, 0x60, 0xE5, 0xE1, - 0x30, 0xE2, 0x5B, 0xE5, 0x09, 0x70, 0x04, 0x7F, -/*1880*/0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5, 0x08, 0x70, - 0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, -/*1890*/0x5F, 0x60, 0x43, 0x53, 0xF9, 0xF8, 0xE5, 0xE2, - 0x30, 0xE4, 0x3B, 0xE5, 0xE1, 0x30, 0xE2, 0x2E, -/*18A0*/0x43, 0xFA, 0x02, 0x53, 0xFA, 0xFB, 0xE4, 0xF5, - 0x10, 0x90, 0x94, 0x70, 0xE5, 0x10, 0xF0, 0xE5, -/*18B0*/0xE1, 0x30, 0xE2, 0xE7, 0x90, 0x94, 0x70, 0xE0, - 0x65, 0x10, 0x60, 0x03, 0x43, 0xFA, 0x04, 0x05, -/*18C0*/0x10, 0x90, 0x94, 0x70, 0xE5, 0x10, 0xF0, 0x70, - 0xE6, 0x12, 0x00, 0x06, 0x80, 0xE1, 0x53, 0xFA, -/*18D0*/0xFD, 0x53, 0xFA, 0xFB, 0x80, 0xC0, 0x22, 0x8F, - 0x54, 0x12, 0x00, 0x06, 0xE5, 0xE1, 0x30, 0xE0, -/*18E0*/0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5, - 0x7E, 0xD3, 0x94, 0x05, 0x40, 0x04, 0x7E, 0x01, -/*18F0*/0x80, 0x02, 0x7E, 0x00, 0xEE, 0x4F, 0x60, 0x3D, - 0x85, 0x54, 0x11, 0xE5, 0xE2, 0x20, 0xE1, 0x32, -/*1900*/0x74, 0xCE, 0x12, 0x1A, 0x05, 0x30, 0xE7, 0x04, - 0x7D, 0x01, 0x80, 0x02, 0x7D, 0x00, 0x8F, 0x82, -/*1910*/0x8E, 0x83, 0xE0, 0x30, 0xE6, 0x04, 0x7F, 0x01, - 0x80, 0x02, 0x7F, 0x00, 0xEF, 0x5D, 0x70, 0x15, -/*1920*/0x12, 0x15, 0xC6, 0x74, 0xCE, 0x12, 0x1A, 0x05, - 0x30, 0xE6, 0x07, 0xE0, 0x44, 0x80, 0xF0, 0x43, -/*1930*/0xF9, 0x80, 0x12, 0x18, 0x71, 0x22, 0x12, 0x0E, - 0x44, 0xE5, 0x16, 0x25, 0xE0, 0x25, 0xE0, 0x24, -/*1940*/0xB0, 0xF5, 0x82, 0xE4, 0x34, 0x1A, 0xF5, 0x83, - 0xE4, 0x93, 0xF5, 0x0F, 0xE5, 0x16, 0x25, 0xE0, -/*1950*/0x25, 0xE0, 0x24, 0xB1, 0xF5, 0x82, 0xE4, 0x34, - 0x1A, 0xF5, 0x83, 0xE4, 0x93, 0xF5, 0x0E, 0x12, -/*1960*/0x0E, 0x65, 0xF5, 0x10, 0xE5, 0x0F, 0x54, 0xF0, - 0x12, 0x0E, 0x17, 0x75, 0x83, 0x8C, 0xEF, 0xF0, -/*1970*/0xE5, 0x0F, 0x30, 0xE0, 0x0C, 0x12, 0x0E, 0x04, - 0x75, 0x83, 0x86, 0xE0, 0x44, 0x40, 0xF0, 0x80, -/*1980*/0x0A, 0x12, 0x0E, 0x04, 0x75, 0x83, 0x86, 0xE0, - 0x54, 0xBF, 0xF0, 0x12, 0x0E, 0x91, 0x75, 0x83, -/*1990*/0x82, 0xE5, 0x0E, 0xF0, 0x22, 0x7F, 0x05, 0x12, - 0x17, 0x31, 0x12, 0x0E, 0x04, 0x12, 0x0E, 0x33, -/*19A0*/0x74, 0x02, 0xF0, 0x74, 0x8E, 0xFE, 0x12, 0x0E, - 0x04, 0x12, 0x0E, 0x0B, 0xEF, 0xF0, 0x75, 0x15, -/*19B0*/0x70, 0x12, 0x0F, 0xF7, 0x20, 0x34, 0x05, 0x75, - 0x15, 0x10, 0x80, 0x03, 0x75, 0x15, 0x50, 0x12, -/*19C0*/0x0F, 0xF7, 0x20, 0x34, 0x04, 0x74, 0x10, 0x80, - 0x02, 0x74, 0xF0, 0x25, 0x15, 0xF5, 0x15, 0x12, -/*19D0*/0x0E, 0x21, 0xEF, 0xF0, 0x12, 0x10, 0x91, 0x20, - 0x34, 0x17, 0xE5, 0x15, 0x64, 0x30, 0x60, 0x0C, -/*19E0*/0x74, 0x10, 0x25, 0x15, 0xF5, 0x15, 0xB4, 0x80, - 0x03, 0xE4, 0xF5, 0x15, 0x12, 0x0E, 0x21, 0xEF, -/*19F0*/0xF0, 0x22, 0xF0, 0xE5, 0x0B, 0x25, 0xE0, 0x25, - 0xE0, 0x24, 0x82, 0xF5, 0x82, 0xE4, 0x34, 0x07, -/*1A00*/0xF5, 0x83, 0x22, 0x74, 0x88, 0xFE, 0xE5, 0x08, - 0x44, 0x07, 0xFF, 0xF5, 0x82, 0x8E, 0x83, 0xE0, -/*1A10*/0x22, 0xF0, 0xE5, 0x08, 0x44, 0x07, 0xF5, 0x82, - 0x22, 0xF0, 0xE0, 0x54, 0xC0, 0x8F, 0x82, 0x8E, -/*1A20*/0x83, 0xF0, 0x22, 0xEF, 0x44, 0x07, 0xF5, 0x82, - 0x75, 0x83, 0x86, 0xE0, 0x54, 0x10, 0xD3, 0x94, -/*1A30*/0x00, 0x22, 0xF0, 0x90, 0x07, 0x15, 0xE0, 0x04, - 0xF0, 0x22, 0x44, 0x06, 0xF5, 0x82, 0x75, 0x83, -/*1A40*/0x9E, 0xE0, 0x22, 0xFE, 0xEF, 0x44, 0x07, 0xF5, - 0x82, 0x8E, 0x83, 0xE0, 0x22, 0xE4, 0x90, 0x07, -/*1A50*/0x2A, 0xF0, 0xA3, 0xF0, 0x12, 0x07, 0x2A, 0x75, - 0x83, 0x82, 0xE0, 0x54, 0x7F, 0x12, 0x07, 0x29, -/*1A60*/0xE0, 0x44, 0x80, 0xF0, 0x12, 0x10, 0xFC, 0x12, - 0x08, 0x1F, 0x75, 0x83, 0xA0, 0xE0, 0x20, 0xE0, -/*1A70*/0x1A, 0x90, 0x07, 0x2B, 0xE0, 0x04, 0xF0, 0x70, - 0x06, 0x90, 0x07, 0x2A, 0xE0, 0x04, 0xF0, 0x90, -/*1A80*/0x07, 0x2A, 0xE0, 0xB4, 0x10, 0xE1, 0xA3, 0xE0, - 0xB4, 0x00, 0xDC, 0xEE, 0x44, 0xA6, 0xFC, 0xEF, -/*1A90*/0x44, 0x07, 0xF5, 0x82, 0x8C, 0x83, 0xE0, 0xF5, - 0x32, 0xEE, 0x44, 0xA8, 0xFE, 0xEF, 0x44, 0x07, -/*1AA0*/0xF5, 0x82, 0x8E, 0x83, 0xE0, 0xF5, 0x33, 0x22, - 0x01, 0x20, 0x11, 0x00, 0x04, 0x20, 0x00, 0x90, -/*1AB0*/0x00, 0x20, 0x0F, 0x92, 0x00, 0x21, 0x0F, 0x94, - 0x00, 0x22, 0x0F, 0x96, 0x00, 0x23, 0x0F, 0x98, -/*1AC0*/0x00, 0x24, 0x0F, 0x9A, 0x00, 0x25, 0x0F, 0x9C, - 0x00, 0x26, 0x0F, 0x9E, 0x00, 0x27, 0x0F, 0xA0, -/*1AD0*/0x01, 0x20, 0x01, 0xA2, 0x01, 0x21, 0x01, 0xA4, - 0x01, 0x22, 0x01, 0xA6, 0x01, 0x23, 0x01, 0xA8, -/*1AE0*/0x01, 0x24, 0x01, 0xAA, 0x01, 0x25, 0x01, 0xAC, - 0x01, 0x26, 0x01, 0xAE, 0x01, 0x27, 0x01, 0xB0, -/*1AF0*/0x01, 0x28, 0x01, 0xB4, 0x00, 0x28, 0x0F, 0xB6, - 0x40, 0x28, 0x0F, 0xB8, 0x61, 0x28, 0x01, 0xCB, -/*1B00*/0xEF, 0xCB, 0xCA, 0xEE, 0xCA, 0x7F, 0x01, 0xE4, - 0xFD, 0xEB, 0x4A, 0x70, 0x24, 0xE5, 0x08, 0xF5, -/*1B10*/0x82, 0x74, 0xB6, 0x12, 0x08, 0x29, 0xE5, 0x08, - 0xF5, 0x82, 0x74, 0xB8, 0x12, 0x08, 0x29, 0xE5, -/*1B20*/0x08, 0xF5, 0x82, 0x74, 0xBA, 0x12, 0x08, 0x29, - 0x7E, 0x00, 0x7C, 0x00, 0x12, 0x0A, 0xFF, 0x80, -/*1B30*/0x12, 0x90, 0x07, 0x26, 0x12, 0x07, 0x35, 0xE5, - 0x41, 0xF0, 0x90, 0x07, 0x24, 0x12, 0x07, 0x35, -/*1B40*/0xE5, 0x40, 0xF0, 0x12, 0x07, 0x2A, 0x75, 0x83, - 0x8E, 0xE4, 0x12, 0x07, 0x29, 0x74, 0x01, 0x12, -/*1B50*/0x07, 0x29, 0xE4, 0xF0, 0x22, 0xE4, 0xF5, 0x26, - 0xF5, 0x27, 0x53, 0xE1, 0xFE, 0xF5, 0x2A, 0x75, -/*1B60*/0x2B, 0x01, 0xF5, 0x08, 0x7F, 0x01, 0x12, 0x17, - 0x31, 0x30, 0x30, 0x1C, 0x90, 0x1A, 0xA9, 0xE4, -/*1B70*/0x93, 0xF5, 0x10, 0x90, 0x1F, 0xF9, 0xE4, 0x93, - 0xF5, 0x10, 0x90, 0x00, 0x41, 0xE4, 0x93, 0xF5, -/*1B80*/0x10, 0x90, 0x1E, 0xCA, 0xE4, 0x93, 0xF5, 0x10, - 0x7F, 0x02, 0x12, 0x17, 0x31, 0x12, 0x0F, 0x54, -/*1B90*/0x7F, 0x03, 0x12, 0x17, 0x31, 0x12, 0x00, 0x06, - 0xE5, 0xE2, 0x30, 0xE7, 0x09, 0x12, 0x10, 0x00, -/*1BA0*/0x30, 0x30, 0x03, 0x12, 0x11, 0x00, 0x02, 0x00, - 0x47, 0x12, 0x08, 0x1F, 0x75, 0x83, 0xD0, 0xE0, -/*1BB0*/0xC4, 0x54, 0x0F, 0xFD, 0x75, 0x43, 0x01, 0x75, - 0x44, 0xFF, 0x12, 0x08, 0xAA, 0x74, 0x04, 0xF0, -/*1BC0*/0x75, 0x3B, 0x01, 0xED, 0x14, 0x60, 0x0C, 0x14, - 0x60, 0x0B, 0x14, 0x60, 0x0F, 0x24, 0x03, 0x70, -/*1BD0*/0x0B, 0x80, 0x09, 0x80, 0x00, 0x12, 0x08, 0xA7, - 0x04, 0xF0, 0x80, 0x06, 0x12, 0x08, 0xA7, 0x74, -/*1BE0*/0x04, 0xF0, 0xEE, 0x44, 0x82, 0xFE, 0xEF, 0x44, - 0x07, 0xF5, 0x82, 0x8E, 0x83, 0xE5, 0x45, 0x12, -/*1BF0*/0x08, 0xBE, 0x75, 0x83, 0x82, 0xE5, 0x31, 0xF0, - 0x02, 0x11, 0x4C, 0x8E, 0x60, 0x8F, 0x61, 0x12, -/*1C00*/0x1E, 0xA5, 0xE4, 0xFF, 0xCE, 0xED, 0xCE, 0xEE, - 0xD3, 0x95, 0x61, 0xE5, 0x60, 0x12, 0x07, 0x6B, -/*1C10*/0x40, 0x39, 0x74, 0x20, 0x2E, 0xF5, 0x82, 0xE4, - 0x34, 0x03, 0xF5, 0x83, 0xE0, 0x70, 0x03, 0xFF, -/*1C20*/0x80, 0x26, 0x12, 0x08, 0xE2, 0xFD, 0xC3, 0x9F, - 0x40, 0x1E, 0xCF, 0xED, 0xCF, 0xEB, 0x4A, 0x70, -/*1C30*/0x0B, 0x8D, 0x42, 0x12, 0x08, 0xEE, 0xF5, 0x41, - 0x8E, 0x40, 0x80, 0x0C, 0x12, 0x08, 0xE2, 0xF5, -/*1C40*/0x38, 0x12, 0x08, 0xEE, 0xF5, 0x39, 0x8E, 0x3A, - 0x1E, 0x80, 0xBC, 0x22, 0x75, 0x58, 0x01, 0xE5, -/*1C50*/0x35, 0x70, 0x0C, 0x12, 0x07, 0xCC, 0xE0, 0xF5, - 0x4A, 0x12, 0x07, 0xD8, 0xE0, 0xF5, 0x4C, 0xE5, -/*1C60*/0x35, 0xB4, 0x04, 0x0C, 0x12, 0x07, 0xE4, 0xE0, - 0xF5, 0x4A, 0x12, 0x07, 0xF0, 0xE0, 0xF5, 0x4C, -/*1C70*/0xE5, 0x35, 0xB4, 0x01, 0x04, 0x7F, 0x01, 0x80, - 0x02, 0x7F, 0x00, 0xE5, 0x35, 0xB4, 0x02, 0x04, -/*1C80*/0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x4F, - 0x60, 0x0C, 0x12, 0x07, 0xFC, 0xE0, 0xF5, 0x4A, -/*1C90*/0x12, 0x08, 0x08, 0xE0, 0xF5, 0x4C, 0x85, 0x41, - 0x49, 0x85, 0x40, 0x4B, 0x22, 0x75, 0x5B, 0x01, -/*1CA0*/0x90, 0x07, 0x24, 0x12, 0x07, 0x35, 0xE0, 0x54, - 0x1F, 0xFF, 0xD3, 0x94, 0x02, 0x50, 0x04, 0x8F, -/*1CB0*/0x58, 0x80, 0x05, 0xEF, 0x24, 0xFE, 0xF5, 0x58, - 0xEF, 0xC3, 0x94, 0x18, 0x40, 0x05, 0x75, 0x59, -/*1CC0*/0x18, 0x80, 0x04, 0xEF, 0x04, 0xF5, 0x59, 0x85, - 0x43, 0x5A, 0xAF, 0x58, 0x7E, 0x00, 0xAD, 0x59, -/*1CD0*/0x7C, 0x00, 0xAB, 0x5B, 0x7A, 0x00, 0x12, 0x15, - 0x41, 0xAF, 0x5A, 0x7E, 0x00, 0x12, 0x18, 0x0A, -/*1CE0*/0xAF, 0x5B, 0x7E, 0x00, 0x02, 0x1A, 0xFF, 0xE5, - 0xE2, 0x30, 0xE7, 0x0E, 0x12, 0x10, 0x03, 0xC2, -/*1CF0*/0x30, 0x30, 0x30, 0x03, 0x12, 0x10, 0xFF, 0x20, - 0x33, 0x28, 0xE5, 0xE7, 0x30, 0xE7, 0x05, 0x12, -/*1D00*/0x0E, 0xA2, 0x80, 0x0D, 0xE5, 0xFE, 0xC3, 0x94, - 0x20, 0x50, 0x06, 0x12, 0x0E, 0xA2, 0x43, 0xF9, -/*1D10*/0x08, 0xE5, 0xF2, 0x30, 0xE7, 0x03, 0x53, 0xF9, - 0x7F, 0xE5, 0xF1, 0x54, 0x70, 0xD3, 0x94, 0x00, -/*1D20*/0x50, 0xD8, 0x22, 0x12, 0x0E, 0x04, 0x75, 0x83, - 0x80, 0xE4, 0xF0, 0xE5, 0x08, 0x44, 0x07, 0x12, -/*1D30*/0x0D, 0xFD, 0x75, 0x83, 0x84, 0x12, 0x0E, 0x02, - 0x75, 0x83, 0x86, 0x12, 0x0E, 0x02, 0x75, 0x83, -/*1D40*/0x8C, 0xE0, 0x54, 0xF3, 0x12, 0x0E, 0x03, 0x75, - 0x83, 0x8E, 0x12, 0x0E, 0x02, 0x75, 0x83, 0x94, -/*1D50*/0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x12, 0x07, 0x2A, - 0x75, 0x83, 0x8E, 0xE4, 0x12, 0x07, 0x29, 0x74, -/*1D60*/0x01, 0x12, 0x07, 0x29, 0xE4, 0x12, 0x08, 0xBE, - 0x75, 0x83, 0x8C, 0xE0, 0x44, 0x20, 0x12, 0x08, -/*1D70*/0xBE, 0xE0, 0x54, 0xDF, 0xF0, 0x74, 0x84, 0x85, - 0x08, 0x82, 0xF5, 0x83, 0xE0, 0x54, 0x7F, 0xF0, -/*1D80*/0xE0, 0x44, 0x80, 0xF0, 0x22, 0x75, 0x56, 0x01, - 0xE4, 0xFD, 0xF5, 0x57, 0xAF, 0x35, 0xFE, 0xFC, -/*1D90*/0x12, 0x09, 0x15, 0x12, 0x1C, 0x9D, 0x12, 0x1E, - 0x7A, 0x12, 0x1C, 0x4C, 0xAF, 0x57, 0x7E, 0x00, -/*1DA0*/0xAD, 0x56, 0x7C, 0x00, 0x12, 0x04, 0x44, 0xAF, - 0x56, 0x7E, 0x00, 0x02, 0x11, 0xEE, 0x75, 0x56, -/*1DB0*/0x01, 0xE4, 0xFD, 0xF5, 0x57, 0xAF, 0x35, 0xFE, - 0xFC, 0x12, 0x09, 0x15, 0x12, 0x1C, 0x9D, 0x12, -/*1DC0*/0x1E, 0x7A, 0x12, 0x1C, 0x4C, 0xAF, 0x57, 0x7E, - 0x00, 0xAD, 0x56, 0x7C, 0x00, 0x12, 0x04, 0x44, -/*1DD0*/0xAF, 0x56, 0x7E, 0x00, 0x02, 0x11, 0xEE, 0xE4, - 0xF5, 0x16, 0x12, 0x0E, 0x44, 0xFE, 0xE5, 0x08, -/*1DE0*/0x44, 0x05, 0xFF, 0x12, 0x0E, 0x65, 0x8F, 0x82, - 0x8E, 0x83, 0xF0, 0x05, 0x16, 0xE5, 0x16, 0xC3, -/*1DF0*/0x94, 0x14, 0x40, 0xE6, 0xE5, 0x08, 0x12, 0x0E, - 0x2B, 0xE4, 0xF0, 0x22, 0xE4, 0xF5, 0x58, 0xF5, -/*1E00*/0x59, 0xF5, 0x5A, 0xFF, 0xFE, 0xAD, 0x58, 0xFC, - 0x12, 0x09, 0x15, 0x7F, 0x04, 0x7E, 0x00, 0xAD, -/*1E10*/0x58, 0x7C, 0x00, 0x12, 0x09, 0x15, 0x7F, 0x02, - 0x7E, 0x00, 0xAD, 0x58, 0x7C, 0x00, 0x02, 0x09, -/*1E20*/0x15, 0xE5, 0x3C, 0x25, 0x3E, 0xFC, 0xE5, 0x42, - 0x24, 0x00, 0xFB, 0xE4, 0x33, 0xFA, 0xEC, 0xC3, -/*1E30*/0x9B, 0xEA, 0x12, 0x07, 0x6B, 0x40, 0x0B, 0x8C, - 0x42, 0xE5, 0x3D, 0x25, 0x3F, 0xF5, 0x41, 0x8F, -/*1E40*/0x40, 0x22, 0x12, 0x09, 0x0B, 0x22, 0x74, 0x84, - 0xF5, 0x18, 0x85, 0x08, 0x19, 0x85, 0x19, 0x82, -/*1E50*/0x85, 0x18, 0x83, 0xE0, 0x54, 0x7F, 0xF0, 0xE0, - 0x44, 0x80, 0xF0, 0xE0, 0x44, 0x80, 0xF0, 0x22, -/*1E60*/0xEF, 0x4E, 0x70, 0x0B, 0x12, 0x07, 0x2A, 0x75, - 0x83, 0xD2, 0xE0, 0x54, 0xDF, 0xF0, 0x22, 0x12, -/*1E70*/0x07, 0x2A, 0x75, 0x83, 0xD2, 0xE0, 0x44, 0x20, - 0xF0, 0x22, 0x75, 0x58, 0x01, 0x90, 0x07, 0x26, -/*1E80*/0x12, 0x07, 0x35, 0xE0, 0x54, 0x3F, 0xF5, 0x41, - 0x12, 0x07, 0x32, 0xE0, 0x54, 0x3F, 0xF5, 0x40, -/*1E90*/0x22, 0x75, 0x56, 0x02, 0xE4, 0xF5, 0x57, 0x12, - 0x1D, 0xFC, 0xAF, 0x57, 0x7E, 0x00, 0xAD, 0x56, -/*1EA0*/0x7C, 0x00, 0x02, 0x04, 0x44, 0xE4, 0xF5, 0x42, - 0xF5, 0x41, 0xF5, 0x40, 0xF5, 0x38, 0xF5, 0x39, -/*1EB0*/0xF5, 0x3A, 0x22, 0xEF, 0x54, 0x07, 0xFF, 0xE5, - 0xF9, 0x54, 0xF8, 0x4F, 0xF5, 0xF9, 0x22, 0x7F, -/*1EC0*/0x01, 0xE4, 0xFE, 0x0F, 0x0E, 0xBE, 0xFF, 0xFB, - 0x22, 0x01, 0x20, 0x00, 0x01, 0x04, 0x20, 0x00, -/*1ED0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1EE0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1EF0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F00*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F10*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F20*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F30*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F40*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F50*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F60*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F70*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F80*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1F90*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1FA0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1FB0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1FC0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1FD0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1FE0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*1FF0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x20, 0x11, 0x00, 0x04, 0x20, 0x00, 0x81 -}; diff --git a/gpxe/src/drivers/infiniband/mlx_bitops.h b/gpxe/src/drivers/infiniband/mlx_bitops.h deleted file mode 100644 index 71a9bf1e..00000000 --- a/gpxe/src/drivers/infiniband/mlx_bitops.h +++ /dev/null @@ -1,223 +0,0 @@ -#ifndef _MLX_BITOPS_H -#define _MLX_BITOPS_H - -/* - * Copyright (C) 2007 Michael Brown <mbrown@fensystems.co.uk>. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -FILE_LICENCE ( GPL2_OR_LATER ); - -/** - * @file - * - * Mellanox bit operations - * - */ - -/* Datatype used to represent a bit in the Mellanox autogenerated headers */ -typedef unsigned char pseudo_bit_t; - -/** - * Wrapper structure for pseudo_bit_t structures - * - * This structure provides a wrapper around the autogenerated - * pseudo_bit_t structures. It has the correct size, and also - * encapsulates type information about the underlying pseudo_bit_t - * structure, which allows the MLX_FILL etc. macros to work without - * requiring explicit type information. - */ -#define MLX_DECLARE_STRUCT( _structure ) \ - _structure { \ - union { \ - uint8_t bytes[ sizeof ( struct _structure ## _st ) / 8 ]; \ - uint32_t dwords[ sizeof ( struct _structure ## _st ) / 32 ]; \ - struct _structure ## _st *dummy[0]; \ - } u; \ - } - -/** Get pseudo_bit_t structure type from wrapper structure pointer */ -#define MLX_PSEUDO_STRUCT( _ptr ) \ - typeof ( *((_ptr)->u.dummy[0]) ) - -/** Bit offset of a field within a pseudo_bit_t structure */ -#define MLX_BIT_OFFSET( _structure_st, _field ) \ - offsetof ( _structure_st, _field ) - -/** Dword offset of a field within a pseudo_bit_t structure */ -#define MLX_DWORD_OFFSET( _structure_st, _field ) \ - ( MLX_BIT_OFFSET ( _structure_st, _field ) / 32 ) - -/** Dword bit offset of a field within a pseudo_bit_t structure - * - * Yes, using mod-32 would work, but would lose the check for the - * error of specifying a mismatched field name and dword index. - */ -#define MLX_DWORD_BIT_OFFSET( _structure_st, _index, _field ) \ - ( MLX_BIT_OFFSET ( _structure_st, _field ) - ( 32 * (_index) ) ) - -/** Bit width of a field within a pseudo_bit_t structure */ -#define MLX_BIT_WIDTH( _structure_st, _field ) \ - sizeof ( ( ( _structure_st * ) NULL )->_field ) - -/** Bit mask for a field within a pseudo_bit_t structure */ -#define MLX_BIT_MASK( _structure_st, _field ) \ - ( ( ~( ( uint32_t ) 0 ) ) >> \ - ( 32 - MLX_BIT_WIDTH ( _structure_st, _field ) ) ) - -/* - * Assemble native-endian dword from named fields and values - * - */ - -#define MLX_ASSEMBLE_1( _structure_st, _index, _field, _value ) \ - ( (_value) << MLX_DWORD_BIT_OFFSET ( _structure_st, _index, _field ) ) - -#define MLX_ASSEMBLE_2( _structure_st, _index, _field, _value, ... ) \ - ( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \ - MLX_ASSEMBLE_1 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_ASSEMBLE_3( _structure_st, _index, _field, _value, ... ) \ - ( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \ - MLX_ASSEMBLE_2 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_ASSEMBLE_4( _structure_st, _index, _field, _value, ... ) \ - ( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \ - MLX_ASSEMBLE_3 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_ASSEMBLE_5( _structure_st, _index, _field, _value, ... ) \ - ( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \ - MLX_ASSEMBLE_4 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_ASSEMBLE_6( _structure_st, _index, _field, _value, ... ) \ - ( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \ - MLX_ASSEMBLE_5 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_ASSEMBLE_7( _structure_st, _index, _field, _value, ... ) \ - ( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \ - MLX_ASSEMBLE_6 ( _structure_st, _index, __VA_ARGS__ ) ) - -/* - * Build native-endian (positive) dword bitmasks from named fields - * - */ - -#define MLX_MASK_1( _structure_st, _index, _field ) \ - ( MLX_BIT_MASK ( _structure_st, _field ) << \ - MLX_DWORD_BIT_OFFSET ( _structure_st, _index, _field ) ) - -#define MLX_MASK_2( _structure_st, _index, _field, ... ) \ - ( MLX_MASK_1 ( _structure_st, _index, _field ) | \ - MLX_MASK_1 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_MASK_3( _structure_st, _index, _field, ... ) \ - ( MLX_MASK_1 ( _structure_st, _index, _field ) | \ - MLX_MASK_2 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_MASK_4( _structure_st, _index, _field, ... ) \ - ( MLX_MASK_1 ( _structure_st, _index, _field ) | \ - MLX_MASK_3 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_MASK_5( _structure_st, _index, _field, ... ) \ - ( MLX_MASK_1 ( _structure_st, _index, _field ) | \ - MLX_MASK_4 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_MASK_6( _structure_st, _index, _field, ... ) \ - ( MLX_MASK_1 ( _structure_st, _index, _field ) | \ - MLX_MASK_5 ( _structure_st, _index, __VA_ARGS__ ) ) - -#define MLX_MASK_7( _structure_st, _index, _field, ... ) \ - ( MLX_MASK_1 ( _structure_st, _index, _field ) | \ - MLX_MASK_6 ( _structure_st, _index, __VA_ARGS__ ) ) - -/* - * Populate big-endian dwords from named fields and values - * - */ - -#define MLX_FILL( _ptr, _index, _assembled ) \ - do { \ - uint32_t *__ptr = &(_ptr)->u.dwords[(_index)]; \ - uint32_t __assembled = (_assembled); \ - *__ptr = cpu_to_be32 ( __assembled ); \ - } while ( 0 ) - -#define MLX_FILL_1( _ptr, _index, ... ) \ - MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_1 ( MLX_PSEUDO_STRUCT ( _ptr ),\ - _index, __VA_ARGS__ ) ) - -#define MLX_FILL_2( _ptr, _index, ... ) \ - MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_2 ( MLX_PSEUDO_STRUCT ( _ptr ),\ - _index, __VA_ARGS__ ) ) - -#define MLX_FILL_3( _ptr, _index, ... ) \ - MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_3 ( MLX_PSEUDO_STRUCT ( _ptr ),\ - _index, __VA_ARGS__ ) ) - -#define MLX_FILL_4( _ptr, _index, ... ) \ - MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_4 ( MLX_PSEUDO_STRUCT ( _ptr ),\ - _index, __VA_ARGS__ ) ) - -#define MLX_FILL_5( _ptr, _index, ... ) \ - MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_5 ( MLX_PSEUDO_STRUCT ( _ptr ),\ - _index, __VA_ARGS__ ) ) - -#define MLX_FILL_6( _ptr, _index, ... ) \ - MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_6 ( MLX_PSEUDO_STRUCT ( _ptr ),\ - _index, __VA_ARGS__ ) ) - -#define MLX_FILL_7( _ptr, _index, ... ) \ - MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_7 ( MLX_PSEUDO_STRUCT ( _ptr ),\ - _index, __VA_ARGS__ ) ) - -/* - * Modify big-endian dword using named field and value - * - */ - -#define MLX_SET( _ptr, _field, _value ) \ - do { \ - unsigned int __index = \ - MLX_DWORD_OFFSET ( MLX_PSEUDO_STRUCT ( _ptr ), _field ); \ - uint32_t *__ptr = &(_ptr)->u.dwords[__index]; \ - uint32_t __value = be32_to_cpu ( *__ptr ); \ - __value &= ~( MLX_MASK_1 ( MLX_PSEUDO_STRUCT ( _ptr ), \ - __index, _field ) ); \ - __value |= MLX_ASSEMBLE_1 ( MLX_PSEUDO_STRUCT ( _ptr ), \ - __index, _field, _value ); \ - *__ptr = cpu_to_be32 ( __value ); \ - } while ( 0 ) - -/* - * Extract value of named field - * - */ - -#define MLX_GET( _ptr, _field ) \ - ( { \ - unsigned int __index = \ - MLX_DWORD_OFFSET ( MLX_PSEUDO_STRUCT ( _ptr ), _field ); \ - uint32_t *__ptr = &(_ptr)->u.dwords[__index]; \ - uint32_t __value = be32_to_cpu ( *__ptr ); \ - __value >>= \ - MLX_DWORD_BIT_OFFSET ( MLX_PSEUDO_STRUCT ( _ptr ), \ - __index, _field ); \ - __value &= \ - MLX_BIT_MASK ( MLX_PSEUDO_STRUCT ( _ptr ), _field ); \ - __value; \ - } ) - -#endif /* _MLX_BITOPS_H */ diff --git a/gpxe/src/drivers/infiniband/qib_7220_regs.h b/gpxe/src/drivers/infiniband/qib_7220_regs.h deleted file mode 100644 index 0637ec80..00000000 --- a/gpxe/src/drivers/infiniband/qib_7220_regs.h +++ /dev/null @@ -1,1762 +0,0 @@ -/* - * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved. - * - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * OpenIB.org BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - */ -/* This file is mechanically generated from RTL. Any hand-edits will be lost! */ - -/* This file has been further processed by ./drivers/infiniband/qib_genbits.pl */ - -FILE_LICENCE ( GPL2_ONLY ); - -#define QIB_7220_Revision_offset 0x00000000UL -struct QIB_7220_Revision_pb { - pseudo_bit_t R_ChipRevMinor[8]; - pseudo_bit_t R_ChipRevMajor[8]; - pseudo_bit_t R_Arch[8]; - pseudo_bit_t R_SW[8]; - pseudo_bit_t BoardID[8]; - pseudo_bit_t R_Emulation_Revcode[22]; - pseudo_bit_t R_Emulation[1]; - pseudo_bit_t R_Simulator[1]; -}; -struct QIB_7220_Revision { - PSEUDO_BIT_STRUCT ( struct QIB_7220_Revision_pb ); -}; - -#define QIB_7220_Control_offset 0x00000008UL -struct QIB_7220_Control_pb { - pseudo_bit_t SyncReset[1]; - pseudo_bit_t FreezeMode[1]; - pseudo_bit_t LinkEn[1]; - pseudo_bit_t PCIERetryBufDiagEn[1]; - pseudo_bit_t TxLatency[1]; - pseudo_bit_t Reserved[1]; - pseudo_bit_t PCIECplQDiagEn[1]; - pseudo_bit_t SyncResetExceptPcieIRAMRST[1]; - pseudo_bit_t _unused_0[56]; -}; -struct QIB_7220_Control { - PSEUDO_BIT_STRUCT ( struct QIB_7220_Control_pb ); -}; - -#define QIB_7220_PageAlign_offset 0x00000010UL - -#define QIB_7220_PortCnt_offset 0x00000018UL - -#define QIB_7220_DbgPortSel_offset 0x00000020UL -struct QIB_7220_DbgPortSel_pb { - pseudo_bit_t NibbleSel0[4]; - pseudo_bit_t NibbleSel1[4]; - pseudo_bit_t NibbleSel2[4]; - pseudo_bit_t NibbleSel3[4]; - pseudo_bit_t NibbleSel4[4]; - pseudo_bit_t NibbleSel5[4]; - pseudo_bit_t NibbleSel6[4]; - pseudo_bit_t NibbleSel7[4]; - pseudo_bit_t SrcMuxSel[14]; - pseudo_bit_t DbgClkPortSel[5]; - pseudo_bit_t EnDbgPort[1]; - pseudo_bit_t EnEnhancedDebugMode[1]; - pseudo_bit_t EnhMode_SrcMuxSelIndex[10]; - pseudo_bit_t EnhMode_SrcMuxSelWrEn[1]; -}; -struct QIB_7220_DbgPortSel { - PSEUDO_BIT_STRUCT ( struct QIB_7220_DbgPortSel_pb ); -}; - -#define QIB_7220_DebugSigsIntSel_offset 0x00000028UL -struct QIB_7220_DebugSigsIntSel_pb { - pseudo_bit_t debug_port_sel_pcs_pipe_lane07[3]; - pseudo_bit_t debug_port_sel_pcs_pipe_lane815[3]; - pseudo_bit_t debug_port_sel_pcs_sdout[1]; - pseudo_bit_t debug_port_sel_pcs_symlock_elfifo_lane[4]; - pseudo_bit_t debug_port_sel_pcs_rxdet_encdec_lane[4]; - pseudo_bit_t debug_port_sel_pcie_rx_tx[1]; - pseudo_bit_t debug_port_sel_xgxs[4]; - pseudo_bit_t debug_port_sel_epb_pcie[1]; - pseudo_bit_t _unused_0[43]; -}; -struct QIB_7220_DebugSigsIntSel { - PSEUDO_BIT_STRUCT ( struct QIB_7220_DebugSigsIntSel_pb ); -}; - -#define QIB_7220_SendRegBase_offset 0x00000030UL - -#define QIB_7220_UserRegBase_offset 0x00000038UL - -#define QIB_7220_CntrRegBase_offset 0x00000040UL - -#define QIB_7220_Scratch_offset 0x00000048UL - -#define QIB_7220_REG_000050_offset 0x00000050UL - -#define QIB_7220_IntBlocked_offset 0x00000060UL -struct QIB_7220_IntBlocked_pb { - pseudo_bit_t RcvAvail0IntBlocked[1]; - pseudo_bit_t RcvAvail1IntBlocked[1]; - pseudo_bit_t RcvAvail2IntBlocked[1]; - pseudo_bit_t RcvAvail3IntBlocked[1]; - pseudo_bit_t RcvAvail4IntBlocked[1]; - pseudo_bit_t RcvAvail5IntBlocked[1]; - pseudo_bit_t RcvAvail6IntBlocked[1]; - pseudo_bit_t RcvAvail7IntBlocked[1]; - pseudo_bit_t RcvAvail8IntBlocked[1]; - pseudo_bit_t RcvAvail9IntBlocked[1]; - pseudo_bit_t RcvAvail10IntBlocked[1]; - pseudo_bit_t RcvAvail11IntBlocked[1]; - pseudo_bit_t RcvAvail12IntBlocked[1]; - pseudo_bit_t RcvAvail13IntBlocked[1]; - pseudo_bit_t RcvAvail14IntBlocked[1]; - pseudo_bit_t RcvAvail15IntBlocked[1]; - pseudo_bit_t RcvAvail16IntBlocked[1]; - pseudo_bit_t Reserved1[9]; - pseudo_bit_t JIntBlocked[1]; - pseudo_bit_t IBSerdesTrimDoneIntBlocked[1]; - pseudo_bit_t assertGPIOIntBlocked[1]; - pseudo_bit_t PioBufAvailIntBlocked[1]; - pseudo_bit_t PioSetIntBlocked[1]; - pseudo_bit_t ErrorIntBlocked[1]; - pseudo_bit_t RcvUrg0IntBlocked[1]; - pseudo_bit_t RcvUrg1IntBlocked[1]; - pseudo_bit_t RcvUrg2IntBlocked[1]; - pseudo_bit_t RcvUrg3IntBlocked[1]; - pseudo_bit_t RcvUrg4IntBlocked[1]; - pseudo_bit_t RcvUrg5IntBlocked[1]; - pseudo_bit_t RcvUrg6IntBlocked[1]; - pseudo_bit_t RcvUrg7IntBlocked[1]; - pseudo_bit_t RcvUrg8IntBlocked[1]; - pseudo_bit_t RcvUrg9IntBlocked[1]; - pseudo_bit_t RcvUrg10IntBlocked[1]; - pseudo_bit_t RcvUrg11IntBlocked[1]; - pseudo_bit_t RcvUrg12IntBlocked[1]; - pseudo_bit_t RcvUrg13IntBlocked[1]; - pseudo_bit_t RcvUrg14IntBlocked[1]; - pseudo_bit_t RcvUrg15IntBlocked[1]; - pseudo_bit_t RcvUrg16IntBlocked[1]; - pseudo_bit_t Reserved[13]; - pseudo_bit_t SDmaDisabledBlocked[1]; - pseudo_bit_t SDmaIntBlocked[1]; -}; -struct QIB_7220_IntBlocked { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IntBlocked_pb ); -}; - -#define QIB_7220_IntMask_offset 0x00000068UL -struct QIB_7220_IntMask_pb { - pseudo_bit_t RcvAvail0IntMask[1]; - pseudo_bit_t RcvAvail1IntMask[1]; - pseudo_bit_t RcvAvail2IntMask[1]; - pseudo_bit_t RcvAvail3IntMask[1]; - pseudo_bit_t RcvAvail4IntMask[1]; - pseudo_bit_t RcvAvail5IntMask[1]; - pseudo_bit_t RcvAvail6IntMask[1]; - pseudo_bit_t RcvAvail7IntMask[1]; - pseudo_bit_t RcvAvail8IntMask[1]; - pseudo_bit_t RcvAvail9IntMask[1]; - pseudo_bit_t RcvAvail10IntMask[1]; - pseudo_bit_t RcvAvail11IntMask[1]; - pseudo_bit_t RcvAvail12IntMask[1]; - pseudo_bit_t RcvAvail13IntMask[1]; - pseudo_bit_t RcvAvail14IntMask[1]; - pseudo_bit_t RcvAvail15IntMask[1]; - pseudo_bit_t RcvAvail16IntMask[1]; - pseudo_bit_t Reserved1[9]; - pseudo_bit_t JIntMask[1]; - pseudo_bit_t IBSerdesTrimDoneIntMask[1]; - pseudo_bit_t assertGPIOIntMask[1]; - pseudo_bit_t PioBufAvailIntMask[1]; - pseudo_bit_t PioSetIntMask[1]; - pseudo_bit_t ErrorIntMask[1]; - pseudo_bit_t RcvUrg0IntMask[1]; - pseudo_bit_t RcvUrg1IntMask[1]; - pseudo_bit_t RcvUrg2IntMask[1]; - pseudo_bit_t RcvUrg3IntMask[1]; - pseudo_bit_t RcvUrg4IntMask[1]; - pseudo_bit_t RcvUrg5IntMask[1]; - pseudo_bit_t RcvUrg6IntMask[1]; - pseudo_bit_t RcvUrg7IntMask[1]; - pseudo_bit_t RcvUrg8IntMask[1]; - pseudo_bit_t RcvUrg9IntMask[1]; - pseudo_bit_t RcvUrg10IntMask[1]; - pseudo_bit_t RcvUrg11IntMask[1]; - pseudo_bit_t RcvUrg12IntMask[1]; - pseudo_bit_t RcvUrg13IntMask[1]; - pseudo_bit_t RcvUrg14IntMask[1]; - pseudo_bit_t RcvUrg15IntMask[1]; - pseudo_bit_t RcvUrg16IntMask[1]; - pseudo_bit_t Reserved[13]; - pseudo_bit_t SDmaDisabledMasked[1]; - pseudo_bit_t SDmaIntMask[1]; -}; -struct QIB_7220_IntMask { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IntMask_pb ); -}; - -#define QIB_7220_IntStatus_offset 0x00000070UL -struct QIB_7220_IntStatus_pb { - pseudo_bit_t RcvAvail0[1]; - pseudo_bit_t RcvAvail1[1]; - pseudo_bit_t RcvAvail2[1]; - pseudo_bit_t RcvAvail3[1]; - pseudo_bit_t RcvAvail4[1]; - pseudo_bit_t RcvAvail5[1]; - pseudo_bit_t RcvAvail6[1]; - pseudo_bit_t RcvAvail7[1]; - pseudo_bit_t RcvAvail8[1]; - pseudo_bit_t RcvAvail9[1]; - pseudo_bit_t RcvAvail10[1]; - pseudo_bit_t RcvAvail11[1]; - pseudo_bit_t RcvAvail12[1]; - pseudo_bit_t RcvAvail13[1]; - pseudo_bit_t RcvAvail14[1]; - pseudo_bit_t RcvAvail15[1]; - pseudo_bit_t RcvAvail16[1]; - pseudo_bit_t Reserved1[9]; - pseudo_bit_t JInt[1]; - pseudo_bit_t IBSerdesTrimDone[1]; - pseudo_bit_t assertGPIO[1]; - pseudo_bit_t PioBufAvail[1]; - pseudo_bit_t PioSent[1]; - pseudo_bit_t Error[1]; - pseudo_bit_t RcvUrg0[1]; - pseudo_bit_t RcvUrg1[1]; - pseudo_bit_t RcvUrg2[1]; - pseudo_bit_t RcvUrg3[1]; - pseudo_bit_t RcvUrg4[1]; - pseudo_bit_t RcvUrg5[1]; - pseudo_bit_t RcvUrg6[1]; - pseudo_bit_t RcvUrg7[1]; - pseudo_bit_t RcvUrg8[1]; - pseudo_bit_t RcvUrg9[1]; - pseudo_bit_t RcvUrg10[1]; - pseudo_bit_t RcvUrg11[1]; - pseudo_bit_t RcvUrg12[1]; - pseudo_bit_t RcvUrg13[1]; - pseudo_bit_t RcvUrg14[1]; - pseudo_bit_t RcvUrg15[1]; - pseudo_bit_t RcvUrg16[1]; - pseudo_bit_t Reserved[13]; - pseudo_bit_t SDmaDisabled[1]; - pseudo_bit_t SDmaInt[1]; -}; -struct QIB_7220_IntStatus { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IntStatus_pb ); -}; - -#define QIB_7220_IntClear_offset 0x00000078UL -struct QIB_7220_IntClear_pb { - pseudo_bit_t RcvAvail0IntClear[1]; - pseudo_bit_t RcvAvail1IntClear[1]; - pseudo_bit_t RcvAvail2IntClear[1]; - pseudo_bit_t RcvAvail3IntClear[1]; - pseudo_bit_t RcvAvail4IntClear[1]; - pseudo_bit_t RcvAvail5IntClear[1]; - pseudo_bit_t RcvAvail6IntClear[1]; - pseudo_bit_t RcvAvail7IntClear[1]; - pseudo_bit_t RcvAvail8IntClear[1]; - pseudo_bit_t RcvAvail9IntClear[1]; - pseudo_bit_t RcvAvail10IntClear[1]; - pseudo_bit_t RcvAvail11IntClear[1]; - pseudo_bit_t RcvAvail12IntClear[1]; - pseudo_bit_t RcvAvail13IntClear[1]; - pseudo_bit_t RcvAvail14IntClear[1]; - pseudo_bit_t RcvAvail15IntClear[1]; - pseudo_bit_t RcvAvail16IntClear[1]; - pseudo_bit_t Reserved1[9]; - pseudo_bit_t JIntClear[1]; - pseudo_bit_t IBSerdesTrimDoneClear[1]; - pseudo_bit_t assertGPIOIntClear[1]; - pseudo_bit_t PioBufAvailIntClear[1]; - pseudo_bit_t PioSetIntClear[1]; - pseudo_bit_t ErrorIntClear[1]; - pseudo_bit_t RcvUrg0IntClear[1]; - pseudo_bit_t RcvUrg1IntClear[1]; - pseudo_bit_t RcvUrg2IntClear[1]; - pseudo_bit_t RcvUrg3IntClear[1]; - pseudo_bit_t RcvUrg4IntClear[1]; - pseudo_bit_t RcvUrg5IntClear[1]; - pseudo_bit_t RcvUrg6IntClear[1]; - pseudo_bit_t RcvUrg7IntClear[1]; - pseudo_bit_t RcvUrg8IntClear[1]; - pseudo_bit_t RcvUrg9IntClear[1]; - pseudo_bit_t RcvUrg10IntClear[1]; - pseudo_bit_t RcvUrg11IntClear[1]; - pseudo_bit_t RcvUrg12IntClear[1]; - pseudo_bit_t RcvUrg13IntClear[1]; - pseudo_bit_t RcvUrg14IntClear[1]; - pseudo_bit_t RcvUrg15IntClear[1]; - pseudo_bit_t RcvUrg16IntClear[1]; - pseudo_bit_t Reserved[13]; - pseudo_bit_t SDmaDisabledClear[1]; - pseudo_bit_t SDmaIntClear[1]; -}; -struct QIB_7220_IntClear { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IntClear_pb ); -}; - -#define QIB_7220_ErrMask_offset 0x00000080UL -struct QIB_7220_ErrMask_pb { - pseudo_bit_t RcvFormatErrMask[1]; - pseudo_bit_t RcvVCRCErrMask[1]; - pseudo_bit_t RcvICRCErrMask[1]; - pseudo_bit_t RcvMinPktLenErrMask[1]; - pseudo_bit_t RcvMaxPktLenErrMask[1]; - pseudo_bit_t RcvLongPktLenErrMask[1]; - pseudo_bit_t RcvShortPktLenErrMask[1]; - pseudo_bit_t RcvUnexpectedCharErrMask[1]; - pseudo_bit_t RcvUnsupportedVLErrMask[1]; - pseudo_bit_t RcvEBPErrMask[1]; - pseudo_bit_t RcvIBFlowErrMask[1]; - pseudo_bit_t RcvBadVersionErrMask[1]; - pseudo_bit_t RcvEgrFullErrMask[1]; - pseudo_bit_t RcvHdrFullErrMask[1]; - pseudo_bit_t RcvBadTidErrMask[1]; - pseudo_bit_t RcvHdrLenErrMask[1]; - pseudo_bit_t RcvHdrErrMask[1]; - pseudo_bit_t RcvIBLostLinkErrMask[1]; - pseudo_bit_t Reserved1[9]; - pseudo_bit_t SendSpecialTriggerErrMask[1]; - pseudo_bit_t SDmaDisabledErrMask[1]; - pseudo_bit_t SendMinPktLenErrMask[1]; - pseudo_bit_t SendMaxPktLenErrMask[1]; - pseudo_bit_t SendUnderRunErrMask[1]; - pseudo_bit_t SendPktLenErrMask[1]; - pseudo_bit_t SendDroppedSmpPktErrMask[1]; - pseudo_bit_t SendDroppedDataPktErrMask[1]; - pseudo_bit_t SendPioArmLaunchErrMask[1]; - pseudo_bit_t SendUnexpectedPktNumErrMask[1]; - pseudo_bit_t SendUnsupportedVLErrMask[1]; - pseudo_bit_t SendBufMisuseErrMask[1]; - pseudo_bit_t SDmaGenMismatchErrMask[1]; - pseudo_bit_t SDmaOutOfBoundErrMask[1]; - pseudo_bit_t SDmaTailOutOfBoundErrMask[1]; - pseudo_bit_t SDmaBaseErrMask[1]; - pseudo_bit_t SDma1stDescErrMask[1]; - pseudo_bit_t SDmaRpyTagErrMask[1]; - pseudo_bit_t SDmaDwEnErrMask[1]; - pseudo_bit_t SDmaMissingDwErrMask[1]; - pseudo_bit_t SDmaUnexpDataErrMask[1]; - pseudo_bit_t IBStatusChangedMask[1]; - pseudo_bit_t InvalidAddrErrMask[1]; - pseudo_bit_t ResetNegatedMask[1]; - pseudo_bit_t HardwareErrMask[1]; - pseudo_bit_t SDmaDescAddrMisalignErrMask[1]; - pseudo_bit_t InvalidEEPCmdMask[1]; - pseudo_bit_t Reserved[10]; -}; -struct QIB_7220_ErrMask { - PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrMask_pb ); -}; - -#define QIB_7220_ErrStatus_offset 0x00000088UL -struct QIB_7220_ErrStatus_pb { - pseudo_bit_t RcvFormatErr[1]; - pseudo_bit_t RcvVCRCErr[1]; - pseudo_bit_t RcvICRCErr[1]; - pseudo_bit_t RcvMinPktLenErr[1]; - pseudo_bit_t RcvMaxPktLenErr[1]; - pseudo_bit_t RcvLongPktLenErr[1]; - pseudo_bit_t RcvShortPktLenErr[1]; - pseudo_bit_t RcvUnexpectedCharErr[1]; - pseudo_bit_t RcvUnsupportedVLErr[1]; - pseudo_bit_t RcvEBPErr[1]; - pseudo_bit_t RcvIBFlowErr[1]; - pseudo_bit_t RcvBadVersionErr[1]; - pseudo_bit_t RcvEgrFullErr[1]; - pseudo_bit_t RcvHdrFullErr[1]; - pseudo_bit_t RcvBadTidErr[1]; - pseudo_bit_t RcvHdrLenErr[1]; - pseudo_bit_t RcvHdrErr[1]; - pseudo_bit_t RcvIBLostLinkErr[1]; - pseudo_bit_t Reserved1[9]; - pseudo_bit_t SendSpecialTriggerErr[1]; - pseudo_bit_t SDmaDisabledErr[1]; - pseudo_bit_t SendMinPktLenErr[1]; - pseudo_bit_t SendMaxPktLenErr[1]; - pseudo_bit_t SendUnderRunErr[1]; - pseudo_bit_t SendPktLenErr[1]; - pseudo_bit_t SendDroppedSmpPktErr[1]; - pseudo_bit_t SendDroppedDataPktErr[1]; - pseudo_bit_t SendPioArmLaunchErr[1]; - pseudo_bit_t SendUnexpectedPktNumErr[1]; - pseudo_bit_t SendUnsupportedVLErr[1]; - pseudo_bit_t SendBufMisuseErr[1]; - pseudo_bit_t SDmaGenMismatchErr[1]; - pseudo_bit_t SDmaOutOfBoundErr[1]; - pseudo_bit_t SDmaTailOutOfBoundErr[1]; - pseudo_bit_t SDmaBaseErr[1]; - pseudo_bit_t SDma1stDescErr[1]; - pseudo_bit_t SDmaRpyTagErr[1]; - pseudo_bit_t SDmaDwEnErr[1]; - pseudo_bit_t SDmaMissingDwErr[1]; - pseudo_bit_t SDmaUnexpDataErr[1]; - pseudo_bit_t IBStatusChanged[1]; - pseudo_bit_t InvalidAddrErr[1]; - pseudo_bit_t ResetNegated[1]; - pseudo_bit_t HardwareErr[1]; - pseudo_bit_t SDmaDescAddrMisalignErr[1]; - pseudo_bit_t InvalidEEPCmdErr[1]; - pseudo_bit_t Reserved[10]; -}; -struct QIB_7220_ErrStatus { - PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrStatus_pb ); -}; - -#define QIB_7220_ErrClear_offset 0x00000090UL -struct QIB_7220_ErrClear_pb { - pseudo_bit_t RcvFormatErrClear[1]; - pseudo_bit_t RcvVCRCErrClear[1]; - pseudo_bit_t RcvICRCErrClear[1]; - pseudo_bit_t RcvMinPktLenErrClear[1]; - pseudo_bit_t RcvMaxPktLenErrClear[1]; - pseudo_bit_t RcvLongPktLenErrClear[1]; - pseudo_bit_t RcvShortPktLenErrClear[1]; - pseudo_bit_t RcvUnexpectedCharErrClear[1]; - pseudo_bit_t RcvUnsupportedVLErrClear[1]; - pseudo_bit_t RcvEBPErrClear[1]; - pseudo_bit_t RcvIBFlowErrClear[1]; - pseudo_bit_t RcvBadVersionErrClear[1]; - pseudo_bit_t RcvEgrFullErrClear[1]; - pseudo_bit_t RcvHdrFullErrClear[1]; - pseudo_bit_t RcvBadTidErrClear[1]; - pseudo_bit_t RcvHdrLenErrClear[1]; - pseudo_bit_t RcvHdrErrClear[1]; - pseudo_bit_t RcvIBLostLinkErrClear[1]; - pseudo_bit_t Reserved1[9]; - pseudo_bit_t SendSpecialTriggerErrClear[1]; - pseudo_bit_t SDmaDisabledErrClear[1]; - pseudo_bit_t SendMinPktLenErrClear[1]; - pseudo_bit_t SendMaxPktLenErrClear[1]; - pseudo_bit_t SendUnderRunErrClear[1]; - pseudo_bit_t SendPktLenErrClear[1]; - pseudo_bit_t SendDroppedSmpPktErrClear[1]; - pseudo_bit_t SendDroppedDataPktErrClear[1]; - pseudo_bit_t SendPioArmLaunchErrClear[1]; - pseudo_bit_t SendUnexpectedPktNumErrClear[1]; - pseudo_bit_t SendUnsupportedVLErrClear[1]; - pseudo_bit_t SendBufMisuseErrClear[1]; - pseudo_bit_t SDmaGenMismatchErrClear[1]; - pseudo_bit_t SDmaOutOfBoundErrClear[1]; - pseudo_bit_t SDmaTailOutOfBoundErrClear[1]; - pseudo_bit_t SDmaBaseErrClear[1]; - pseudo_bit_t SDma1stDescErrClear[1]; - pseudo_bit_t SDmaRpyTagErrClear[1]; - pseudo_bit_t SDmaDwEnErrClear[1]; - pseudo_bit_t SDmaMissingDwErrClear[1]; - pseudo_bit_t SDmaUnexpDataErrClear[1]; - pseudo_bit_t IBStatusChangedClear[1]; - pseudo_bit_t InvalidAddrErrClear[1]; - pseudo_bit_t ResetNegatedClear[1]; - pseudo_bit_t HardwareErrClear[1]; - pseudo_bit_t SDmaDescAddrMisalignErrClear[1]; - pseudo_bit_t InvalidEEPCmdErrClear[1]; - pseudo_bit_t Reserved[10]; -}; -struct QIB_7220_ErrClear { - PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrClear_pb ); -}; - -#define QIB_7220_HwErrMask_offset 0x00000098UL -struct QIB_7220_HwErrMask_pb { - pseudo_bit_t PCIeMemParityErrMask[8]; - pseudo_bit_t Reserved3[20]; - pseudo_bit_t SDmaMemReadErrMask[1]; - pseudo_bit_t PoisonedTLPMask[1]; - pseudo_bit_t PcieCplTimeoutMask[1]; - pseudo_bit_t PCIeBusParityErrMask[3]; - pseudo_bit_t Reserved2[2]; - pseudo_bit_t PCIEOct0_uC_MemoryParityErrMask[1]; - pseudo_bit_t PCIEOct1_uC_MemoryParityErrMask[1]; - pseudo_bit_t IB_uC_MemoryParityErrMask[1]; - pseudo_bit_t DDSRXEQMemoryParityErrMask[1]; - pseudo_bit_t TXEMemParityErrMask[4]; - pseudo_bit_t RXEMemParityErrMask[7]; - pseudo_bit_t Reserved1[3]; - pseudo_bit_t PowerOnBISTFailedMask[1]; - pseudo_bit_t Reserved[1]; - pseudo_bit_t PCIESerdesQ0PClkNotDetectMask[1]; - pseudo_bit_t PCIESerdesQ1PClkNotDetectMask[1]; - pseudo_bit_t PCIESerdesQ2PClkNotDetectMask[1]; - pseudo_bit_t PCIESerdesQ3PClkNotDetectMask[1]; - pseudo_bit_t IBSerdesPClkNotDetectMask[1]; - pseudo_bit_t Clk_uC_PLLNotLockedMask[1]; - pseudo_bit_t IBCBusToSPCParityErrMask[1]; - pseudo_bit_t IBCBusFromSPCParityErrMask[1]; -}; -struct QIB_7220_HwErrMask { - PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrMask_pb ); -}; - -#define QIB_7220_HwErrStatus_offset 0x000000a0UL -struct QIB_7220_HwErrStatus_pb { - pseudo_bit_t PCIeMemParity[8]; - pseudo_bit_t Reserved3[20]; - pseudo_bit_t SDmaMemReadErr[1]; - pseudo_bit_t PoisenedTLP[1]; - pseudo_bit_t PcieCplTimeout[1]; - pseudo_bit_t PCIeBusParity[3]; - pseudo_bit_t Reserved2[2]; - pseudo_bit_t PCIE_uC_Oct0MemoryParityErr[1]; - pseudo_bit_t PCIE_uC_Oct1MemoryParityErr[1]; - pseudo_bit_t IB_uC_MemoryParityErr[1]; - pseudo_bit_t DDSRXEQMemoryParityErr[1]; - pseudo_bit_t TXEMemParity[4]; - pseudo_bit_t RXEMemParity[7]; - pseudo_bit_t Reserved1[3]; - pseudo_bit_t PowerOnBISTFailed[1]; - pseudo_bit_t Reserved[1]; - pseudo_bit_t PCIESerdesQ0PClkNotDetect[1]; - pseudo_bit_t PCIESerdesQ1PClkNotDetect[1]; - pseudo_bit_t PCIESerdesQ2PClkNotDetect[1]; - pseudo_bit_t PCIESerdesQ3PClkNotDetect[1]; - pseudo_bit_t IBSerdesPClkNotDetect[1]; - pseudo_bit_t Clk_uC_PLLNotLocked[1]; - pseudo_bit_t IBCBusToSPCParityErr[1]; - pseudo_bit_t IBCBusFromSPCParityErr[1]; -}; -struct QIB_7220_HwErrStatus { - PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrStatus_pb ); -}; - -#define QIB_7220_HwErrClear_offset 0x000000a8UL -struct QIB_7220_HwErrClear_pb { - pseudo_bit_t PCIeMemParityClr[8]; - pseudo_bit_t Reserved3[20]; - pseudo_bit_t SDmaMemReadErrClear[1]; - pseudo_bit_t PoisonedTLPClear[1]; - pseudo_bit_t PcieCplTimeoutClear[1]; - pseudo_bit_t PCIeBusParityClr[3]; - pseudo_bit_t Reserved2[2]; - pseudo_bit_t PCIE_uC_Oct0MemoryParityErrClear[1]; - pseudo_bit_t PCIE_uC_Oct1MemoryParityErrClear[1]; - pseudo_bit_t IB_uC_MemoryParityErrClear[1]; - pseudo_bit_t DDSRXEQMemoryParityErrClear[1]; - pseudo_bit_t TXEMemParityClear[4]; - pseudo_bit_t RXEMemParityClear[7]; - pseudo_bit_t Reserved1[3]; - pseudo_bit_t PowerOnBISTFailedClear[1]; - pseudo_bit_t Reserved[1]; - pseudo_bit_t PCIESerdesQ0PClkNotDetectClear[1]; - pseudo_bit_t PCIESerdesQ1PClkNotDetectClear[1]; - pseudo_bit_t PCIESerdesQ2PClkNotDetectClear[1]; - pseudo_bit_t PCIESerdesQ3PClkNotDetectClear[1]; - pseudo_bit_t IBSerdesPClkNotDetectClear[1]; - pseudo_bit_t Clk_uC_PLLNotLockedClear[1]; - pseudo_bit_t IBCBusToSPCparityErrClear[1]; - pseudo_bit_t IBCBusFromSPCParityErrClear[1]; -}; -struct QIB_7220_HwErrClear { - PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrClear_pb ); -}; - -#define QIB_7220_HwDiagCtrl_offset 0x000000b0UL -struct QIB_7220_HwDiagCtrl_pb { - pseudo_bit_t forcePCIeMemParity[8]; - pseudo_bit_t Reserved2[23]; - pseudo_bit_t forcePCIeBusParity[4]; - pseudo_bit_t Reserved1[1]; - pseudo_bit_t ForcePCIE_uC_Oct0MemoryParityErr[1]; - pseudo_bit_t ForcePCIE_uC_Oct1MemoryParityErr[1]; - pseudo_bit_t ForceIB_uC_MemoryParityErr[1]; - pseudo_bit_t ForceDDSRXEQMemoryParityErr[1]; - pseudo_bit_t ForceTxMemparityErr[4]; - pseudo_bit_t ForceRxMemParityErr[7]; - pseudo_bit_t Reserved[9]; - pseudo_bit_t CounterDisable[1]; - pseudo_bit_t CounterWrEnable[1]; - pseudo_bit_t ForceIBCBusToSPCParityErr[1]; - pseudo_bit_t ForceIBCBusFromSPCParityErr[1]; -}; -struct QIB_7220_HwDiagCtrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_HwDiagCtrl_pb ); -}; - -#define QIB_7220_REG_0000B8_offset 0x000000b8UL - -#define QIB_7220_IBCStatus_offset 0x000000c0UL -struct QIB_7220_IBCStatus_pb { - pseudo_bit_t LinkTrainingState[5]; - pseudo_bit_t LinkState[3]; - pseudo_bit_t LinkSpeedActive[1]; - pseudo_bit_t LinkWidthActive[1]; - pseudo_bit_t DDS_RXEQ_FAIL[1]; - pseudo_bit_t IB_SERDES_TRIM_DONE[1]; - pseudo_bit_t IBRxLaneReversed[1]; - pseudo_bit_t IBTxLaneReversed[1]; - pseudo_bit_t Reserved[16]; - pseudo_bit_t TxReady[1]; - pseudo_bit_t TxCreditOk[1]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_IBCStatus { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCStatus_pb ); -}; - -#define QIB_7220_IBCCtrl_offset 0x000000c8UL -struct QIB_7220_IBCCtrl_pb { - pseudo_bit_t FlowCtrlPeriod[8]; - pseudo_bit_t FlowCtrlWaterMark[8]; - pseudo_bit_t LinkInitCmd[3]; - pseudo_bit_t LinkCmd[2]; - pseudo_bit_t MaxPktLen[11]; - pseudo_bit_t PhyerrThreshold[4]; - pseudo_bit_t OverrunThreshold[4]; - pseudo_bit_t CreditScale[3]; - pseudo_bit_t Reserved[19]; - pseudo_bit_t LinkDownDefaultState[1]; - pseudo_bit_t Loopback[1]; -}; -struct QIB_7220_IBCCtrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCCtrl_pb ); -}; - -#define QIB_7220_EXTStatus_offset 0x000000d0UL -struct QIB_7220_EXTStatus_pb { - pseudo_bit_t Reserved2[14]; - pseudo_bit_t MemBISTEndTest[1]; - pseudo_bit_t MemBISTDisabled[1]; - pseudo_bit_t Reserved1[16]; - pseudo_bit_t Reserved[16]; - pseudo_bit_t GPIOIn[16]; -}; -struct QIB_7220_EXTStatus { - PSEUDO_BIT_STRUCT ( struct QIB_7220_EXTStatus_pb ); -}; - -#define QIB_7220_EXTCtrl_offset 0x000000d8UL -struct QIB_7220_EXTCtrl_pb { - pseudo_bit_t LEDGblErrRedOff[1]; - pseudo_bit_t LEDGblOkGreenOn[1]; - pseudo_bit_t LEDPriPortYellowOn[1]; - pseudo_bit_t LEDPriPortGreenOn[1]; - pseudo_bit_t Reserved[28]; - pseudo_bit_t GPIOInvert[16]; - pseudo_bit_t GPIOOe[16]; -}; -struct QIB_7220_EXTCtrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_EXTCtrl_pb ); -}; - -#define QIB_7220_GPIOOut_offset 0x000000e0UL - -#define QIB_7220_GPIOMask_offset 0x000000e8UL - -#define QIB_7220_GPIOStatus_offset 0x000000f0UL - -#define QIB_7220_GPIOClear_offset 0x000000f8UL - -#define QIB_7220_RcvCtrl_offset 0x00000100UL -struct QIB_7220_RcvCtrl_pb { - pseudo_bit_t PortEnable[17]; - pseudo_bit_t IntrAvail[17]; - pseudo_bit_t RcvPartitionKeyDisable[1]; - pseudo_bit_t TailUpd[1]; - pseudo_bit_t PortCfg[2]; - pseudo_bit_t RcvQPMapEnable[1]; - pseudo_bit_t Reserved[25]; -}; -struct QIB_7220_RcvCtrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvCtrl_pb ); -}; - -#define QIB_7220_RcvBTHQP_offset 0x00000108UL -struct QIB_7220_RcvBTHQP_pb { - pseudo_bit_t RcvBTHQP[24]; - pseudo_bit_t Reserved[8]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_RcvBTHQP { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvBTHQP_pb ); -}; - -#define QIB_7220_RcvHdrSize_offset 0x00000110UL - -#define QIB_7220_RcvHdrCnt_offset 0x00000118UL - -#define QIB_7220_RcvHdrEntSize_offset 0x00000120UL - -#define QIB_7220_RcvTIDBase_offset 0x00000128UL - -#define QIB_7220_RcvTIDCnt_offset 0x00000130UL - -#define QIB_7220_RcvEgrBase_offset 0x00000138UL - -#define QIB_7220_RcvEgrCnt_offset 0x00000140UL - -#define QIB_7220_RcvBufBase_offset 0x00000148UL - -#define QIB_7220_RcvBufSize_offset 0x00000150UL - -#define QIB_7220_RxIntMemBase_offset 0x00000158UL - -#define QIB_7220_RxIntMemSize_offset 0x00000160UL - -#define QIB_7220_RcvPartitionKey_offset 0x00000168UL - -#define QIB_7220_RcvQPMulticastPort_offset 0x00000170UL -struct QIB_7220_RcvQPMulticastPort_pb { - pseudo_bit_t RcvQpMcPort[5]; - pseudo_bit_t Reserved[59]; -}; -struct QIB_7220_RcvQPMulticastPort { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvQPMulticastPort_pb ); -}; - -#define QIB_7220_RcvPktLEDCnt_offset 0x00000178UL -struct QIB_7220_RcvPktLEDCnt_pb { - pseudo_bit_t OFFperiod[32]; - pseudo_bit_t ONperiod[32]; -}; -struct QIB_7220_RcvPktLEDCnt { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvPktLEDCnt_pb ); -}; - -#define QIB_7220_IBCDDRCtrl_offset 0x00000180UL -struct QIB_7220_IBCDDRCtrl_pb { - pseudo_bit_t IB_ENHANCED_MODE[1]; - pseudo_bit_t SD_SPEED[1]; - pseudo_bit_t SD_SPEED_SDR[1]; - pseudo_bit_t SD_SPEED_DDR[1]; - pseudo_bit_t SD_SPEED_QDR[1]; - pseudo_bit_t IB_NUM_CHANNELS[2]; - pseudo_bit_t IB_POLARITY_REV_SUPP[1]; - pseudo_bit_t IB_LANE_REV_SUPPORTED[1]; - pseudo_bit_t SD_RX_EQUAL_ENABLE[1]; - pseudo_bit_t SD_ADD_ENB[1]; - pseudo_bit_t SD_DDSV[1]; - pseudo_bit_t SD_DDS[4]; - pseudo_bit_t HRTBT_ENB[1]; - pseudo_bit_t HRTBT_AUTO[1]; - pseudo_bit_t HRTBT_PORT[8]; - pseudo_bit_t HRTBT_REQ[1]; - pseudo_bit_t Reserved[5]; - pseudo_bit_t IB_DLID[16]; - pseudo_bit_t IB_DLID_MASK[16]; -}; -struct QIB_7220_IBCDDRCtrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRCtrl_pb ); -}; - -#define QIB_7220_HRTBT_GUID_offset 0x00000188UL - -#define QIB_7220_IB_SDTEST_IF_TX_offset 0x00000190UL -struct QIB_7220_IB_SDTEST_IF_TX_pb { - pseudo_bit_t TS_T_TX_VALID[1]; - pseudo_bit_t TS_3_TX_VALID[1]; - pseudo_bit_t Reserved1[9]; - pseudo_bit_t TS_TX_OPCODE[2]; - pseudo_bit_t TS_TX_SPEED[3]; - pseudo_bit_t Reserved[16]; - pseudo_bit_t TS_TX_TX_CFG[16]; - pseudo_bit_t TS_TX_RX_CFG[16]; -}; -struct QIB_7220_IB_SDTEST_IF_TX { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IB_SDTEST_IF_TX_pb ); -}; - -#define QIB_7220_IB_SDTEST_IF_RX_offset 0x00000198UL -struct QIB_7220_IB_SDTEST_IF_RX_pb { - pseudo_bit_t TS_T_RX_VALID[1]; - pseudo_bit_t TS_3_RX_VALID[1]; - pseudo_bit_t Reserved[14]; - pseudo_bit_t TS_RX_A[8]; - pseudo_bit_t TS_RX_B[8]; - pseudo_bit_t TS_RX_TX_CFG[16]; - pseudo_bit_t TS_RX_RX_CFG[16]; -}; -struct QIB_7220_IB_SDTEST_IF_RX { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IB_SDTEST_IF_RX_pb ); -}; - -#define QIB_7220_IBCDDRCtrl2_offset 0x000001a0UL -struct QIB_7220_IBCDDRCtrl2_pb { - pseudo_bit_t IB_FRONT_PORCH[5]; - pseudo_bit_t IB_BACK_PORCH[5]; - pseudo_bit_t _unused_0[54]; -}; -struct QIB_7220_IBCDDRCtrl2 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRCtrl2_pb ); -}; - -#define QIB_7220_IBCDDRStatus_offset 0x000001a8UL -struct QIB_7220_IBCDDRStatus_pb { - pseudo_bit_t LinkRoundTripLatency[26]; - pseudo_bit_t ReqDDSLocalFromRmt[4]; - pseudo_bit_t RxEqLocalDevice[2]; - pseudo_bit_t heartbeat_crosstalk[4]; - pseudo_bit_t heartbeat_timed_out[1]; - pseudo_bit_t _unused_0[27]; -}; -struct QIB_7220_IBCDDRStatus { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRStatus_pb ); -}; - -#define QIB_7220_JIntReload_offset 0x000001b0UL -struct QIB_7220_JIntReload_pb { - pseudo_bit_t J_reload[16]; - pseudo_bit_t J_limit_reload[16]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_JIntReload { - PSEUDO_BIT_STRUCT ( struct QIB_7220_JIntReload_pb ); -}; - -#define QIB_7220_IBNCModeCtrl_offset 0x000001b8UL -struct QIB_7220_IBNCModeCtrl_pb { - pseudo_bit_t TSMEnable_send_TS1[1]; - pseudo_bit_t TSMEnable_send_TS2[1]; - pseudo_bit_t TSMEnable_ignore_TSM_on_rx[1]; - pseudo_bit_t Reserved1[5]; - pseudo_bit_t TSMCode_TS1[9]; - pseudo_bit_t TSMCode_TS2[9]; - pseudo_bit_t Reserved[38]; -}; -struct QIB_7220_IBNCModeCtrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IBNCModeCtrl_pb ); -}; - -#define QIB_7220_SendCtrl_offset 0x000001c0UL -struct QIB_7220_SendCtrl_pb { - pseudo_bit_t Abort[1]; - pseudo_bit_t SendIntBufAvail[1]; - pseudo_bit_t SendBufAvailUpd[1]; - pseudo_bit_t SPioEnable[1]; - pseudo_bit_t SSpecialTriggerEn[1]; - pseudo_bit_t Reserved2[4]; - pseudo_bit_t SDmaIntEnable[1]; - pseudo_bit_t SDmaSingleDescriptor[1]; - pseudo_bit_t SDmaEnable[1]; - pseudo_bit_t SDmaHalt[1]; - pseudo_bit_t Reserved1[3]; - pseudo_bit_t DisarmPIOBuf[8]; - pseudo_bit_t AvailUpdThld[5]; - pseudo_bit_t Reserved[2]; - pseudo_bit_t Disarm[1]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_SendCtrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendCtrl_pb ); -}; - -#define QIB_7220_SendBufBase_offset 0x000001c8UL -struct QIB_7220_SendBufBase_pb { - pseudo_bit_t BaseAddr_SmallPIO[21]; - pseudo_bit_t Reserved1[11]; - pseudo_bit_t BaseAddr_LargePIO[21]; - pseudo_bit_t Reserved[11]; -}; -struct QIB_7220_SendBufBase { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufBase_pb ); -}; - -#define QIB_7220_SendBufSize_offset 0x000001d0UL -struct QIB_7220_SendBufSize_pb { - pseudo_bit_t Size_SmallPIO[12]; - pseudo_bit_t Reserved1[20]; - pseudo_bit_t Size_LargePIO[13]; - pseudo_bit_t Reserved[19]; -}; -struct QIB_7220_SendBufSize { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufSize_pb ); -}; - -#define QIB_7220_SendBufCnt_offset 0x000001d8UL -struct QIB_7220_SendBufCnt_pb { - pseudo_bit_t Num_SmallBuffers[9]; - pseudo_bit_t Reserved1[23]; - pseudo_bit_t Num_LargeBuffers[4]; - pseudo_bit_t Reserved[28]; -}; -struct QIB_7220_SendBufCnt { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufCnt_pb ); -}; - -#define QIB_7220_SendBufAvailAddr_offset 0x000001e0UL -struct QIB_7220_SendBufAvailAddr_pb { - pseudo_bit_t Reserved[6]; - pseudo_bit_t SendBufAvailAddr[34]; - pseudo_bit_t _unused_0[24]; -}; -struct QIB_7220_SendBufAvailAddr { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvailAddr_pb ); -}; - -#define QIB_7220_TxIntMemBase_offset 0x000001e8UL - -#define QIB_7220_TxIntMemSize_offset 0x000001f0UL - -#define QIB_7220_SendDmaBase_offset 0x000001f8UL -struct QIB_7220_SendDmaBase_pb { - pseudo_bit_t SendDmaBase[48]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_SendDmaBase { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBase_pb ); -}; - -#define QIB_7220_SendDmaLenGen_offset 0x00000200UL -struct QIB_7220_SendDmaLenGen_pb { - pseudo_bit_t Length[16]; - pseudo_bit_t Generation[3]; - pseudo_bit_t Reserved[45]; -}; -struct QIB_7220_SendDmaLenGen { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaLenGen_pb ); -}; - -#define QIB_7220_SendDmaTail_offset 0x00000208UL -struct QIB_7220_SendDmaTail_pb { - pseudo_bit_t SendDmaTail[16]; - pseudo_bit_t Reserved[48]; -}; -struct QIB_7220_SendDmaTail { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaTail_pb ); -}; - -#define QIB_7220_SendDmaHead_offset 0x00000210UL -struct QIB_7220_SendDmaHead_pb { - pseudo_bit_t SendDmaHead[16]; - pseudo_bit_t Reserved1[16]; - pseudo_bit_t InternalSendDmaHead[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_SendDmaHead { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaHead_pb ); -}; - -#define QIB_7220_SendDmaHeadAddr_offset 0x00000218UL -struct QIB_7220_SendDmaHeadAddr_pb { - pseudo_bit_t SendDmaHeadAddr[48]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_SendDmaHeadAddr { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaHeadAddr_pb ); -}; - -#define QIB_7220_SendDmaBufMask0_offset 0x00000220UL -struct QIB_7220_SendDmaBufMask0_pb { - pseudo_bit_t BufMask_63_0[0]; - pseudo_bit_t _unused_0[64]; -}; -struct QIB_7220_SendDmaBufMask0 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBufMask0_pb ); -}; - -#define QIB_7220_SendDmaStatus_offset 0x00000238UL -struct QIB_7220_SendDmaStatus_pb { - pseudo_bit_t SplFifoDescIndex[16]; - pseudo_bit_t SplFifoBufNum[8]; - pseudo_bit_t SplFifoFull[1]; - pseudo_bit_t SplFifoEmpty[1]; - pseudo_bit_t SplFifoDisarmed[1]; - pseudo_bit_t SplFifoReadyToGo[1]; - pseudo_bit_t ScbFetchDescFlag[1]; - pseudo_bit_t ScbEntryValid[1]; - pseudo_bit_t ScbEmpty[1]; - pseudo_bit_t ScbFull[1]; - pseudo_bit_t RpyTag_7_0[8]; - pseudo_bit_t RpyLowAddr_6_0[7]; - pseudo_bit_t ScbDescIndex_13_0[14]; - pseudo_bit_t InternalSDmaEnable[1]; - pseudo_bit_t AbortInProg[1]; - pseudo_bit_t ScoreBoardDrainInProg[1]; -}; -struct QIB_7220_SendDmaStatus { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaStatus_pb ); -}; - -#define QIB_7220_SendBufErr0_offset 0x00000240UL -struct QIB_7220_SendBufErr0_pb { - pseudo_bit_t SendBufErr_63_0[0]; - pseudo_bit_t _unused_0[64]; -}; -struct QIB_7220_SendBufErr0 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufErr0_pb ); -}; - -#define QIB_7220_REG_000258_offset 0x00000258UL - -#define QIB_7220_AvailUpdCount_offset 0x00000268UL -struct QIB_7220_AvailUpdCount_pb { - pseudo_bit_t AvailUpdCount[5]; - pseudo_bit_t _unused_0[59]; -}; -struct QIB_7220_AvailUpdCount { - PSEUDO_BIT_STRUCT ( struct QIB_7220_AvailUpdCount_pb ); -}; - -#define QIB_7220_RcvHdrAddr0_offset 0x00000270UL -struct QIB_7220_RcvHdrAddr0_pb { - pseudo_bit_t Reserved[2]; - pseudo_bit_t RcvHdrAddr0[38]; - pseudo_bit_t _unused_0[24]; -}; -struct QIB_7220_RcvHdrAddr0 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrAddr0_pb ); -}; - -#define QIB_7220_REG_0002F8_offset 0x000002f8UL - -#define QIB_7220_RcvHdrTailAddr0_offset 0x00000300UL -struct QIB_7220_RcvHdrTailAddr0_pb { - pseudo_bit_t Reserved[2]; - pseudo_bit_t RcvHdrTailAddr0[38]; - pseudo_bit_t _unused_0[24]; -}; -struct QIB_7220_RcvHdrTailAddr0 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrTailAddr0_pb ); -}; - -#define QIB_7220_REG_000388_offset 0x00000388UL - -#define QIB_7220_ibsd_epb_access_ctrl_offset 0x000003c0UL -struct QIB_7220_ibsd_epb_access_ctrl_pb { - pseudo_bit_t sw_ib_epb_req[1]; - pseudo_bit_t Reserved[7]; - pseudo_bit_t sw_ib_epb_req_granted[1]; - pseudo_bit_t _unused_0[55]; -}; -struct QIB_7220_ibsd_epb_access_ctrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_ibsd_epb_access_ctrl_pb ); -}; - -#define QIB_7220_ibsd_epb_transaction_reg_offset 0x000003c8UL -struct QIB_7220_ibsd_epb_transaction_reg_pb { - pseudo_bit_t ib_epb_data[8]; - pseudo_bit_t ib_epb_address[15]; - pseudo_bit_t Reserved2[1]; - pseudo_bit_t ib_epb_read_write[1]; - pseudo_bit_t ib_epb_cs[2]; - pseudo_bit_t Reserved1[1]; - pseudo_bit_t mem_data_parity[1]; - pseudo_bit_t Reserved[1]; - pseudo_bit_t ib_epb_req_error[1]; - pseudo_bit_t ib_epb_rdy[1]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_ibsd_epb_transaction_reg { - PSEUDO_BIT_STRUCT ( struct QIB_7220_ibsd_epb_transaction_reg_pb ); -}; - -#define QIB_7220_REG_0003D0_offset 0x000003d0UL - -#define QIB_7220_XGXSCfg_offset 0x000003d8UL -struct QIB_7220_XGXSCfg_pb { - pseudo_bit_t tx_rx_reset[1]; - pseudo_bit_t Reserved2[1]; - pseudo_bit_t xcv_reset[1]; - pseudo_bit_t Reserved1[6]; - pseudo_bit_t link_sync_mask[10]; - pseudo_bit_t Reserved[44]; - pseudo_bit_t sel_link_down_for_fctrl_lane_sync_reset[1]; -}; -struct QIB_7220_XGXSCfg { - PSEUDO_BIT_STRUCT ( struct QIB_7220_XGXSCfg_pb ); -}; - -#define QIB_7220_IBSerDesCtrl_offset 0x000003e0UL -struct QIB_7220_IBSerDesCtrl_pb { - pseudo_bit_t ResetIB_uC_Core[1]; - pseudo_bit_t Reserved2[7]; - pseudo_bit_t NumSerDesRegsToWrForDDS[5]; - pseudo_bit_t NumSerDesRegsToWrForRXEQ[5]; - pseudo_bit_t Reserved1[14]; - pseudo_bit_t TXINV[1]; - pseudo_bit_t RXINV[1]; - pseudo_bit_t RXIDLE[1]; - pseudo_bit_t TWC[1]; - pseudo_bit_t TXOBPD[1]; - pseudo_bit_t PLLM[3]; - pseudo_bit_t PLLN[2]; - pseudo_bit_t CKSEL_uC[2]; - pseudo_bit_t INT_uC[1]; - pseudo_bit_t Reserved[19]; -}; -struct QIB_7220_IBSerDesCtrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_IBSerDesCtrl_pb ); -}; - -#define QIB_7220_EEPCtlStat_offset 0x000003e8UL -struct QIB_7220_EEPCtlStat_pb { - pseudo_bit_t EPAccEn[2]; - pseudo_bit_t EPReset[1]; - pseudo_bit_t ByteProg[1]; - pseudo_bit_t PageMode[1]; - pseudo_bit_t LstDatWr[1]; - pseudo_bit_t CmdWrErr[1]; - pseudo_bit_t Reserved[24]; - pseudo_bit_t CtlrStat[1]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_EEPCtlStat { - PSEUDO_BIT_STRUCT ( struct QIB_7220_EEPCtlStat_pb ); -}; - -#define QIB_7220_EEPAddrCmd_offset 0x000003f0UL -struct QIB_7220_EEPAddrCmd_pb { - pseudo_bit_t EPAddr[24]; - pseudo_bit_t EPCmd[8]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_EEPAddrCmd { - PSEUDO_BIT_STRUCT ( struct QIB_7220_EEPAddrCmd_pb ); -}; - -#define QIB_7220_EEPData_offset 0x000003f8UL - -#define QIB_7220_pciesd_epb_access_ctrl_offset 0x00000400UL -struct QIB_7220_pciesd_epb_access_ctrl_pb { - pseudo_bit_t sw_pcie_epb_req[1]; - pseudo_bit_t sw_pcieepb_star_en[2]; - pseudo_bit_t Reserved[5]; - pseudo_bit_t sw_pcie_epb_req_granted[1]; - pseudo_bit_t _unused_0[55]; -}; -struct QIB_7220_pciesd_epb_access_ctrl { - PSEUDO_BIT_STRUCT ( struct QIB_7220_pciesd_epb_access_ctrl_pb ); -}; - -#define QIB_7220_pciesd_epb_transaction_reg_offset 0x00000408UL -struct QIB_7220_pciesd_epb_transaction_reg_pb { - pseudo_bit_t pcie_epb_data[8]; - pseudo_bit_t pcie_epb_address[15]; - pseudo_bit_t Reserved1[1]; - pseudo_bit_t pcie_epb_read_write[1]; - pseudo_bit_t pcie_epb_cs[3]; - pseudo_bit_t mem_data_parity[1]; - pseudo_bit_t Reserved[1]; - pseudo_bit_t pcie_epb_req_error[1]; - pseudo_bit_t pcie_epb_rdy[1]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_pciesd_epb_transaction_reg { - PSEUDO_BIT_STRUCT ( struct QIB_7220_pciesd_epb_transaction_reg_pb ); -}; - -#define QIB_7220_efuse_control_reg_offset 0x00000410UL -struct QIB_7220_efuse_control_reg_pb { - pseudo_bit_t start_op[1]; - pseudo_bit_t operation[1]; - pseudo_bit_t read_valid[1]; - pseudo_bit_t req_error[1]; - pseudo_bit_t Reserved[27]; - pseudo_bit_t rdy[1]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_efuse_control_reg { - PSEUDO_BIT_STRUCT ( struct QIB_7220_efuse_control_reg_pb ); -}; - -#define QIB_7220_efuse_rddata0_reg_offset 0x00000418UL - -#define QIB_7220_procmon_register_offset 0x00000438UL -struct QIB_7220_procmon_register_pb { - pseudo_bit_t interval_time[12]; - pseudo_bit_t Reserved1[2]; - pseudo_bit_t clear_counter[1]; - pseudo_bit_t start_counter[1]; - pseudo_bit_t procmon_count[9]; - pseudo_bit_t Reserved[6]; - pseudo_bit_t procmon_count_valid[1]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_procmon_register { - PSEUDO_BIT_STRUCT ( struct QIB_7220_procmon_register_pb ); -}; - -#define QIB_7220_PcieRbufTestReg0_offset 0x00000440UL - -#define QIB_7220_PcieRBufTestReg1_offset 0x00000448UL - -#define QIB_7220_SPC_JTAG_ACCESS_REG_offset 0x00000460UL -struct QIB_7220_SPC_JTAG_ACCESS_REG_pb { - pseudo_bit_t rdy[1]; - pseudo_bit_t tdo[1]; - pseudo_bit_t tdi[1]; - pseudo_bit_t opcode[2]; - pseudo_bit_t bist_en[5]; - pseudo_bit_t SPC_JTAG_ACCESS_EN[1]; - pseudo_bit_t _unused_0[53]; -}; -struct QIB_7220_SPC_JTAG_ACCESS_REG { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SPC_JTAG_ACCESS_REG_pb ); -}; - -#define QIB_7220_LAControlReg_offset 0x00000468UL -struct QIB_7220_LAControlReg_pb { - pseudo_bit_t Finished[1]; - pseudo_bit_t Address[8]; - pseudo_bit_t Mode[2]; - pseudo_bit_t Delay[20]; - pseudo_bit_t Reserved[1]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_LAControlReg { - PSEUDO_BIT_STRUCT ( struct QIB_7220_LAControlReg_pb ); -}; - -#define QIB_7220_GPIODebugSelReg_offset 0x00000470UL -struct QIB_7220_GPIODebugSelReg_pb { - pseudo_bit_t GPIOSourceSelDebug[16]; - pseudo_bit_t SelPulse[16]; - pseudo_bit_t _unused_0[32]; -}; -struct QIB_7220_GPIODebugSelReg { - PSEUDO_BIT_STRUCT ( struct QIB_7220_GPIODebugSelReg_pb ); -}; - -#define QIB_7220_DebugPortValueReg_offset 0x00000478UL - -#define QIB_7220_SendDmaBufUsed0_offset 0x00000480UL -struct QIB_7220_SendDmaBufUsed0_pb { - pseudo_bit_t BufUsed_63_0[0]; - pseudo_bit_t _unused_0[64]; -}; -struct QIB_7220_SendDmaBufUsed0 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBufUsed0_pb ); -}; - -#define QIB_7220_SendDmaReqTagUsed_offset 0x00000498UL -struct QIB_7220_SendDmaReqTagUsed_pb { - pseudo_bit_t ReqTagUsed_7_0[8]; - pseudo_bit_t _unused_0[8]; - pseudo_bit_t Reserved[48]; -}; -struct QIB_7220_SendDmaReqTagUsed { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaReqTagUsed_pb ); -}; - -#define QIB_7220_efuse_pgm_data0_offset 0x000004a0UL - -#define QIB_7220_MEM_0004B0_offset 0x000004b0UL - -#define QIB_7220_SerDes_DDSRXEQ0_offset 0x00000500UL -struct QIB_7220_SerDes_DDSRXEQ0_pb { - pseudo_bit_t element_num[4]; - pseudo_bit_t reg_addr[6]; - pseudo_bit_t _unused_0[54]; -}; -struct QIB_7220_SerDes_DDSRXEQ0 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SerDes_DDSRXEQ0_pb ); -}; - -#define QIB_7220_MEM_0005F0_offset 0x000005f0UL - -#define QIB_7220_LAMemory_offset 0x00000600UL - -#define QIB_7220_MEM_0007F0_offset 0x000007f0UL - -#define QIB_7220_SendBufAvail0_offset 0x00001000UL -struct QIB_7220_SendBufAvail0_pb { - pseudo_bit_t SendBuf_31_0[0]; - pseudo_bit_t _unused_0[64]; -}; -struct QIB_7220_SendBufAvail0 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvail0_pb ); -}; - -#define QIB_7220_MEM_001028_offset 0x00001028UL - -#define QIB_7220_LBIntCnt_offset 0x00013000UL - -#define QIB_7220_LBFlowStallCnt_offset 0x00013008UL - -#define QIB_7220_TxSDmaDescCnt_offset 0x00013010UL - -#define QIB_7220_TxUnsupVLErrCnt_offset 0x00013018UL - -#define QIB_7220_TxDataPktCnt_offset 0x00013020UL - -#define QIB_7220_TxFlowPktCnt_offset 0x00013028UL - -#define QIB_7220_TxDwordCnt_offset 0x00013030UL - -#define QIB_7220_TxLenErrCnt_offset 0x00013038UL - -#define QIB_7220_TxMaxMinLenErrCnt_offset 0x00013040UL - -#define QIB_7220_TxUnderrunCnt_offset 0x00013048UL - -#define QIB_7220_TxFlowStallCnt_offset 0x00013050UL - -#define QIB_7220_TxDroppedPktCnt_offset 0x00013058UL - -#define QIB_7220_RxDroppedPktCnt_offset 0x00013060UL - -#define QIB_7220_RxDataPktCnt_offset 0x00013068UL - -#define QIB_7220_RxFlowPktCnt_offset 0x00013070UL - -#define QIB_7220_RxDwordCnt_offset 0x00013078UL - -#define QIB_7220_RxLenErrCnt_offset 0x00013080UL - -#define QIB_7220_RxMaxMinLenErrCnt_offset 0x00013088UL - -#define QIB_7220_RxICRCErrCnt_offset 0x00013090UL - -#define QIB_7220_RxVCRCErrCnt_offset 0x00013098UL - -#define QIB_7220_RxFlowCtrlViolCnt_offset 0x000130a0UL - -#define QIB_7220_RxVersionErrCnt_offset 0x000130a8UL - -#define QIB_7220_RxLinkMalformCnt_offset 0x000130b0UL - -#define QIB_7220_RxEBPCnt_offset 0x000130b8UL - -#define QIB_7220_RxLPCRCErrCnt_offset 0x000130c0UL - -#define QIB_7220_RxBufOvflCnt_offset 0x000130c8UL - -#define QIB_7220_RxTIDFullErrCnt_offset 0x000130d0UL - -#define QIB_7220_RxTIDValidErrCnt_offset 0x000130d8UL - -#define QIB_7220_RxPKeyMismatchCnt_offset 0x000130e0UL - -#define QIB_7220_RxP0HdrEgrOvflCnt_offset 0x000130e8UL - -#define QIB_7220_IBStatusChangeCnt_offset 0x00013170UL - -#define QIB_7220_IBLinkErrRecoveryCnt_offset 0x00013178UL - -#define QIB_7220_IBLinkDownedCnt_offset 0x00013180UL - -#define QIB_7220_IBSymbolErrCnt_offset 0x00013188UL - -#define QIB_7220_RxVL15DroppedPktCnt_offset 0x00013190UL - -#define QIB_7220_RxOtherLocalPhyErrCnt_offset 0x00013198UL - -#define QIB_7220_PcieRetryBufDiagQwordCnt_offset 0x000131a0UL - -#define QIB_7220_ExcessBufferOvflCnt_offset 0x000131a8UL - -#define QIB_7220_LocalLinkIntegrityErrCnt_offset 0x000131b0UL - -#define QIB_7220_RxVlErrCnt_offset 0x000131b8UL - -#define QIB_7220_RxDlidFltrCnt_offset 0x000131c0UL - -#define QIB_7220_CNT_0131C8_offset 0x000131c8UL - -#define QIB_7220_PSStat_offset 0x00013200UL - -#define QIB_7220_PSStart_offset 0x00013208UL - -#define QIB_7220_PSInterval_offset 0x00013210UL - -#define QIB_7220_PSRcvDataCount_offset 0x00013218UL - -#define QIB_7220_PSRcvPktsCount_offset 0x00013220UL - -#define QIB_7220_PSXmitDataCount_offset 0x00013228UL - -#define QIB_7220_PSXmitPktsCount_offset 0x00013230UL - -#define QIB_7220_PSXmitWaitCount_offset 0x00013238UL - -#define QIB_7220_CNT_013240_offset 0x00013240UL - -#define QIB_7220_RcvEgrArray_offset 0x00014000UL - -#define QIB_7220_MEM_038000_offset 0x00038000UL - -#define QIB_7220_RcvTIDArray0_offset 0x00053000UL - -#define QIB_7220_PIOLaunchFIFO_offset 0x00064000UL - -#define QIB_7220_MEM_064480_offset 0x00064480UL - -#define QIB_7220_SendPIOpbcCache_offset 0x00064800UL - -#define QIB_7220_MEM_064C80_offset 0x00064c80UL - -#define QIB_7220_PreLaunchFIFO_offset 0x00065000UL - -#define QIB_7220_MEM_065080_offset 0x00065080UL - -#define QIB_7220_ScoreBoard_offset 0x00065400UL - -#define QIB_7220_MEM_065440_offset 0x00065440UL - -#define QIB_7220_DescriptorFIFO_offset 0x00065800UL - -#define QIB_7220_MEM_065880_offset 0x00065880UL - -#define QIB_7220_RcvBuf1_offset 0x00072000UL - -#define QIB_7220_MEM_074800_offset 0x00074800UL - -#define QIB_7220_RcvBuf2_offset 0x00075000UL - -#define QIB_7220_MEM_076400_offset 0x00076400UL - -#define QIB_7220_RcvFlags_offset 0x00077000UL - -#define QIB_7220_MEM_078400_offset 0x00078400UL - -#define QIB_7220_RcvLookupBuf1_offset 0x00079000UL - -#define QIB_7220_MEM_07A400_offset 0x0007a400UL - -#define QIB_7220_RcvDMADatBuf_offset 0x0007b000UL - -#define QIB_7220_RcvDMAHdrBuf_offset 0x0007b800UL - -#define QIB_7220_MiscRXEIntMem_offset 0x0007c000UL - -#define QIB_7220_MEM_07D400_offset 0x0007d400UL - -#define QIB_7220_PCIERcvBuf_offset 0x00080000UL - -#define QIB_7220_PCIERetryBuf_offset 0x00084000UL - -#define QIB_7220_PCIERcvBufRdToWrAddr_offset 0x00088000UL - -#define QIB_7220_PCIECplBuf_offset 0x00090000UL - -#define QIB_7220_IBSerDesMappTable_offset 0x00094000UL - -#define QIB_7220_MEM_095000_offset 0x00095000UL - -#define QIB_7220_SendBuf0_MA_offset 0x00100000UL - -#define QIB_7220_MEM_1A0000_offset 0x001a0000UL - -#define QIB_7220_RcvHdrTail0_offset 0x00200000UL - -#define QIB_7220_RcvHdrHead0_offset 0x00200008UL -struct QIB_7220_RcvHdrHead0_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead0 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead0_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail0_offset 0x00200010UL - -#define QIB_7220_RcvEgrIndexHead0_offset 0x00200018UL - -#define QIB_7220_MEM_200020_offset 0x00200020UL - -#define QIB_7220_RcvHdrTail1_offset 0x00210000UL - -#define QIB_7220_RcvHdrHead1_offset 0x00210008UL -struct QIB_7220_RcvHdrHead1_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead1 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead1_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail1_offset 0x00210010UL - -#define QIB_7220_RcvEgrIndexHead1_offset 0x00210018UL - -#define QIB_7220_MEM_210020_offset 0x00210020UL - -#define QIB_7220_RcvHdrTail2_offset 0x00220000UL - -#define QIB_7220_RcvHdrHead2_offset 0x00220008UL -struct QIB_7220_RcvHdrHead2_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead2 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead2_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail2_offset 0x00220010UL - -#define QIB_7220_RcvEgrIndexHead2_offset 0x00220018UL - -#define QIB_7220_MEM_220020_offset 0x00220020UL - -#define QIB_7220_RcvHdrTail3_offset 0x00230000UL - -#define QIB_7220_RcvHdrHead3_offset 0x00230008UL -struct QIB_7220_RcvHdrHead3_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead3 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead3_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail3_offset 0x00230010UL - -#define QIB_7220_RcvEgrIndexHead3_offset 0x00230018UL - -#define QIB_7220_MEM_230020_offset 0x00230020UL - -#define QIB_7220_RcvHdrTail4_offset 0x00240000UL - -#define QIB_7220_RcvHdrHead4_offset 0x00240008UL -struct QIB_7220_RcvHdrHead4_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead4 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead4_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail4_offset 0x00240010UL - -#define QIB_7220_RcvEgrIndexHead4_offset 0x00240018UL - -#define QIB_7220_MEM_240020_offset 0x00240020UL - -#define QIB_7220_RcvHdrTail5_offset 0x00250000UL - -#define QIB_7220_RcvHdrHead5_offset 0x00250008UL -struct QIB_7220_RcvHdrHead5_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead5 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead5_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail5_offset 0x00250010UL - -#define QIB_7220_RcvEgrIndexHead5_offset 0x00250018UL - -#define QIB_7220_MEM_250020_offset 0x00250020UL - -#define QIB_7220_RcvHdrTail6_offset 0x00260000UL - -#define QIB_7220_RcvHdrHead6_offset 0x00260008UL -struct QIB_7220_RcvHdrHead6_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead6 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead6_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail6_offset 0x00260010UL - -#define QIB_7220_RcvEgrIndexHead6_offset 0x00260018UL - -#define QIB_7220_MEM_260020_offset 0x00260020UL - -#define QIB_7220_RcvHdrTail7_offset 0x00270000UL - -#define QIB_7220_RcvHdrHead7_offset 0x00270008UL -struct QIB_7220_RcvHdrHead7_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead7 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead7_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail7_offset 0x00270010UL - -#define QIB_7220_RcvEgrIndexHead7_offset 0x00270018UL - -#define QIB_7220_MEM_270020_offset 0x00270020UL - -#define QIB_7220_RcvHdrTail8_offset 0x00280000UL - -#define QIB_7220_RcvHdrHead8_offset 0x00280008UL -struct QIB_7220_RcvHdrHead8_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead8 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead8_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail8_offset 0x00280010UL - -#define QIB_7220_RcvEgrIndexHead8_offset 0x00280018UL - -#define QIB_7220_MEM_280020_offset 0x00280020UL - -#define QIB_7220_RcvHdrTail9_offset 0x00290000UL - -#define QIB_7220_RcvHdrHead9_offset 0x00290008UL -struct QIB_7220_RcvHdrHead9_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead9 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead9_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail9_offset 0x00290010UL - -#define QIB_7220_RcvEgrIndexHead9_offset 0x00290018UL - -#define QIB_7220_MEM_290020_offset 0x00290020UL - -#define QIB_7220_RcvHdrTail10_offset 0x002a0000UL - -#define QIB_7220_RcvHdrHead10_offset 0x002a0008UL -struct QIB_7220_RcvHdrHead10_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead10 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead10_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail10_offset 0x002a0010UL - -#define QIB_7220_RcvEgrIndexHead10_offset 0x002a0018UL - -#define QIB_7220_MEM_2A0020_offset 0x002a0020UL - -#define QIB_7220_RcvHdrTail11_offset 0x002b0000UL - -#define QIB_7220_RcvHdrHead11_offset 0x002b0008UL -struct QIB_7220_RcvHdrHead11_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead11 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead11_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail11_offset 0x002b0010UL - -#define QIB_7220_RcvEgrIndexHead11_offset 0x002b0018UL - -#define QIB_7220_MEM_2B0020_offset 0x002b0020UL - -#define QIB_7220_RcvHdrTail12_offset 0x002c0000UL - -#define QIB_7220_RcvHdrHead12_offset 0x002c0008UL -struct QIB_7220_RcvHdrHead12_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead12 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead12_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail12_offset 0x002c0010UL - -#define QIB_7220_RcvEgrIndexHead12_offset 0x002c0018UL - -#define QIB_7220_MEM_2C0020_offset 0x002c0020UL - -#define QIB_7220_RcvHdrTail13_offset 0x002d0000UL - -#define QIB_7220_RcvHdrHead13_offset 0x002d0008UL -struct QIB_7220_RcvHdrHead13_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead13 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead13_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail13_offset 0x002d0010UL - -#define QIB_7220_RcvEgrIndexHead13_offset 0x002d0018UL - -#define QIB_7220_MEM_2D0020_offset 0x002d0020UL - -#define QIB_7220_RcvHdrTail14_offset 0x002e0000UL - -#define QIB_7220_RcvHdrHead14_offset 0x002e0008UL -struct QIB_7220_RcvHdrHead14_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead14 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead14_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail14_offset 0x002e0010UL - -#define QIB_7220_RcvEgrIndexHead14_offset 0x002e0018UL - -#define QIB_7220_MEM_2E0020_offset 0x002e0020UL - -#define QIB_7220_RcvHdrTail15_offset 0x002f0000UL - -#define QIB_7220_RcvHdrHead15_offset 0x002f0008UL -struct QIB_7220_RcvHdrHead15_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead15 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead15_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail15_offset 0x002f0010UL - -#define QIB_7220_RcvEgrIndexHead15_offset 0x002f0018UL - -#define QIB_7220_MEM_2F0020_offset 0x002f0020UL - -#define QIB_7220_RcvHdrTail16_offset 0x00300000UL - -#define QIB_7220_RcvHdrHead16_offset 0x00300008UL -struct QIB_7220_RcvHdrHead16_pb { - pseudo_bit_t RcvHeadPointer[32]; - pseudo_bit_t counter[16]; - pseudo_bit_t Reserved[16]; -}; -struct QIB_7220_RcvHdrHead16 { - PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead16_pb ); -}; - -#define QIB_7220_RcvEgrIndexTail16_offset 0x00300010UL - -#define QIB_7220_RcvEgrIndexHead16_offset 0x00300018UL - -#define QIB_7220_MEM_300020_offset 0x00300020UL - diff --git a/gpxe/src/drivers/infiniband/qib_genbits.pl b/gpxe/src/drivers/infiniband/qib_genbits.pl deleted file mode 100755 index 1d5eeded..00000000 --- a/gpxe/src/drivers/infiniband/qib_genbits.pl +++ /dev/null @@ -1,116 +0,0 @@ -#!/usr/bin/perl -w -# -# Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of the -# License, or any later version. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - -use strict; -use warnings; - -my $offsets = {}; -my $defaults = {}; -my $structures = {}; -my $structure = ""; - -while ( <> ) { - chomp; - if ( /^\#define (\S+)_OFFS (\S+)$/ ) { - $structure = $1; - $offsets->{$structure} = $2; - } elsif ( /^\#define ${structure}_DEF (\S+)$/ ) { - $defaults->{$structure} = $1; - } elsif ( /^\#define ${structure}_(\S+)_LSB (\S+)$/ ) { - $structures->{$structure}->{$1}->{LSB} = $2; - } elsif ( /^\#define ${structure}_(\S+)_MSB (\S+)$/ ) { - $structures->{$structure}->{$1}->{MSB} = $2; - } elsif ( /^\#define ${structure}_(\S+)_RMASK (\S+)$/ ) { - $structures->{$structure}->{$1}->{RMASK} = $2; - } elsif ( /^\s*$/ ) { - # Do nothing - } else { - print "$_\n"; - } -} - -my $data = [ map { { name => $_, offset => $offsets->{$_}, - default => $defaults->{$_} }; } - sort { hex ( $offsets->{$a} ) <=> hex ( $offsets->{$b} ) } - keys %$offsets ]; - -foreach my $datum ( @$data ) { - next unless exists $structures->{$datum->{name}}; - $structure = $structures->{$datum->{name}}; - my $fields = [ map { { name => $_, lsb => $structure->{$_}->{LSB}, - msb => $structure->{$_}->{MSB}, - rmask => $structure->{$_}->{RMASK} }; } - sort { hex ( $structure->{$a}->{LSB} ) <=> - hex ( $structure->{$b}->{LSB} ) } - keys %$structure ]; - $datum->{fields} = $fields; -} - -print "\n/* This file has been further processed by $0 */\n\n"; -print "FILE_LICENCE ( GPL2_ONLY );\n\n"; - -foreach my $datum ( @$data ) { - printf "#define %s_offset 0x%08xUL\n", - $datum->{name}, hex ( $datum->{offset} ); - if ( exists $datum->{fields} ) { - my $lsb = 0; - my $reserved_idx = 0; - printf "struct %s_pb {\n", $datum->{name}; - foreach my $field ( @{$datum->{fields}} ) { - my $pad_width = ( hex ( $field->{lsb} ) - $lsb ); - die "Inconsistent LSB/RMASK in $datum->{name} before $field->{name}\n" - if $pad_width < 0; - printf "\tpseudo_bit_t _unused_%u[%u];\n", $reserved_idx++, $pad_width - if $pad_width; - $lsb += $pad_width; - # Damn Perl can't cope with 64-bit hex constants - my $width = 0; - die "Missing RMASK in $datum->{name}.$field->{name}\n" - unless defined $field->{rmask}; - my $rmask = $field->{rmask}; - while ( $rmask =~ /^(0x.+)f$/i ) { - $width += 4; - $rmask = $1; - } - $rmask = hex ( $rmask ); - while ( $rmask ) { - $width++; - $rmask >>= 1; - } - if ( defined $field->{msb} ) { - my $msb_width = ( hex ( $field->{msb} ) - $lsb + 1 ); - $width ||= $msb_width; - die "Inconsistent LSB/MSB/RMASK in $datum->{name}.$field->{name}\n" - unless $width == $msb_width; - } - printf "\tpseudo_bit_t %s[%u];\n", $field->{name}, $width; - $lsb += $width; - } - my $pad_width = ( 64 - $lsb ); - die "Inconsistent LSB/RMASK in $datum->{name} final field\n" - if $pad_width < 0; - printf "\tpseudo_bit_t _unused_%u[%u];\n", $reserved_idx++, $pad_width - if $pad_width; - printf "};\n"; - printf "struct %s {\n\tPSEUDO_BIT_STRUCT ( struct %s_pb );\n};\n", - $datum->{name}, $datum->{name}; - } - printf "/* Default value: %s */\n", $datum->{default} - if defined $datum->{default}; - print "\n"; -} |