vout: support vout2 command for viu2 display [1/1]

PD#TV-5428

Problem:
need viu2 display support

Solution:
add vout2 management
you can use "vout2 output ${outputmode}" to enable vout2 display

Verify:
x301

Change-Id: Id47e430453ebdf7c32f41d271d6e926fd5cf0f6b
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
Signed-off-by: Dongjin Kim <tobetter@gmail.com>

27 files changed, 139 insertions, 311 deletions

diff --git a/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c
index ec2ac574f6..4d4209c661 100644
--- a/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c
@@ -65,20 +65,6 @@
 			printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
 	} while(0);
 
-// viu_channel_sel: 1 or 2
-// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
-int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
-{
-	if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
-		return -1;
-	if (viu_channel_sel == 1)
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
-	else
-		//viu_channel_sel ==2
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
-	return 0;
-}
-
 static void set_hdmitx_sys_clk(void)
 {
 	hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
@@ -345,7 +331,6 @@ void set_hdmitx_clk(enum hdmi_vic vic)
 		return;
 	}
 next:
-	set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out);
 	set_hpll_od1(p_enc[j].od1);
diff --git a/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_set.c
index 8be50642b5..cbe14fb6ed 100644
--- a/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_set.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/register.h>
+#include <amlogic/vout.h>
 #include <amlogic/hdmi.h>
 #include "hdmitx_reg.h"
 #include "hdmitx_tvenc.h"
@@ -406,7 +407,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 
 int hdmi_outputmode_check(char *mode)
 {
-	int i, ret = -1;
+	int i, ret = 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
 		if (!strcmp(mode, gxbb_modes[i].sname)) {
@@ -415,8 +416,14 @@ int hdmi_outputmode_check(char *mode)
 		}
 	}
 
-	if (ret)
+	if (ret) {
 		printf("hdmitx: outputmode[%s] is invalid\n", mode);
+		return ret;
+	}
+	if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+		ret = VIU_MUX_ENCI;
+	else
+		ret = VIU_MUX_ENCP;
 	return ret;
 }
 
diff --git a/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_tvenc.c
index 1de1ea117b..04a4353b1f 100644
--- a/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_tvenc.c
+++ b/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_tvenc.c
@@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 749},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = {
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x407},
 	{P_ENCP_VIDEO_YC_DLY, 0},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x207},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 1124},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_VENC_VIDEO_PROG_MODE, 0x100},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
@@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
index 25b331fc48..c5bf713ce1 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
@@ -70,19 +70,6 @@
 			printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
 	} while (0)
 
-// viu_channel_sel: 1 or 2
-// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
-int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
-{
-	if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
-		return -1;
-	if (viu_channel_sel == 1)
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
-	else
-		//viu_channel_sel ==2
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
-	return 0;
-}
 
 static void set_hdmitx_sys_clk(void)
 {
@@ -1124,7 +1111,6 @@ void hdmitx_set_clk_(struct hdmitx_dev *hdev)
 	}
 
 next:
-	set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out, hdev);
 	if (!getenv("sspll_dis"))
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
index 776c48b61e..565c8d35ea 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/register.h>
+#include <amlogic/vout.h>
 #include <amlogic/hdmi.h>
 #include "hdmitx_reg.h"
 #include "hdmitx_tvenc.h"
@@ -502,7 +503,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 
 int hdmi_outputmode_check(char *mode)
 {
-	int i, ret = -1;
+	int i, ret = 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
 		if (!strcmp(mode, gxbb_modes[i].sname)) {
@@ -511,8 +512,14 @@ int hdmi_outputmode_check(char *mode)
 		}
 	}
 
-	if (ret)
+	if (ret) {
 		printf("hdmitx: outputmode[%s] is invalid\n", mode);
+		return ret;
+	}
+	if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+		ret = VIU_MUX_ENCI;
+	else
+		ret = VIU_MUX_ENCP;
 	return ret;
 }
 
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c
index 9d7e1a6ed6..a911cce90d 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c
@@ -58,7 +58,6 @@ static const struct reg_t tvregs_720p[] = {
 	{P_ENCP_DE_V_END_EVEN, 0x2E9,},
 	{P_ENCP_DE_V_BEGIN_ODD, 0x0,},
 	{P_ENCP_DE_V_END_ODD, 0x0,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -98,7 +97,6 @@ static const struct reg_t tvregs_720p_50hz[] = {
 	{P_ENCP_DE_V_END_EVEN, 0x2E9,},
 	{P_ENCP_DE_V_BEGIN_ODD, 0x0,},
 	{P_ENCP_DE_V_END_ODD, 0x0,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -130,7 +128,6 @@ static const struct reg_t tvregs_480i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -167,7 +164,6 @@ static const struct reg_t tvregs_480p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -204,7 +200,6 @@ static const struct reg_t tvregs_576i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -241,7 +236,6 @@ static const struct reg_t tvregs_576p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -281,7 +275,6 @@ static const struct reg_t tvregs_1080i[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0018},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x207},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -317,7 +310,6 @@ static const struct reg_t tvregs_1080i_50hz[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0018},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -351,7 +343,6 @@ static const struct reg_t tvregs_1080p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 1124},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_VENC_VIDEO_PROG_MODE, 0x100},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
@@ -391,7 +382,6 @@ static const struct reg_t tvregs_1080p_50hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -431,7 +421,6 @@ static const struct reg_t tvregs_1080p_24hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -464,7 +453,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -497,7 +485,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -530,7 +517,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -563,7 +549,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -586,7 +571,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -609,7 +593,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -1006,6 +989,30 @@ static const struct reg_t tvregs_vesa_2560x1080p60hz[] = {
 	{MREG_END_MARKER, 0},
 };
 
+static const struct reg_t tvregs_vesa_1440x2560p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x623,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0xA23,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x44,},
+	{P_ENCP_VIDEO_HAVON_END, 0x5E3,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x14,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0xA13,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x4,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x4,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
 struct vic_tvregs_set {
 	enum hdmi_vic vic;
 	const struct reg_t *reg_setting;
diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c
index 25b331fc48..47da9e9e13 100644
--- a/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c
@@ -70,20 +70,6 @@
 			printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
 	} while (0)
 
-// viu_channel_sel: 1 or 2
-// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
-int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
-{
-	if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
-		return -1;
-	if (viu_channel_sel == 1)
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
-	else
-		//viu_channel_sel ==2
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
-	return 0;
-}
-
 static void set_hdmitx_sys_clk(void)
 {
 	hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
@@ -1124,7 +1110,6 @@ void hdmitx_set_clk_(struct hdmitx_dev *hdev)
 	}
 
 next:
-	set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out, hdev);
 	if (!getenv("sspll_dis"))
diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c
index 776c48b61e..565c8d35ea 100644
--- a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/register.h>
+#include <amlogic/vout.h>
 #include <amlogic/hdmi.h>
 #include "hdmitx_reg.h"
 #include "hdmitx_tvenc.h"
@@ -502,7 +503,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 
 int hdmi_outputmode_check(char *mode)
 {
-	int i, ret = -1;
+	int i, ret = 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
 		if (!strcmp(mode, gxbb_modes[i].sname)) {
@@ -511,8 +512,14 @@ int hdmi_outputmode_check(char *mode)
 		}
 	}
 
-	if (ret)
+	if (ret) {
 		printf("hdmitx: outputmode[%s] is invalid\n", mode);
+		return ret;
+	}
+	if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+		ret = VIU_MUX_ENCI;
+	else
+		ret = VIU_MUX_ENCP;
 	return ret;
 }
 
diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_tvenc.c
index 9d7e1a6ed6..9434bc4d18 100644
--- a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_tvenc.c
+++ b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_tvenc.c
@@ -58,7 +58,6 @@ static const struct reg_t tvregs_720p[] = {
 	{P_ENCP_DE_V_END_EVEN, 0x2E9,},
 	{P_ENCP_DE_V_BEGIN_ODD, 0x0,},
 	{P_ENCP_DE_V_END_ODD, 0x0,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -98,7 +97,6 @@ static const struct reg_t tvregs_720p_50hz[] = {
 	{P_ENCP_DE_V_END_EVEN, 0x2E9,},
 	{P_ENCP_DE_V_BEGIN_ODD, 0x0,},
 	{P_ENCP_DE_V_END_ODD, 0x0,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -130,7 +128,6 @@ static const struct reg_t tvregs_480i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -167,7 +164,6 @@ static const struct reg_t tvregs_480p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -204,7 +200,6 @@ static const struct reg_t tvregs_576i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -241,7 +236,6 @@ static const struct reg_t tvregs_576p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -281,7 +275,6 @@ static const struct reg_t tvregs_1080i[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0018},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x207},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -317,7 +310,6 @@ static const struct reg_t tvregs_1080i_50hz[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0018},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -351,7 +343,6 @@ static const struct reg_t tvregs_1080p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 1124},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_VENC_VIDEO_PROG_MODE, 0x100},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
@@ -391,7 +382,6 @@ static const struct reg_t tvregs_1080p_50hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -431,7 +421,6 @@ static const struct reg_t tvregs_1080p_24hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -464,7 +453,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -497,7 +485,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -530,7 +517,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -563,7 +549,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -586,7 +571,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -609,7 +593,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
diff --git a/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c
index 84582d6e27..7590a5f9e0 100644
--- a/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c
@@ -68,20 +68,6 @@
 			printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
 	} while (0)
 
-// viu_channel_sel: 1 or 2
-// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
-int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
-{
-	if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
-		return -1;
-	if (viu_channel_sel == 1)
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
-	else
-		//viu_channel_sel ==2
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
-	return 0;
-}
-
 static void set_hdmitx_sys_clk(void)
 {
 	hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
@@ -372,7 +358,6 @@ void set_hdmitx_clk(enum hdmi_vic vic)
 		return;
 	}
 next:
-	set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out);
 	set_hpll_od1(p_enc[j].od1);
diff --git a/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_set.c
index 25fe4119d2..3d1dacf4ac 100644
--- a/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_set.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/register.h>
+#include <amlogic/vout.h>
 #include <amlogic/hdmi.h>
 #include <amlogic/sound.h>
 #include "hdmitx_reg.h"
@@ -414,7 +415,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 
 int hdmi_outputmode_check(char *mode)
 {
-	int i, ret = -1;
+	int i, ret = 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
 		if (!strcmp(mode, gxbb_modes[i].sname)) {
@@ -423,8 +424,14 @@ int hdmi_outputmode_check(char *mode)
 		}
 	}
 
-	if (ret)
+	if (ret) {
 		printf("hdmitx: outputmode[%s] is invalid\n", mode);
+		return ret;
+	}
+	if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+		ret = VIU_MUX_ENCI;
+	else
+		ret = VIU_MUX_ENCP;
 	return ret;
 }
 
diff --git a/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_tvenc.c
index 9c4dad7d38..ff6bc1ac8a 100644
--- a/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_tvenc.c
+++ b/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_tvenc.c
@@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 749},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = {
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x407},
 	{P_ENCP_VIDEO_YC_DLY, 0},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x207},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 1124},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_VENC_VIDEO_PROG_MODE, 0x100},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
@@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
diff --git a/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c
index c4169775c6..da6964d482 100644
--- a/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c
@@ -70,20 +70,6 @@ static uint32_t frac_rate;
 			printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
 	} while (0)
 
-// viu_channel_sel: 1 or 2
-// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
-int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
-{
-	if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
-		return -1;
-	if (viu_channel_sel == 1)
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
-	else
-		//viu_channel_sel ==2
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
-	return 0;
-}
-
 static void set_hdmitx_sys_clk(void)
 {
 	hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
@@ -947,7 +933,6 @@ static void set_hdmitx_clk_(struct hdmitx_dev *hdev, enum hdmi_color_depth cd)
 		return;
 	}
 next:
-	set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out);
 	if (!getenv("sspll_dis"))
diff --git a/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_set.c
index f0702ca1c0..6e8c4f5061 100644
--- a/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_set.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/register.h>
+#include <amlogic/vout.h>
 #include <amlogic/hdmi.h>
 #include <amlogic/sound.h>
 #include "hdmitx_reg.h"
@@ -430,7 +431,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 
 int hdmi_outputmode_check(char *mode)
 {
-	int i, ret = -1;
+	int i, ret = 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
 		if (!strcmp(mode, gxbb_modes[i].sname)) {
@@ -439,8 +440,14 @@ int hdmi_outputmode_check(char *mode)
 		}
 	}
 
-	if (ret)
+	if (ret) {
 		printf("hdmitx: outputmode[%s] is invalid\n", mode);
+		return ret;
+	}
+	if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+		ret = VIU_MUX_ENCI;
+	else
+		ret = VIU_MUX_ENCP;
 	return ret;
 }
 
diff --git a/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_tvenc.c
index 3572484923..183194812b 100644
--- a/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_tvenc.c
+++ b/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_tvenc.c
@@ -51,7 +51,6 @@ static const struct reg_t tvregs_720p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 749},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -87,7 +86,6 @@ static const struct reg_t tvregs_720p_50hz[] = {
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x407},
 	{P_ENCP_VIDEO_YC_DLY, 0},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -123,7 +121,6 @@ static const struct reg_t tvregs_720p_100hz[] = {
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x407},
 	{P_ENCP_VIDEO_YC_DLY, 0},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -156,7 +153,6 @@ static const struct reg_t tvregs_720p_120hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 749},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -188,7 +184,6 @@ static const struct reg_t tvregs_480i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -225,7 +220,6 @@ static const struct reg_t tvregs_480p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -262,7 +256,6 @@ static const struct reg_t tvregs_576i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -299,7 +292,6 @@ static const struct reg_t tvregs_576p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -339,7 +331,6 @@ static const struct reg_t tvregs_1080i[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x207},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -375,7 +366,6 @@ static const struct reg_t tvregs_1080i_50hz[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -409,7 +399,6 @@ static const struct reg_t tvregs_1080p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 1124},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_VENC_VIDEO_PROG_MODE, 0x100},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
@@ -449,7 +438,6 @@ static const struct reg_t tvregs_1080p_50hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -489,7 +477,6 @@ static const struct reg_t tvregs_1080p_24hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -522,7 +509,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -555,7 +541,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -588,7 +573,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -621,7 +605,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -644,7 +627,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -667,7 +649,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -692,7 +673,6 @@ static const struct reg_t tvregs_vesa_640x480p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x2,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -717,7 +697,6 @@ static const struct reg_t tvregs_vesa_800x600p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x4,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -742,7 +721,6 @@ static const struct reg_t tvregs_vesa_800x480p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x7},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -765,7 +743,6 @@ static const struct reg_t tvregs_vesa_852x480p60hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -788,7 +765,6 @@ static const struct reg_t tvregs_vesa_854x480p60hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -813,7 +789,6 @@ static const struct reg_t tvregs_vesa_1024x600p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -838,7 +813,6 @@ static const struct reg_t tvregs_vesa_1024x768p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -863,7 +837,6 @@ static const struct reg_t tvregs_vesa_1152x864p75hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -889,7 +862,6 @@ static const struct reg_t tvregs_vesa_1280x600p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
@@ -915,7 +887,6 @@ static const struct reg_t tvregs_vesa_1280x768p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x7,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
@@ -940,7 +911,6 @@ static const struct reg_t tvregs_vesa_1280x800p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
@@ -965,7 +935,6 @@ static const struct reg_t tvregs_vesa_1280x960p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
@@ -990,7 +959,6 @@ static const struct reg_t tvregs_vesa_1280x1024p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
@@ -1015,7 +983,6 @@ static const struct reg_t tvregs_vesa_1360x768p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -1040,7 +1007,6 @@ static const struct reg_t tvregs_vesa_1366x768p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -1065,7 +1031,6 @@ static const struct reg_t tvregs_vesa_1400x1050p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x4,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -1090,7 +1055,6 @@ static const struct reg_t tvregs_vesa_1440x900p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -1115,7 +1079,6 @@ static const struct reg_t tvregs_vesa_1440x2560p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x4,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -1140,7 +1103,6 @@ static const struct reg_t tvregs_vesa_1440x2560p70hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -1165,7 +1127,6 @@ static const struct reg_t tvregs_vesa_1600x900p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -1190,7 +1151,6 @@ static const struct reg_t tvregs_vesa_1600x1200p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -1215,7 +1175,6 @@ static const struct reg_t tvregs_vesa_1680x1050p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1,},
 	{P_ENCI_VIDEO_EN, 0,},
 	{MREG_END_MARKER, 0}
@@ -1240,7 +1199,6 @@ static const struct reg_t tvregs_vesa_1920x1200p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
@@ -1264,7 +1222,6 @@ static const struct reg_t tvregs_vesa_2160x1200p90hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -1289,7 +1246,6 @@ static const struct reg_t tvregs_vesa_2560x1600p60hz[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
@@ -1316,7 +1272,6 @@ static const struct reg_t tvregs_vesa_2560x1080p60hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
@@ -1342,7 +1297,6 @@ static const struct reg_t tvregs_vesa_2560x1440p60hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
@@ -1368,7 +1322,6 @@ static const struct reg_t tvregs_vesa_3440x1440p60hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
 
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0}
diff --git a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c
index aff0b0d819..de86a7898e 100644
--- a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c
@@ -68,20 +68,6 @@
 			printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
 	} while (0)
 
-// viu_channel_sel: 1 or 2
-// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
-int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
-{
-	if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
-		return -1;
-	if (viu_channel_sel == 1)
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
-	else
-		//viu_channel_sel ==2
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
-	return 0;
-}
-
 static void set_hdmitx_sys_clk(void)
 {
 	hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
@@ -355,7 +341,6 @@ void set_hdmitx_clk(enum hdmi_vic vic)
 		return;
 	}
 next:
-	set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out);
 	set_hpll_od1(p_enc[j].od1);
diff --git a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_set.c
index 1c972f1548..bbd9a8597f 100644
--- a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_set.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/register.h>
+#include <amlogic/vout.h>
 #include <amlogic/hdmi.h>
 #include <amlogic/sound.h>
 #include "hdmitx_reg.h"
@@ -411,7 +412,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 
 int hdmi_outputmode_check(char *mode)
 {
-	int i, ret = -1;
+	int i, ret = 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
 		if (!strcmp(mode, gxbb_modes[i].sname)) {
@@ -420,8 +421,14 @@ int hdmi_outputmode_check(char *mode)
 		}
 	}
 
-	if (ret)
+	if (ret) {
 		printf("hdmitx: outputmode[%s] is invalid\n", mode);
+		return ret;
+	}
+	if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+		ret = VIU_MUX_ENCI;
+	else
+		ret = VIU_MUX_ENCP;
 	return ret;
 }
 
diff --git a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_tvenc.c
index ccfd907fdb..2a57113b8e 100644
--- a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_tvenc.c
+++ b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_tvenc.c
@@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 749},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = {
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x407},
 	{P_ENCP_VIDEO_YC_DLY, 0},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x207},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 1124},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_VENC_VIDEO_PROG_MODE, 0x100},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
@@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
diff --git a/arch/arm/cpu/armv8/tl1/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/tl1/hdmitx20/hdmitx_set.c
index 01ed7d321c..f898dc2742 100644
--- a/arch/arm/cpu/armv8/tl1/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/tl1/hdmitx20/hdmitx_set.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/register.h>
+#include <amlogic/vout.h>
 #include <amlogic/hdmi.h>
 #include "hdmitx_reg.h"
 #include "hdmitx_tvenc.h"
@@ -424,7 +425,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 
 int hdmi_outputmode_check(char *mode)
 {
-	int i, ret = -1;
+	int i, ret = 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
 		if (!strcmp(mode, gxbb_modes[i].sname)) {
@@ -433,8 +434,14 @@ int hdmi_outputmode_check(char *mode)
 		}
 	}
 
-	if (ret)
+	if (ret) {
 		printf("hdmitx: outputmode[%s] is invalid\n", mode);
+		return ret;
+	}
+	if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+		ret = VIU_MUX_ENCI;
+	else
+		ret = VIU_MUX_ENCP;
 	return ret;
 }
 
diff --git a/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c
index ec2ac574f6..4d4209c661 100644
--- a/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c
@@ -65,20 +65,6 @@
 			printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
 	} while(0);
 
-// viu_channel_sel: 1 or 2
-// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
-int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
-{
-	if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
-		return -1;
-	if (viu_channel_sel == 1)
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
-	else
-		//viu_channel_sel ==2
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
-	return 0;
-}
-
 static void set_hdmitx_sys_clk(void)
 {
 	hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
@@ -345,7 +331,6 @@ void set_hdmitx_clk(enum hdmi_vic vic)
 		return;
 	}
 next:
-	set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out);
 	set_hpll_od1(p_enc[j].od1);
diff --git a/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_set.c
index 68634d7d3f..7d4b8921b8 100644
--- a/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_set.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/register.h>
+#include <amlogic/vout.h>
 #include <amlogic/hdmi.h>
 #include "hdmitx_reg.h"
 #include "hdmitx_tvenc.h"
@@ -406,7 +407,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 
 int hdmi_outputmode_check(char *mode)
 {
-	int i, ret = -1;
+	int i, ret = 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
 		if (!strcmp(mode, gxbb_modes[i].sname)) {
@@ -415,8 +416,14 @@ int hdmi_outputmode_check(char *mode)
 		}
 	}
 
-	if (ret)
+	if (ret) {
 		printf("hdmitx: outputmode[%s] is invalid\n", mode);
+		return ret;
+	}
+	if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+		ret = VIU_MUX_ENCI;
+	else
+		ret = VIU_MUX_ENCP;
 	return ret;
 }
 
diff --git a/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_tvenc.c
index 1de1ea117b..04a4353b1f 100644
--- a/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_tvenc.c
+++ b/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_tvenc.c
@@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 749},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = {
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x407},
 	{P_ENCP_VIDEO_YC_DLY, 0},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x207},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 1124},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_VENC_VIDEO_PROG_MODE, 0x100},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
@@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
diff --git a/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c
index ca12caa63c..550fd5532f 100644
--- a/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c
@@ -70,20 +70,6 @@ static uint32_t frac_rate;
 			printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
 	} while (0)
 
-// viu_channel_sel: 1 or 2
-// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
-int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
-{
-	if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
-		return -1;
-	if (viu_channel_sel == 1)
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
-	else
-		//viu_channel_sel ==2
-		hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
-	return 0;
-}
-
 static void set_hdmitx_sys_clk(void)
 {
 	hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
@@ -947,7 +933,6 @@ static void set_hdmitx_clk_(struct hdmitx_dev *hdev, enum hdmi_color_depth cd)
 		return;
 	}
 next:
-	set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out);
 	if (!getenv("sspll_dis"))
diff --git a/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_set.c
index f5da4f7b43..122f490457 100644
--- a/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_set.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/register.h>
+#include <amlogic/vout.h>
 #include <amlogic/hdmi.h>
 #include "hdmitx_reg.h"
 #include "hdmitx_tvenc.h"
@@ -424,7 +425,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 
 int hdmi_outputmode_check(char *mode)
 {
-	int i, ret = -1;
+	int i, ret = 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
 		if (!strcmp(mode, gxbb_modes[i].sname)) {
@@ -433,8 +434,14 @@ int hdmi_outputmode_check(char *mode)
 		}
 	}
 
-	if (ret)
+	if (ret) {
 		printf("hdmitx: outputmode[%s] is invalid\n", mode);
+		return ret;
+	}
+	if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+		ret = VIU_MUX_ENCI;
+	else
+		ret = VIU_MUX_ENCP;
 	return ret;
 }
 
diff --git a/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_tvenc.c
index 25aebf5dca..cf672dc7e5 100644
--- a/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_tvenc.c
+++ b/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_tvenc.c
@@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 749},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = {
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x407},
 	{P_ENCP_VIDEO_YC_DLY, 0},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = {
 	{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
 	{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
 	{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
 	{P_ENCP_VIDEO_EN, 0},
 	{P_ENCI_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_SY_VAL, 8},
 	{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x207},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = {
 	{P_ENCP_VIDEO_MODE, 0x5ffc},
 	{P_ENCP_VIDEO_MODE_ADV, 0x0019},
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = {
 	{P_ENCP_VIDEO_VSO_BLINE, 0},
 	{P_ENCP_VIDEO_VSO_ELINE, 5},
 	{P_ENCP_VIDEO_MAX_LNCNT, 1124},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_VENC_VIDEO_PROG_MODE, 0x100},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
@@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = {
 	{P_ENCP_VIDEO_SYNC_MODE, 0x7},
 	{P_ENCP_VIDEO_YC_DLY, 0},
 	{P_ENCP_VIDEO_RGB_CTRL, 2},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCI_VIDEO_EN, 0},
 	{P_ENCP_VIDEO_EN, 1},
 	{MREG_END_MARKER, 0},
@@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = {
 	{P_ENCP_VIDEO_VSO_ELINE, 53},
 	{P_ENCP_VIDEO_MAX_LNCNT, 2249},
 	{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
@@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
 	{P_ENCP_VIDEO_VSO_END, 0x32,},
 	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
 	{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-	{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
 	{P_ENCP_VIDEO_EN, 1},
 	{P_ENCI_VIDEO_EN, 0},
 	{MREG_END_MARKER, 0},
diff --git a/arch/arm/include/asm/arch-g12a/regs.h b/arch/arm/include/asm/arch-g12a/regs.h
index af9fa9b33a..25b121a4ba 100644
--- a/arch/arm/include/asm/arch-g12a/regs.h
+++ b/arch/arm/include/asm/arch-g12a/regs.h
@@ -24129,10 +24129,21 @@
 //Bit 11:0   vertical formatter width
 #define   VIU2_VD1_FMT_W                           (0x1e69)
 #define P_VIU2_VD1_FMT_W                           (volatile unsigned int *)((0x1e69  << 2) + 0xff900000)
-#define   VIU2_VD1_IF0_GEN_REG3                    (0x1e70)
-#define P_VIU2_VD1_IF0_GEN_REG3                    (volatile unsigned int *)((0x1e70  << 2) + 0xff900000)
-//bit 31:1,  reversed
-//bit 0,     cntl_64bit_rev
+//`define VIU2_MATRIX_CTRL                       8'h70
+#define VIU2_OSD1_MATRIX_COEF00_01                 0x1e70
+#define VIU2_OSD1_MATRIX_COEF02_10                 0x1e71
+#define VIU2_OSD1_MATRIX_COEF11_12                 0x1e72
+#define VIU2_OSD1_MATRIX_COEF20_21                 0x1e73
+#define VIU2_OSD1_MATRIX_COEF22                    0x1e74
+#define VIU2_OSD1_MATRIX_COEF13_14                 0x1e75
+#define VIU2_OSD1_MATRIX_COEF23_24                 0x1e76
+#define VIU2_OSD1_MATRIX_COEF15_25                 0x1e77
+#define VIU2_OSD1_MATRIX_CLIP                      0x1e78
+#define VIU2_OSD1_MATRIX_OFFSET0_1                 0x1e79
+#define VIU2_OSD1_MATRIX_OFFSET2                   0x1e7a
+#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1             0x1e7b
+#define VIU2_OSD1_MATRIX_PRE_OFFSET2               0x1e7c
+#define VIU2_OSD1_MATRIX_EN_CTRL                   0x1e7d
 // synopsys translate_off
 // synopsys translate_on
 //
@@ -24689,6 +24700,7 @@
 #define P_VPU_VIU_ASYNC_MASK                       (volatile unsigned int *)((0x2781  << 2) + 0xff900000)
 #define   VDIN_MISC_CTRL                           (0x2782)
 #define P_VDIN_MISC_CTRL                           (volatile unsigned int *)((0x2782  << 2) + 0xff900000)
+#define VPU_VENCX_CLK_CTRL                         0x2785
 // vpu arbtration :
 // the segment is 8'h90-8'hc8
 //
diff --git a/arch/arm/include/asm/arch-g12b/regs.h b/arch/arm/include/asm/arch-g12b/regs.h
index af9fa9b33a..b75fe2f1c4 100644
--- a/arch/arm/include/asm/arch-g12b/regs.h
+++ b/arch/arm/include/asm/arch-g12b/regs.h
@@ -24129,10 +24129,23 @@
 //Bit 11:0   vertical formatter width
 #define   VIU2_VD1_FMT_W                           (0x1e69)
 #define P_VIU2_VD1_FMT_W                           (volatile unsigned int *)((0x1e69  << 2) + 0xff900000)
-#define   VIU2_VD1_IF0_GEN_REG3                    (0x1e70)
-#define P_VIU2_VD1_IF0_GEN_REG3                    (volatile unsigned int *)((0x1e70  << 2) + 0xff900000)
-//bit 31:1,  reversed
-//bit 0,     cntl_64bit_rev
+//`define VIU2_MATRIX_CTRL                       8'h70
+#define VIU2_OSD1_MATRIX_COEF00_01                 0x1e70
+#define VIU2_OSD1_MATRIX_COEF02_10                 0x1e71
+#define VIU2_OSD1_MATRIX_COEF11_12                 0x1e72
+#define VIU2_OSD1_MATRIX_COEF20_21                 0x1e73
+#define VIU2_OSD1_MATRIX_COEF22                    0x1e74
+#define VIU2_OSD1_MATRIX_COEF13_14                 0x1e75
+#define VIU2_OSD1_MATRIX_COEF23_24                 0x1e76
+#define VIU2_OSD1_MATRIX_COEF15_25                 0x1e77
+#define VIU2_OSD1_MATRIX_CLIP                      0x1e78
+#define VIU2_OSD1_MATRIX_OFFSET0_1                 0x1e79
+#define VIU2_OSD1_MATRIX_OFFSET2                   0x1e7a
+#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1             0x1e7b
+#define VIU2_OSD1_MATRIX_PRE_OFFSET2               0x1e7c
+#define VIU2_OSD1_MATRIX_EN_CTRL                   0x1e7d
+#define VIU2_RMIF_CTRL0                            0x1e80
+#define VIU2_RMIF_CTRL1                            0x1e81
 // synopsys translate_off
 // synopsys translate_on
 //
@@ -24689,6 +24702,7 @@
 #define P_VPU_VIU_ASYNC_MASK                       (volatile unsigned int *)((0x2781  << 2) + 0xff900000)
 #define   VDIN_MISC_CTRL                           (0x2782)
 #define P_VDIN_MISC_CTRL                           (volatile unsigned int *)((0x2782  << 2) + 0xff900000)
+#define VPU_VENCX_CLK_CTRL                         0x2785
 // vpu arbtration :
 // the segment is 8'h90-8'hc8
 //