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| author | Jiamin Ma <jiamin.ma@amlogic.com> | 2019-04-12 08:21:13 +0800 |
|---|---|---|
| committer | Dongjin Kim <tobetter@gmail.com> | 2019-05-16 13:21:14 +0900 |
| commit | 122b7f04618f2bf77a8d9bc88c215e527d08f884 (patch) | |
| tree | 74a4aca8fe97b21ed00c0cedcbe3e35ab624f338 /arch | |
| parent | 1d01156f306cce581374ba3968c8fe658099cc3b (diff) | |
| download | u-boot-odroid-c1-122b7f04618f2bf77a8d9bc88c215e527d08f884.tar.gz | |
virtual_counter: fix abnormal CNTVCT value for ARMv8 AARCH32 mode [1/4]
PD#SWPL-7033
Problem:
The start counter value of the virtual counter value for global counter
in ARMv8 AARCH32 mode is a quite large one. aka. 0x926A55C29C88EBF3,
which is abnormal
Solution:
Clear virtual offset(cntvoff_el2) in suitable places
Verify:
Ampere && R311
Change-Id: I8ba3d5f76c21b9066ee64b568d367127ab616405
Signed-off-by: Jiamin Ma <jiamin.ma@amlogic.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv8/a32_kernel_pre_entry.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/a32_kernel_pre_entry.S b/arch/arm/cpu/armv8/a32_kernel_pre_entry.S index ac4220e08a..145fc47118 100644 --- a/arch/arm/cpu/armv8/a32_kernel_pre_entry.S +++ b/arch/arm/cpu/armv8/a32_kernel_pre_entry.S @@ -33,13 +33,13 @@ ENTRY(jump_to_a32_kernel) movk x0, #0x00c5, lsl #16 // Clear EE and E0E on LE systems msr sctlr_el1, x0 -#if 0 /* Generic timers. */ mrs x0, cnthctl_el2 orr x0, x0, #3 // Enable EL1 physical timers msr cnthctl_el2, x0 msr cntvoff_el2, xzr // Clear virtual offset +#if 0 /* Populate ID registers. */ mrs x0, midr_el1 mrs x1, mpidr_el1 |