diff options
| author | he.he <he.he@amlogic.com> | 2019-02-25 15:21:01 +0800 |
|---|---|---|
| committer | Dongjin Kim <tobetter@gmail.com> | 2020-02-10 22:49:50 +0900 |
| commit | d438d1d5b9d1630bfda6af4cd7c37cf0d29b2237 (patch) | |
| tree | 398f9e0473f1846ff27f2b05c1c122d49b5cd467 /arch | |
| parent | 78d3695dbe40686f5749a3094fdef7a552d4e6ad (diff) | |
| download | u-boot-odroid-c1-d438d1d5b9d1630bfda6af4cd7c37cf0d29b2237.tar.gz | |
uboot-usb: set pll registers of revB usb [2/2]
PD#SWPL-4941
Problem:
revB: EL27,28,29,31 failed in the el compliance test in kernel,
and have been solved by modifing some usb pll parameters.
Solution:
The usb pll registers in uboot need keep consistent with kernel.
Verify:
verify on revB
Test: Pass
Change-Id: I953538bc47fc1b3e2f4f6c85f7eb335ad112f573
Signed-off-by: he.he <he.he@amlogic.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv8/g12b/usb.c | 37 |
1 files changed, 19 insertions, 18 deletions
diff --git a/arch/arm/cpu/armv8/g12b/usb.c b/arch/arm/cpu/armv8/g12b/usb.c index 23e3acc68f..ad128c9bb0 100644 --- a/arch/arm/cpu/armv8/g12b/usb.c +++ b/arch/arm/cpu/armv8/g12b/usb.c @@ -30,15 +30,13 @@ static int Rev_flag = 0; /*Rev_flag == 1, g12b and revB, tl1 */ static void board_usb_check_g12b_revb (void) { - unsigned int version_id; cpu_id_t cpu_id = get_cpu_id(); if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) { - version_id = readl(AO_METAL_REVISION); - if ((version_id == 0x11111111)) - Rev_flag = 0; - else + if (cpu_id.chip_rev == 0xb) Rev_flag = 1; + else + Rev_flag = 0; } else { Rev_flag = 0; } @@ -127,23 +125,26 @@ void board_usb_pll_disable(struct amlogic_usb_config *cfg) void set_usb_phy_tuning_1(int port) { - unsigned long phy_reg_base; - - if (board_usb_get_revb_type() == 1) - return; + unsigned long phy_reg_base; if (port > 2) - return; + return; if (port == 0 ) - phy_reg_base = USB_REG_A; - else - phy_reg_base = USB_REG_B; - - (*(volatile uint32_t *)(phy_reg_base + 0x10)) = USB_G12x_PHY_PLL_SETTING_2; - (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1; - (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB_G12x_PHY_PLL_SETTING_4; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3; + phy_reg_base = USB_REG_A; + else + phy_reg_base = USB_REG_B; + + if (board_usb_get_revb_type() == 1) { + (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1; + (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3 & (0x1f << 16); + return; + } + + (*(volatile uint32_t *)(phy_reg_base + 0x10)) = USB_G12x_PHY_PLL_SETTING_2; + (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1; + (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB_G12x_PHY_PLL_SETTING_4; + (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3; } #endif |