ODROID-C4: display: g12a: Add new display modes on HDMI PHY

- 1024x600p60hz
- 1024x768p60hz
- 1280x1024p60hz
- 1280x800p60hz
- 1360x768p60hz
- 1440x900p60hz
- 1600x1200p60hz
- 1600x900p60hz
- 1920x1200p60hz
- 2560x1080p60hz
- 2560x1440p60hz
- 2560x1600p60hz
- 480x320p60hz
- 640x480p60hz
- 800x480p60hz
- 800x600p60hz

Change-Id: Ib91cc394c88fb4e868dec808b40f9949d72344c0

3 files changed, 887 insertions, 12 deletions

diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
index 7e65a27a00..25b331fc48 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
@@ -226,6 +226,57 @@ static void set_hpll_clk_out(unsigned clk, struct hdmitx_dev *hdev)
 		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		break;
+	case 4324320:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b4);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00005c29);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 4320000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b3);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00005c29);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 4028000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004a7);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00005c29);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
 	case 3712500:
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00049a);
 		if (frac_rate)
@@ -255,6 +306,18 @@ static void set_hpll_clk_out(unsigned clk, struct hdmitx_dev *hdev)
 		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		break;
+	case 3420000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048e);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
 	case 3243240:
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000487);
 		if (frac_rate)
@@ -287,20 +350,153 @@ static void set_hpll_clk_out(unsigned clk, struct hdmitx_dev *hdev)
 		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		break;
-	case 4324320:
-		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b4);
+	case 2685000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00046F);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2600000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00046C);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2415000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000464);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2134000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00045A);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 2058000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000455);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1855800:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00044C);
 		if (frac_rate)
 			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
 		else
-			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00005c29);
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1591600:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000441);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1560000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000440);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1540000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00043F);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
 		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+		break;
+	case 1422000:
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00043A);
+		if (frac_rate)
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+		else
+			hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
 		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		break;
@@ -583,6 +779,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 	{
 		{
 			HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */
+			HDMIV_480x320p60hz,
 			GROUP_END
 		},
 		1, VIU_ENCP, 4028000, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
@@ -591,13 +788,13 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 		{
 			HDMIV_800x480p60hz, GROUP_END
 		},
-		1, VIU_ENCP, 4761600, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+		1, VIU_ENCP, 2415000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
 	},
 	{
 		{
 			HDMIV_800x600p60hz, GROUP_END
 		},
-		1, VIU_ENCP, 3200000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+		1, VIU_ENCP, 1591600, 2, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
 	},
 	{
 		{
@@ -609,13 +806,13 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 		{
 			HDMIV_1024x600p60hz, GROUP_END
 		},
-		1, VIU_ENCP, 4115866, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+		1, VIU_ENCP, 2058000, 2, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
 	},
 	{
 		{
 			HDMIV_1024x768p60hz, GROUP_END
 		},
-		1, VIU_ENCP, 5200000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+		1, VIU_ENCP, 2600000, 2, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
 	},
 	{
 		{
@@ -627,7 +824,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 		{
 			HDMIV_1280x800p60hz,GROUP_END
 		},
-		1, VIU_ENCP, 5680000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+		1, VIU_ENCP, 1422000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
 	},
 	{
 		{
@@ -641,7 +838,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 		{
 			HDMIV_1600x1200p60hz, GROUP_END
 		},
-		1, VIU_ENCP, 3240000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+		1, VIU_ENCP, 1560000, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
 	},
 	{
 		{
@@ -659,7 +856,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 		{
 			HDMIV_1440x900p60hz, GROUP_END
 		},
-		1, VIU_ENCP, 4260000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+		1, VIU_ENCP, 2134000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
 	},
 	{
 		{
@@ -683,13 +880,25 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 		{
 			HDMIV_1920x1200p60hz, GROUP_END
 		},
-		1, VIU_ENCP, 3865000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+		1, VIU_ENCP, 1540000, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
 	},
 	{
 		{
 			HDMIV_2560x1600p60hz, GROUP_END
 		},
-		1, VIU_ENCP, 3485000, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+		1, VIU_ENCP, 2685000, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+	},
+	{
+		{
+			HDMIV_2560x1440p60hz, GROUP_END
+		},
+		1, VIU_ENCP, 2415000, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
+	},
+	{
+		{
+			HDMIV_2560x1080p60hz, GROUP_END
+		},
+		1, VIU_ENCP, 1855800, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
 	},
 };
 
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
index 9e7215e880..776c48b61e 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
@@ -398,6 +398,23 @@ static struct hdmi_support_mode gxbb_modes[] = {
 	{HDMI_720x480p60_16x9, "480p60hz", 0},
 	{HDMI_720x576i50_16x9, "576i50hz", 0},
 	{HDMI_720x480i60_16x9, "480i60hz", 0},
+	/* VESA modes */
+	{HDMIV_800x480p60hz, "800x480p60hz", 0},
+	{HDMIV_1024x600p60hz, "1024x600p60hz", 0},
+	{HDMIV_1600x1200p60hz, "1600x1200p60hz", 0},
+	{HDMIV_1600x900p60hz, "1600x900p60hz", 0},
+	{HDMIV_1440x900p60hz, "1440x900p60hz", 0},
+	{HDMIV_1360x768p60hz, "1360x768p60hz", 0},
+	{HDMIV_1280x1024p60hz, "1280x1024p60hz", 0},
+	{HDMIV_1280x800p60hz, "1280x800p60hz", 0},
+	{HDMIV_1024x768p60hz, "1024x768p60hz", 0},
+	{HDMIV_800x600p60hz, "800x600p60hz", 0},
+	{HDMIV_640x480p60hz, "640x480p60hz", 0},
+	{HDMIV_480x320p60hz, "480x320p60hz", 0},
+	{HDMIV_1920x1200p60hz, "1920x1200p60hz", 0},
+	{HDMIV_2560x1600p60hz, "2560x1600p60hz", 0},
+	{HDMIV_2560x1440p60hz, "2560x1440p60hz", 0},
+	{HDMIV_2560x1080p60hz, "2560x1080p60hz", 0},
 };
 
 static void hdmitx_list_support_modes(void)
@@ -1238,12 +1255,30 @@ static void hdmitx_set_phy(struct hdmitx_dev *hdev)
 		else
 			set_phy_by_mode(1);
 		break;
+	case HDMIV_2560x1600p60hz:
+	case HDMIV_2560x1440p60hz:
+		set_phy_by_mode(2);
+		break;
 	case HDMI_1920x1080p60_16x9:
 	case HDMI_1920x1080p50_16x9:
 	case HDMI_1920x1080i100_16x9:
 	case HDMI_1920x1080i120_16x9:
 	case HDMI_1280x720p100_16x9:
 	case HDMI_1280x720p120_16x9:
+	case HDMIV_800x480p60hz:
+	case HDMIV_1024x600p60hz:
+	case HDMIV_1600x1200p60hz:
+	case HDMIV_1600x900p60hz:
+	case HDMIV_1440x900p60hz:
+	case HDMIV_1360x768p60hz:
+	case HDMIV_1280x1024p60hz:
+	case HDMIV_1280x800p60hz:
+	case HDMIV_1024x768p60hz:
+	case HDMIV_800x600p60hz:
+	case HDMIV_640x480p60hz:
+	case HDMIV_480x320p60hz:
+	case HDMIV_1920x1200p60hz:
+	case HDMIV_2560x1080p60hz:
 	default:
 		set_phy_by_mode(3);
 		break;
@@ -1941,6 +1976,230 @@ static void hdmi_tvenc_set_def(enum hdmi_vic vic)
 		VSYNC_LINES = 5;
 		SOF_LINES = 36;
 		break;
+	case HDMIV_800x480p60hz:
+		INTERLACE_MODE      = 0;
+		PIXEL_REPEAT_VENC   = 0;
+		PIXEL_REPEAT_HDMI   = 0;
+		ACTIVE_PIXELS       = (800*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES        = (480*(1+INTERLACE_MODE));
+		LINES_F0            = 500;
+		LINES_F1            = 500;
+		FRONT_PORCH         = 24;
+		HSYNC_PIXELS        = 72;
+		BACK_PORCH          = 96;
+		VSYNC_LINES         = 7;
+		SOF_LINES           = 10;
+		break;
+	case HDMIV_1024x600p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1024*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (600/(1+INTERLACE_MODE));
+		LINES_F0 = 638;
+		LINES_F1 = 638;
+		FRONT_PORCH = 24;
+		HSYNC_PIXELS = 136;
+		BACK_PORCH = 160;
+		VSYNC_LINES = 6;
+		SOF_LINES = 29;
+		break;
+	case HDMIV_1600x1200p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1600*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1200/(1+INTERLACE_MODE));
+		LINES_F0 = 1270;
+		LINES_F1 = 1270;
+		FRONT_PORCH = 32;
+		HSYNC_PIXELS = 160;
+		BACK_PORCH = 256;
+		VSYNC_LINES = 8;
+		SOF_LINES = 52;
+		break;
+	case HDMIV_1600x900p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1600*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (900/(1+INTERLACE_MODE));
+		LINES_F0 = 1800;
+		LINES_F1 = 1800;
+		FRONT_PORCH = 24;
+		HSYNC_PIXELS = 80;
+		BACK_PORCH = 96;
+		VSYNC_LINES = 3;
+		SOF_LINES = 96;
+		break;
+	case HDMIV_1440x900p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1440*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (900/(1+INTERLACE_MODE));
+		LINES_F0 = 934;
+		LINES_F1 = 934;
+		FRONT_PORCH = 80;
+		HSYNC_PIXELS = 152;
+		BACK_PORCH = 232;
+		VSYNC_LINES = 6;
+		SOF_LINES = 25;
+		break;
+	case HDMIV_1360x768p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1360*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (768/(1+INTERLACE_MODE));
+		LINES_F0 = 795;
+		LINES_F1 = 795;
+		FRONT_PORCH = 64;
+		HSYNC_PIXELS = 112;
+		BACK_PORCH = 256;
+		VSYNC_LINES = 6;
+		SOF_LINES = 18;
+		break;
+	case HDMIV_1280x1024p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1024/(1+INTERLACE_MODE));
+		LINES_F0 = 1066;
+		LINES_F1 = 1066;
+		FRONT_PORCH = 48;
+		HSYNC_PIXELS = 112;
+		BACK_PORCH = 248;
+		VSYNC_LINES = 3;
+		SOF_LINES = 38;
+		break;
+	case HDMIV_1280x800p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (800/(1+INTERLACE_MODE));
+		LINES_F0 = 823;
+		LINES_F1 = 823;
+		FRONT_PORCH = 48;
+		HSYNC_PIXELS = 32;
+		BACK_PORCH = 80;
+		VSYNC_LINES = 6;
+		SOF_LINES = 14;
+		break;
+	case HDMIV_1024x768p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1024*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (768/(1+INTERLACE_MODE));
+		LINES_F0 = 806;
+		LINES_F1 = 806;
+		FRONT_PORCH = 24;
+		HSYNC_PIXELS = 136;
+		BACK_PORCH = 160;
+		VSYNC_LINES = 6;
+		SOF_LINES = 29;
+		break;
+	case HDMIV_800x600p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (800*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (600/(1+INTERLACE_MODE));
+		LINES_F0 = 628;
+		LINES_F1 = 628;
+		FRONT_PORCH = 40;
+		HSYNC_PIXELS = 128;
+		BACK_PORCH = 88;
+		VSYNC_LINES = 4;
+		SOF_LINES = 23;
+		break;
+	case HDMIV_640x480p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (640*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (480/(1+INTERLACE_MODE));
+		LINES_F0 = 525;
+		LINES_F1 = 525;
+		FRONT_PORCH = 16;
+		HSYNC_PIXELS = 96;
+		BACK_PORCH = 48;
+		VSYNC_LINES = 2;
+		SOF_LINES = 33;
+		break;
+	case HDMIV_480x320p60hz:
+		INTERLACE_MODE = 0;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (480*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (320/(1+INTERLACE_MODE));
+		LINES_F0 = 263;
+		LINES_F1 = 263;
+		FRONT_PORCH = 120;
+		HSYNC_PIXELS = 100;
+		BACK_PORCH = 100;
+		VSYNC_LINES = 4;
+		SOF_LINES = 95;
+		break;
+	case HDMIV_1920x1200p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1200/(1+INTERLACE_MODE));
+		LINES_F0 = 1235;
+		LINES_F1 = 1235;
+		FRONT_PORCH = 48;
+		HSYNC_PIXELS = 32;
+		BACK_PORCH = 80;
+		VSYNC_LINES = 6;
+		SOF_LINES = 26;
+		break;
+	case HDMIV_2560x1600p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1600/(1+INTERLACE_MODE));
+		LINES_F0 = 1646;
+		LINES_F1 = 1646;
+		FRONT_PORCH = 48;
+		HSYNC_PIXELS = 32;
+		BACK_PORCH = 80;
+		VSYNC_LINES = 6;
+		SOF_LINES = 38;
+		break;
+	case HDMIV_2560x1440p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1440/(1+INTERLACE_MODE));
+		LINES_F0 = 1481;
+		LINES_F1 = 1481;
+		FRONT_PORCH = 48;
+		HSYNC_PIXELS = 32;
+		BACK_PORCH = 80;
+		VSYNC_LINES = 5;
+		SOF_LINES = 34;
+		break;
+	case HDMIV_2560x1080p60hz:
+		INTERLACE_MODE = 0U;
+		PIXEL_REPEAT_VENC = 0;
+		PIXEL_REPEAT_HDMI = 0;
+		ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
+		ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
+		LINES_F0 = 1111;
+		LINES_F1 = 1111;
+		FRONT_PORCH = 64;
+		HSYNC_PIXELS = 64;
+		BACK_PORCH = 96;
+		VSYNC_LINES = 10;
+		SOF_LINES = 18;
+		break;
 	default:
 		break;
 	}
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c
index 0d1786182f..9d7e1a6ed6 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c
@@ -615,6 +615,397 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
 	{MREG_END_MARKER, 0},
 };
 
+/* VESA modes */
+static const struct reg_t tvregs_vesa_800x480p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0},
+	{P_ENCI_VIDEO_EN, 0},
+
+	{P_ENCP_VIDEO_MODE, 0x4040},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x3DF},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x1F3},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0xA8},
+	{P_ENCP_VIDEO_HAVON_END, 0x3C7},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x11},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x1F0},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0},
+	{P_ENCP_VIDEO_HSO_END, 0x48},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E},
+	{P_ENCP_VIDEO_VSO_END, 0x32},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x7},
+
+	{P_ENCP_VIDEO_EN, 1},
+	{P_ENCI_VIDEO_EN, 0},
+	{MREG_END_MARKER, 0},
+};
+
+static const struct reg_t tvregs_vesa_1024x600p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x53F,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x27D,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x128,},
+	{P_ENCP_VIDEO_HAVON_END, 0x527,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x27A,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x88,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_1600x1200p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x7FF,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x4F5,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x1A0,},
+	{P_ENCP_VIDEO_HAVON_END, 0x7DF,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x3C,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x4EB,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0xA0,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x8,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_1600x900p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x707,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x3E7,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0xB0,},
+	{P_ENCP_VIDEO_HAVON_END, 0x6EF,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x63,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x3E6,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x50,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_1440x900p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x76F,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x3A5,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x180,},
+	{P_ENCP_VIDEO_HAVON_END, 0x71F,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x1F,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x3A2,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x98,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_1360x768p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x6FF,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x31A,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x170,},
+	{P_ENCP_VIDEO_HAVON_END, 0x6BF,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x18,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x317,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x70,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_1280x1024p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x697,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x429,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x168,},
+	{P_ENCP_VIDEO_HAVON_END, 0x667,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x29,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x428,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x70,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
+
+	{P_ENCI_VIDEO_EN, 0},
+	{P_ENCP_VIDEO_EN, 1},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_1280x800p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x59F,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x336,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
+	{P_ENCP_VIDEO_HAVON_END, 0x56F,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x14,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x333,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x20,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+	{P_ENCI_VIDEO_EN, 0},
+	{P_ENCP_VIDEO_EN, 1},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_1024x768p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x53F,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x325,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x128,},
+	{P_ENCP_VIDEO_HAVON_END, 0x527,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x322,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x88,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_800x600p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x41F,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x273,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,},
+	{P_ENCP_VIDEO_HAVON_END, 0x3F7,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x1B,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x272,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x80,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x4,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_640x480p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x31F,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x20C,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x90,},
+	{P_ENCP_VIDEO_HAVON_END, 0x30F,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x202,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x60,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x2,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_480x320p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+	{P_ENCP_VIDEO_MAX_PXCNT, 0x31F,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 0x20C,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 0x64,},
+	{P_ENCP_VIDEO_HAVON_END, 0x243,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 0xBD,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 0x1FC,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+	{P_ENCP_VIDEO_HSO_END, 0x64,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x8,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_1920x1200p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+	{P_ENCP_VIDEO_MAX_PXCNT,   2079,},
+	{P_ENCP_VIDEO_MAX_LNCNT,   1234,},
+	{P_ENCP_VIDEO_HAVON_BEGIN,  112,},
+	{P_ENCP_VIDEO_HAVON_END,   2031,},
+	{P_ENCP_VIDEO_VAVON_BLINE,   32,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 1231,},
+	{P_ENCP_VIDEO_HSO_BEGIN,      0,},
+	{P_ENCP_VIDEO_HSO_END,       48,},
+	{P_ENCP_VIDEO_VSO_BEGIN,   0x1E,},
+	{P_ENCP_VIDEO_VSO_END,     0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE,      0,},
+	{P_ENCP_VIDEO_VSO_ELINE,      6,},
+
+	{P_ENCP_DACSEL_0, 0x0543,},
+	{P_ENCP_DACSEL_1, 0x0000,},
+	{P_ENCI_VIDEO_EN, 0},
+	{P_ENCP_VIDEO_EN, 1},
+	{MREG_END_MARKER, 0}
+};
+
+static const struct reg_t tvregs_vesa_2560x1600p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+	{P_ENCP_VIDEO_MAX_PXCNT, 2719,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 1645,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 80,},
+	{P_ENCP_VIDEO_HAVON_END, 2639,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 38,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 1637,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0,},
+	{P_ENCP_VIDEO_HSO_END, 32,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0},
+};
+
+static const struct reg_t tvregs_vesa_2560x1440p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+	{P_ENCP_VIDEO_MAX_PXCNT, 2719,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 1480,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 80,},
+	{P_ENCP_VIDEO_HAVON_END, 2639,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 34,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 1473,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0,},
+	{P_ENCP_VIDEO_HSO_END, 32,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0x5,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0},
+};
+
+static const struct reg_t tvregs_vesa_2560x1080p60hz[] = {
+	{P_ENCP_VIDEO_EN, 0,},
+	{P_ENCI_VIDEO_EN, 0,},
+
+	{P_ENCP_VIDEO_MODE, 0x4040,},
+	{P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+	{P_ENCP_VIDEO_MAX_PXCNT, 2783,},
+	{P_ENCP_VIDEO_MAX_LNCNT, 1110,},
+	{P_ENCP_VIDEO_HAVON_BEGIN, 96,},
+	{P_ENCP_VIDEO_HAVON_END, 2655,},
+	{P_ENCP_VIDEO_VAVON_BLINE, 18,},
+	{P_ENCP_VIDEO_VAVON_ELINE, 1097,},
+	{P_ENCP_VIDEO_HSO_BEGIN, 0,},
+	{P_ENCP_VIDEO_HSO_END, 64,},
+	{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+	{P_ENCP_VIDEO_VSO_END, 0x32,},
+	{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+	{P_ENCP_VIDEO_VSO_ELINE, 0xa,},
+
+	{P_ENCP_VIDEO_EN, 1,},
+	{P_ENCI_VIDEO_EN, 0,},
+	{MREG_END_MARKER, 0},
+};
+
 struct vic_tvregs_set {
 	enum hdmi_vic vic;
 	const struct reg_t *reg_setting;
@@ -653,6 +1044,22 @@ static struct vic_tvregs_set tvregsTab[] = {
 	{HDMI_3840x2160p50_16x9, tvregs_4k2k_25hz},
 	{HDMI_3840x2160p60_16x9_Y420, tvregs_4k2k_30hz},
 	{HDMI_3840x2160p50_16x9_Y420, tvregs_4k2k_25hz},
+	{HDMIV_800x480p60hz, tvregs_vesa_800x480p60hz},
+	{HDMIV_1024x600p60hz, tvregs_vesa_1024x600p60hz},
+	{HDMIV_1600x1200p60hz, tvregs_vesa_1600x1200p60hz},
+	{HDMIV_1600x900p60hz, tvregs_vesa_1600x900p60hz},
+	{HDMIV_1440x900p60hz, tvregs_vesa_1440x900p60hz},
+	{HDMIV_1360x768p60hz, tvregs_vesa_1360x768p60hz},
+	{HDMIV_1280x1024p60hz, tvregs_vesa_1280x1024p60hz},
+	{HDMIV_1280x800p60hz, tvregs_vesa_1280x800p60hz},
+	{HDMIV_1024x768p60hz, tvregs_vesa_1024x768p60hz},
+	{HDMIV_800x600p60hz, tvregs_vesa_800x600p60hz},
+	{HDMIV_640x480p60hz, tvregs_vesa_640x480p60hz},
+	{HDMIV_480x320p60hz, tvregs_vesa_480x320p60hz},
+	{HDMIV_1920x1200p60hz, tvregs_vesa_1920x1200p60hz},
+	{HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz},
+	{HDMIV_2560x1440p60hz, tvregs_vesa_2560x1440p60hz},
+	{HDMIV_2560x1080p60hz, tvregs_vesa_2560x1080p60hz},
 };
 
 static inline void setreg(const struct reg_t *r)