uboot: update ddr and emmc driver. [1/3]

6a2a443 storage: mmc/nand: support support to read saved ddr parameter [1/1]
cb80c6c uboot: emmc: setup emmc hs400 debug environment in uboot [1/1]
9927af4 ddr: timing:G12A/G12B/TL1/TM2 update LPDDR4_PHY_V_0_1_14 bl33 [2/3]
c9dfa59 ddr: driver:G12A/G12B/TL1 update LPDDR4_PHY_V_0_1_13 bl33 [2/3]
ac463ed ddr: timing:G12A/G12B/TL1_update_LPDDR4_PHY_V_0_1_12_bl33 [2/3]
3fead4a dram: scramble: update scramble key config [2/2]

dram: scramble: update scramble key config [2/2]

PD#SWPL-3152

Problem:
can not configure non-sec memory scramble key in uboot

Solution:
add config interface in ddr function

Verity:
test pass on u200/w400/x301

Change-Id: Ie987ecc336483518913dc3cb850cbe04d348720e
Signed-off-by: xiaobo gu <xiaobo.gu@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>

ddr: timing:G12A/G12B/TL1_update_LPDDR4_PHY_V_0_1_12_bl33 [2/3]

PD#SWPL-5973

Problem:
none

Solution:
DDR_DRIVER_VERSION   "LPDDR4_PHY_V_0_1_12"     20190128
1      reduice funciton  ddr_init_soc_calculate_impedence_ctrl code size
2      modify ddr4 DqDqsRcvCntrl register for swith to extend vref range
       improve vref training
3      adjust 16bit lpddr4 dfi mode register and DMC_DRAM_DFI_CTRL
       register for 16bit test
4      change ddr scramble to after exter_ddrtest
5      add amlogic vref correction function
6      combine g12 rev-a and rev-b
7      repair tl1 ddr3 autosize function
8      config cfg_ddr_dqs=5 improve rank switch speed
9      change ddr4 rtt_park to 0  for ddr4 dqs level will increase vddq power
10     add fail_pass_ddr test method
11     disable asr only apd after ddrtest
12     add ddr_fast_boot function
13     add lpddr4 fast boot vt function

Verify:
test pass at x301

Change-Id: I19c0100cd08990854ab1f006d5e7060e7c2cc1bf
Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>

ddr: driver:G12A/G12B/TL1 update LPDDR4_PHY_V_0_1_13 bl33 [2/3]

PD#SWPL-7341

Problem:
none.

Solution:
DDR_DRIVER_VERSION   "LPDDR4_PHY_V_0_1_13"     20190417
1      add ddr_fast_boot data sha2 checksum
2      repair ddr reinit training all use for auto frequency scan
3      adjust tl1 bl2 stack link
4      reparir cs0 4GB support ,limit ddr addtest <=3928M
5      change tl1 board id to ddr id

Verify:
test pass at x301 and u200.

Change-Id: I582fc6b67d6b565ef260b9bc4c144425ece95cc4
Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com>

ddr: timing:G12A/G12B/TL1/TM2 update LPDDR4_PHY_V_0_1_14 bl33 [2/3]

PD#SWPL-7880

Problem:
none.

Solution:
DDR_DRIVER_VERSION   "LPDDR4_PHY_V_0_1_14"     20190426
1      add soc window vref offset function
2      add  usb_download_full test function
3      repair lpddr4 CA delay offset function
4      repair  suspend resume test command
5      2400 ddr4 change cl from 16 to 18. compatibility new JEDEC
6      add dfi_mrl max value limmit
7      change lpddr4 init soc vref value

Verify:
test pass at T309,U200,W400.

Change-Id: Ie92971f4a009511b72b22eea6dba56c461438d2b
Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>

uboot: emmc: setup emmc hs400 debug environment in uboot [1/1]

PD#SWPL-1265

Problem:
HS400 enviroment is too complexity to debug

Solution:
setup HS400 environment in uboot

Verify:
verify on tl1_skt

Change-Id: Iddc3ec8bdad496baf5792457d5417fe06ac3ce9b
Signed-off-by: Ruixuan Li <ruixuan.li@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>

storage: mmc/nand: support support to read saved ddr parameter [1/1]

PD#SWPL-5550

Problem:
Implement to the function that can read ddr
parameter which saved in reserved area.

Solution:
provide interface.

Verify:
tl1-x301
axg-s400

Change-Id: I68a0a83ac435ad6d4a11e01edc290aedae650941
Signed-off-by: Liang Yang <liang.yang@amlogic.com>
Signed-off-by: Qiang Li <qiang.li@amlogic.com>
Signed-off-by: Liang Yang <liang.yang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>

4 files changed, 28 insertions, 10 deletions

diff --git a/arch/arm/include/asm/arch-g12a/ddr_define.h b/arch/arm/include/asm/arch-g12a/ddr_define.h
index ca44a90615..f13f5e18e7 100644
--- a/arch/arm/include/asm/arch-g12a/ddr_define.h
+++ b/arch/arm/include/asm/arch-g12a/ddr_define.h
@@ -83,6 +83,8 @@
 				(chl_set == CONFIG_DDR0_16BIT))
 #define DDR_USE_2_RANK(chl_set)	((chl_set == CONFIG_DDR0_RANK01))
 
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
 /* DMC_DDR_CTRL defines */
 #define DDR_DDR4_ENABLE						(1<<22)
 #define DDR_RANK1_ENABLE					(1<<21)
diff --git a/arch/arm/include/asm/arch-g12a/timing.h b/arch/arm/include/asm/arch-g12a/timing.h
index de9da4950e..7170cbb210 100644
--- a/arch/arm/include/asm/arch-g12a/timing.h
+++ b/arch/arm/include/asm/arch-g12a/timing.h
@@ -73,7 +73,8 @@ typedef struct ddr_reg {
 
 typedef struct ddr_set{
 	unsigned	int		magic;
-	unsigned	int		rsv_int0;
+	unsigned	char	fast_boot[4];// 0   fastboot enable  1 window test margin  2 auto offset after window test 3 auto window test
+	//unsigned	int		rsv_int0;
 	unsigned	char	board_id;
 	//board id reserve,,do not modify
 	unsigned	char	version;
@@ -131,7 +132,9 @@ typedef struct ddr_set{
 
 	unsigned	short	training_SequenceCtrl[2];
 	//system reserve,do not modify
-	unsigned	char	phy_odt_config_rank[4];
+	unsigned	char	phy_odt_config_rank[2];
+	unsigned	char	 rever1;
+	unsigned	char	 rever2;
 	//training odt config ,only use for training
 	// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
 	// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
@@ -232,7 +235,7 @@ typedef struct ddr_set{
 	unsigned	char	dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
 	unsigned	char	slt_test_function[2];  //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,[1],slt test parameter ,use for force delay line offset
 		//system reserve,do not modify
-	unsigned	short	dq_bdlr_org;
+	unsigned	short	tdqs2dq;
 	unsigned	char  dram_data_wr_odt_ohm;
 	unsigned	char	bitTimeControl_2d;
 	//system reserve,do not modify
@@ -251,7 +254,7 @@ typedef struct ddr_set{
 	//system reserve,do not modify
 	/* align8 */
 
-	unsigned	long	rsv_long0[2];
+	//unsigned	long	rsv_long0[2];
 	/* v1 end */
 	//unsigned	char	read_dqs_adjust[16]; //rank 0 --lane 0 1 2 3  rank 1--4 5 6 7 write  //rank 0 --lane 0 1 2 3  rank 1--4 5 6 7 read
 	//unsigned	char	read_dq_bit_delay[72];
@@ -262,10 +265,13 @@ typedef struct ddr_set{
 	unsigned	short	write_dqs_delay[16];
 	unsigned	short	write_dq_bit_delay[72];
 	unsigned	short	read_dqs_gate_delay[16];
-	unsigned	char	dq_dqs_delay_flag; //read_dqs  read_dq,write_dqs, write_dq
+	unsigned	char	soc_bit_vref[32];
+	unsigned	char	dram_bit_vref[32];
+	unsigned	char	rever3;//read_dqs  read_dq,write_dqs, write_dq
 	unsigned	char	dfi_mrl;
 	unsigned	char	dfi_hwtmrl;
 	unsigned	char	ARdPtrInitVal;
+	unsigned	char	retraining[16];
 	//override read bit delay
 }__attribute__ ((packed)) ddr_set_t;
 
diff --git a/arch/arm/include/asm/arch-g12b/ddr_define.h b/arch/arm/include/asm/arch-g12b/ddr_define.h
index 8b3578e582..3e8a6f0ef0 100644
--- a/arch/arm/include/asm/arch-g12b/ddr_define.h
+++ b/arch/arm/include/asm/arch-g12b/ddr_define.h
@@ -83,6 +83,8 @@
 				(chl_set == CONFIG_DDR0_16BIT))
 #define DDR_USE_2_RANK(chl_set)	((chl_set == CONFIG_DDR0_RANK01))
 
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
 /* DMC_DDR_CTRL defines */
 #define DDR_DDR4_ENABLE						(1<<22)
 #define DDR_RANK1_ENABLE					(1<<21)
diff --git a/arch/arm/include/asm/arch-g12b/timing.h b/arch/arm/include/asm/arch-g12b/timing.h
index cd1002ead9..4124457bf5 100644
--- a/arch/arm/include/asm/arch-g12b/timing.h
+++ b/arch/arm/include/asm/arch-g12b/timing.h
@@ -73,7 +73,8 @@ typedef struct ddr_reg {
 
 typedef struct ddr_set{
 	unsigned	int		magic;
-	unsigned	int		rsv_int0;
+	unsigned	char	fast_boot[4];// 0   fastboot enable  1 window test margin  2 auto offset after window test 3 auto window test
+	//unsigned	int		rsv_int0;
 	unsigned	char	board_id;
 	//board id reserve,,do not modify
 	unsigned	char	version;
@@ -131,7 +132,9 @@ typedef struct ddr_set{
 
 	unsigned	short	training_SequenceCtrl[2];
 	//system reserve,do not modify
-	unsigned	char	phy_odt_config_rank[4];
+	unsigned	char	phy_odt_config_rank[2];
+	unsigned	char	 rever1;
+	unsigned	char	 rever2;
 	//training odt config ,only use for training
 	// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
 	// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
@@ -232,7 +235,7 @@ typedef struct ddr_set{
 	unsigned	char	dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
 	unsigned	char	slt_test_function[2];  //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,[1],slt test parameter ,use for force delay line offset
 		//system reserve,do not modify
-	unsigned	short	dq_bdlr_org;
+	unsigned	short	tdqs2dq;
 	unsigned	char  dram_data_wr_odt_ohm;
 	unsigned	char	bitTimeControl_2d;
 	//system reserve,do not modify
@@ -251,7 +254,7 @@ typedef struct ddr_set{
 	//system reserve,do not modify
 	/* align8 */
 
-	unsigned	long	rsv_long0[2];
+	//unsigned	long	rsv_long0[2];
 	/* v1 end */
 	//unsigned	char	read_dqs_adjust[16]; //rank 0 --lane 0 1 2 3  rank 1--4 5 6 7 write  //rank 0 --lane 0 1 2 3  rank 1--4 5 6 7 read
 	//unsigned	char	read_dq_bit_delay[72];
@@ -260,12 +263,17 @@ typedef struct ddr_set{
 	unsigned	char	read_dqs_delay[16];
 	unsigned	char	read_dq_bit_delay[72];
 	unsigned	short	write_dqs_delay[16];
+//*/
 	unsigned	short	write_dq_bit_delay[72];
 	unsigned	short	read_dqs_gate_delay[16];
-	unsigned	char	dq_dqs_delay_flag; //read_dqs  read_dq,write_dqs, write_dq
+	unsigned	char	soc_bit_vref[32];
+	unsigned	char	dram_bit_vref[32];
+//		/*
+	unsigned	char	rever3;//read_dqs  read_dq,write_dqs, write_dq
 	unsigned	char	dfi_mrl;
 	unsigned	char	dfi_hwtmrl;
 	unsigned	char	ARdPtrInitVal;
+	unsigned	char	retraining[16];
 	//override read bit delay
 }__attribute__ ((packed)) ddr_set_t;