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authorEvoke Zhang <evoke.zhang@amlogic.com>2019-03-13 15:04:09 +0800
committerDongjin Kim <tobetter@gmail.com>2019-05-16 13:18:21 +0900
commit7f269c30f3781a86e8b1116c6129a00e738107df (patch)
tree3bdd97d8aa51e4301b389e37aa7044a6ffedd374 /drivers
parentb4679589cb92ebb8e39e7f223f40093f9d52ab90 (diff)
downloadu-boot-odroid-c1-7f269c30f3781a86e8b1116c6129a00e738107df.tar.gz
vpu: add sm1 support [1/1]
PD#SWPL-5857 Problem: sm1 is a new chip Solution: add sm1 support for vpu driver Verify: pxp Change-Id: If132d69a6a27fd43981a23032256c477f78ea1f2 Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/vpu/aml_vpu.c40
-rw-r--r--drivers/vpu/aml_vpu.h3
-rw-r--r--drivers/vpu/aml_vpu_ctrl.h15
-rw-r--r--drivers/vpu/aml_vpu_power_init.c29
4 files changed, 80 insertions, 7 deletions
diff --git a/drivers/vpu/aml_vpu.c b/drivers/vpu/aml_vpu.c
index 2b85f86457..779ea1b5c4 100644
--- a/drivers/vpu/aml_vpu.c
+++ b/drivers/vpu/aml_vpu.c
@@ -34,7 +34,8 @@
/* v05: add axg support */
/* v06: add g12a support */
/* v20180925: add tl1 support */
-#define VPU_VERION "v20180925"
+/* v20190313: add sm1 support */
+#define VPU_VERION "v20190313"
#ifdef CONFIG_OF_LIBFDT
static char *dt_addr;
@@ -59,6 +60,7 @@ static struct vpu_data_s vpu_data_gxb = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_gxb,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
.module_init_table_cnt = 0,
@@ -76,6 +78,7 @@ static struct vpu_data_s vpu_data_gxtvbb = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_gxb,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
.module_init_table_cnt = 0,
@@ -93,6 +96,7 @@ static struct vpu_data_s vpu_data_gxl = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_gxb,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
.module_init_table_cnt = 0,
@@ -110,6 +114,7 @@ static struct vpu_data_s vpu_data_gxm = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_gxb,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
.module_init_table_cnt = sizeof(vpu_module_init_gxm) / sizeof(struct vpu_ctrl_s),
@@ -127,6 +132,7 @@ static struct vpu_data_s vpu_data_txl = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_gxb,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
.module_init_table_cnt = 0,
@@ -144,6 +150,7 @@ static struct vpu_data_s vpu_data_txlx = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_gxb,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
.module_init_table_cnt = sizeof(vpu_module_init_txlx) / sizeof(struct vpu_ctrl_s),
@@ -161,6 +168,7 @@ static struct vpu_data_s vpu_data_axg = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_axg,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
.module_init_table_cnt = 0,
@@ -178,6 +186,7 @@ static struct vpu_data_s vpu_data_txhd = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_txhd,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_txhd,
.module_init_table_cnt = 0,
@@ -195,6 +204,7 @@ static struct vpu_data_s vpu_data_g12a = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_g12a,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
.module_init_table_cnt = 0,
@@ -212,6 +222,7 @@ static struct vpu_data_s vpu_data_g12b = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_g12a,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
.module_init_table_cnt = 0,
@@ -229,12 +240,31 @@ static struct vpu_data_s vpu_data_tl1 = {
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_tl1,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_tl1,
.module_init_table_cnt = 0,
.module_init_table = NULL,
};
+static struct vpu_data_s vpu_data_sm1 = {
+ .chip_type = VPU_CHIP_SM1,
+ .chip_name = "sm1",
+ .clk_level_dft = CLK_LEVEL_DFT_G12A,
+ .clk_level_max = CLK_LEVEL_MAX_G12A,
+ .gp_pll_valid = 0,
+
+ .fclk_div_table = fclk_div_table_g12a,
+ .vpu_clk_table = vpu_clk_table,
+
+ .mem_pd_table = vpu_mem_pd_tl1,
+ .hdmi_iso_table = vpu_hdmi_iso_sm1,
+ .reset_table = vpu_reset_gx,
+
+ .module_init_table_cnt = 0,
+ .module_init_table = NULL,
+};
+
static void vpu_chip_detect(void)
{
#if 1
@@ -275,12 +305,15 @@ static void vpu_chip_detect(void)
case MESON_CPU_MAJOR_ID_TL1:
vpu_conf.data = &vpu_data_tl1;
break;
+ case MESON_CPU_MAJOR_ID_SM1:
+ vpu_conf.data = &vpu_data_sm1;
+ break;
default:
- vpu_conf.data = &vpu_data_tl1;
+ vpu_conf.data = &vpu_data_sm1;
break;
}
#else
- vpu_conf.data = &vpu_data_tl1;
+ vpu_conf.data = &vpu_data_sm1;
#endif
strcpy(vpu_conf.drv_version, VPU_VERION);
@@ -320,6 +353,7 @@ static int vpu_check(void)
case VPU_CHIP_G12A:
case VPU_CHIP_G12B:
case VPU_CHIP_TL1:
+ case VPU_CHIP_SM1:
ret = 0;
break;
default:
diff --git a/drivers/vpu/aml_vpu.h b/drivers/vpu/aml_vpu.h
index dc56b33070..72111f7476 100644
--- a/drivers/vpu/aml_vpu.h
+++ b/drivers/vpu/aml_vpu.h
@@ -38,6 +38,7 @@ enum vpu_chip_e {
VPU_CHIP_G12A, /* 8 */
VPU_CHIP_G12B, /* 9 */
VPU_CHIP_TL1, /* 10 */
+ VPU_CHIP_SM1, /* 11 */
VPU_CHIP_MAX,
};
@@ -45,6 +46,7 @@ enum vpu_chip_e {
#define VPU_REG_END 0xffff
#define VPU_MEM_PD_CNT_MAX 10
+#define VPU_HDMI_ISO_CNT_MAX 5
#define VPU_RESET_CNT_MAX 10
struct fclk_div_s {
@@ -82,6 +84,7 @@ struct vpu_data_s {
struct vpu_clk_s *vpu_clk_table;
struct vpu_ctrl_s *mem_pd_table;
+ struct vpu_ctrl_s *hdmi_iso_table;
struct vpu_reset_s *reset_table;
unsigned int module_init_table_cnt;
diff --git a/drivers/vpu/aml_vpu_ctrl.h b/drivers/vpu/aml_vpu_ctrl.h
index e71656b280..0099bd6832 100644
--- a/drivers/vpu/aml_vpu_ctrl.h
+++ b/drivers/vpu/aml_vpu_ctrl.h
@@ -163,6 +163,21 @@ static struct vpu_ctrl_s vpu_mem_pd_tl1[] = {
};
/* ******************************************************* */
+/* VPU_HDMI ISO */
+/* ******************************************************* */
+static struct vpu_ctrl_s vpu_hdmi_iso_gxb[] = {
+ /* reg, val, bit, len */
+ {AO_RTI_GEN_PWR_SLEEP0, 1, 9, 1},
+ {VPU_REG_END, 0, 0, 0},
+};
+
+static struct vpu_ctrl_s vpu_hdmi_iso_sm1[] = {
+ /* reg, val, bit, len */
+ {AO_RTI_GEN_PWR_ISO0, 1, 8, 1},
+ {VPU_REG_END, 0, 0, 0},
+};
+
+/* ******************************************************* */
/* VPU module init table */
/* ******************************************************* */
static struct vpu_ctrl_s vpu_module_init_gxm[] = {
diff --git a/drivers/vpu/aml_vpu_power_init.c b/drivers/vpu/aml_vpu_power_init.c
index 6c9dc84134..462bf52039 100644
--- a/drivers/vpu/aml_vpu_power_init.c
+++ b/drivers/vpu/aml_vpu_power_init.c
@@ -69,7 +69,7 @@ void vpu_power_on(void)
{
struct vpu_ctrl_s *ctrl_table;
struct vpu_reset_s *reset_table;
- unsigned int _reg, _start, _end, mask;
+ unsigned int _reg, _start, _end, _len, mask;
int i = 0, j;
/* power up memories */
@@ -121,7 +121,17 @@ void vpu_power_on(void)
}
/* Remove VPU_HDMI ISO */
- vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 0, 9, 1); /* [9] VPU_HDMI */
+ ctrl_table = vpu_conf.data->hdmi_iso_table;
+ i = 0;
+ while (i < VPU_HDMI_ISO_CNT_MAX) {
+ if (ctrl_table[i].reg == VPU_REG_END)
+ break;
+ _reg = ctrl_table[i].reg;
+ _start = ctrl_table[i].bit;
+ _len = ctrl_table[i].len;
+ vpu_ao_setb(_reg, 0, _start, _len);
+ i++;
+ }
VPUPR("%s\n", __func__);
}
@@ -129,16 +139,27 @@ void vpu_power_on(void)
void vpu_power_off(void)
{
struct vpu_ctrl_s *ctrl_table;
- unsigned int _reg, _start, _end;
+ unsigned int _reg, _start, _end, _len, _val;
int i = 0, j;
/* Power down VPU_HDMI */
/* Enable Isolation */
- vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 1, 9, 1); /* ISO */
+ ctrl_table = vpu_conf.data->hdmi_iso_table;
+ while (i < VPU_HDMI_ISO_CNT_MAX) {
+ if (ctrl_table[i].reg == VPU_REG_END)
+ break;
+ _reg = ctrl_table[i].reg;
+ _val = ctrl_table[i].val;
+ _start = ctrl_table[i].bit;
+ _len = ctrl_table[i].len;
+ vpu_ao_setb(_reg, _val, _start, _len);
+ i++;
+ }
udelay(20);
/* power down memories */
ctrl_table = vpu_conf.data->mem_pd_table;
+ i = 0;
while (i < VPU_MEM_PD_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;