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| author | Chin Liang See <clsee@altera.com> | 2014-06-02 16:52:35 +0800 |
|---|---|---|
| committer | Chin Liang See <clsee@altera.com> | 2014-06-02 16:52:35 +0800 |
| commit | 1c0168bcc067cd9941becef3671884361abd9922 (patch) | |
| tree | 42a4e941f0ae9cab8017c7950f7ac053211fc8a3 | |
| parent | 9c3ced745ef48786355516bcf8d5b945a558f492 (diff) | |
| download | u-boot-socfpga-1c0168bcc067cd9941becef3671884361abd9922.tar.gz | |
FogBugz #208110: Fix the L4 clock calculation algorithm
To fix the L4 clock calculation algorithm as the L4 divider
in value of power of 2 instead divisor itself.
Signed-off-by: Chin Liang See <clsee@altera.com>
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/clock_manager.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index 8e4e556d89..62a27832bc 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -583,7 +583,7 @@ unsigned long cm_get_l4_sp_clk_hz(void) /* get the L4 SP clock which supplied to UART */ reg = readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLLGRP_MAINDIV_ADDRESS); reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg); - clock = clock / (reg + 1); + clock = clock / (1 << reg); return clock; } |