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authorLey Foon Tan <ley.foon.tan@intel.com>2020-11-26 12:01:09 +0800
committerLey Foon Tan <ley.foon.tan@intel.com>2020-11-26 12:01:09 +0800
commit3adc2a32e299cbd92a6d735c5f0e72adb59a4606 (patch)
tree631d70c093b457438e324623e80b6a75b405f4b3
parentccdd2dd28c759c2a40504eb0eab38cc6467e26ac (diff)
downloadu-boot-socfpga-rel_socfpga_v2020.07_20.12.02_pr.tar.gz
HSD: #1508430891-5: doc: socfpga: Add secure region changerel_socfpga_v2020.07_20.12.02_pr
Add section 3.2 for SDRAM secure region update. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
-rw-r--r--doc/README.socfpga7
1 files changed, 7 insertions, 0 deletions
diff --git a/doc/README.socfpga b/doc/README.socfpga
index 4629bfd0e9..77d10e75f2 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -69,6 +69,13 @@ Table of Contents
Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key
+ 3.2 Support SDRAM secure region in U-boot-ATF flow
+
+ First 1 MiB of SDRAM is configured as secure region, other
+ address spaces are non-secure regions. Only software executing
+ at secure state EL3 (eg: U-boot SPL) and secure masters are
+ allowed access to secure region.
+
4. Cyclone5 / Arria 5 generating the handoff header files for U-Boot SPL
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