diff options
| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2021-03-15 21:39:48 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2021-03-25 00:10:23 -0700 |
| commit | 77672ded4da6970b6c9bf72622432ae14c885785 (patch) | |
| tree | de622f817839b96b312b0c430038650bbe1d8c08 | |
| parent | 12c8f3f7c6b809b5ce785ba1958a980b32011435 (diff) | |
| download | u-boot-socfpga-77672ded4da6970b6c9bf72622432ae14c885785.tar.gz | |
arm: socfpga: Update system manager for n5x
Both SYSMGR_SOC64_HMC_CLK AND SYSMGR_SOC64_IO_PA_CTRL registers are
replaced by SYSMGR_SOC64_DDR_MODE in n5x. This patch updates the changes
in system manager for n5x.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
v1->v2
- Using #if IS_ENABLED(CONFIG ...) instead of #ifdef
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 9 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.c | 2 |
2 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index ef4dd747c1..f516d81b87 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2021 Intel Corporation <www.intel.com> */ #ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -31,8 +31,12 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_FPGAINTF_EN2 0x6c #define SYSMGR_SOC64_FPGAINTF_EN3 0x70 #define SYSMGR_SOC64_DMA_L3MASTER 0x74 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#define SYSMGR_SOC64_DDR_MODE 0xb8 +#else #define SYSMGR_SOC64_HMC_CLK 0xb4 #define SYSMGR_SOC64_IO_PA_CTRL 0xb8 +#endif #define SYSMGR_SOC64_NOC_TIMEOUT 0xc0 #define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 #define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 @@ -149,4 +153,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F +/* For n5x only */ +#define SYSMGR_SOC64_DDR_MODE_MSK BIT(0) + #endif /* _SYSTEM_MANAGER_SOC64_H_ */ diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 1e7d22e8f9..cda18bd71e 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -99,12 +99,14 @@ int emif_reset(struct altera_sdram_platdata *plat) return 0; } +#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_HMC_CLK), SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); } +#endif void sdram_clear_mem(phys_addr_t addr, phys_size_t size) { |