diff options
| author | Chin Liang See <clsee@altera.com> | 2013-08-07 13:51:41 -0700 |
|---|---|---|
| committer | Chin Liang See <clsee@altera.com> | 2013-08-08 10:56:33 -0700 |
| commit | e8b492bc75d100c0fa47a46cf947ec8ce20884df (patch) | |
| tree | cc10b6620bee37a7a8ccc860366eba4b118395b1 | |
| parent | e4115c160b67de2bfefb3cb5eed34d733a85de16 (diff) | |
| download | u-boot-socfpga-e8b492bc75d100c0fa47a46cf947ec8ce20884df.tar.gz | |
FogBugz #143274: Avoiding debug clk lower than JTAG clk
Revert the debug clock changes made due to FB136810.
With that changes, the debug clock is lower than the JTAG clk
of USB Blaster II. It cause the debugger connection error.
Signed-off-by: Chin Liang See <clsee@altera.com>
| -rw-r--r-- | board/altera/socfpga/pll_config.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h index 6ab53cc678..29730c75a9 100644 --- a/board/altera/socfpga/pll_config.h +++ b/board/altera/socfpga/pll_config.h @@ -18,9 +18,9 @@ #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) /* * To tell where is the clock source: * 0 = MAINPLL |