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| author | York Sun <yorksun@freescale.com> | 2015-11-04 10:03:18 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-12-13 18:27:27 -0800 |
| commit | 0fb7197436378eeb92ff8e2c6a6f6490b31eef1c (patch) | |
| tree | 827a9d0417f2b47790dedd4ebebaa68383d5219f | |
| parent | 19601dd99c8169e27457a96f03f0c3fef908a4c6 (diff) | |
| download | u-boot-0fb7197436378eeb92ff8e2c6a6f6490b31eef1c.tar.gz | |
driver/ddr/fsl: Update DDR4 MR6 for Vref range
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.
Signed-off-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | drivers/ddr/fsl/ctrl_regs.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 8543679108..36bf647791 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1186,6 +1186,9 @@ static void set_ddr_sdram_mode_10(const unsigned int ctrl_num, esdmode6 = ((tccdl_min - 4) & 0x7) << 10; + if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) + esdmode6 |= 1 << 6; /* Range 2 */ + ddr->ddr_sdram_mode_10 = (0 | ((esdmode6 & 0xffff) << 16) | ((esdmode7 & 0xffff) << 0) |