diff options
| author | Yangbo Lu <yangbo.lu@nxp.com> | 2020-10-20 11:04:51 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-11-28 10:39:44 +0800 |
| commit | 263ddfc3454ead3a988adef39b962479adce2b28 (patch) | |
| tree | ba219eb810f896950f258a61ed1fb9e2898f3d99 | |
| parent | da129170600e33bdcea1762ebe4ea0a2c9312a9e (diff) | |
| download | u-boot-263ddfc3454ead3a988adef39b962479adce2b28.tar.gz | |
mmc: fsl_esdhc: set sysctl register for clock initialization
The initial clock setting should be through sysctl register only,
while the mmc_set_clock() will call mmc_set_ios() introduce other
configurations like bus width, mode, and so on.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 642784e1f3..68130ee9f4 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -715,7 +715,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ - mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); + set_sysctl(priv, mmc, 400000); /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |