Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
  ARM: cache: Move the cp15 CR register read before flushing the cache.
  ARM: introduce arch_early_init_r()
  PXA: Enable CONFIG_PREBOOT on zipitz2
  ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
  No need to define CONFIG_ARCH_CPU_INIT.
  add new board vl_ma2sc
  MTD: SPEAr SMI: Add write support for length < 4 bytes
  i2c: designware_i2c.c: Add support for the "i2c probe" command
  rtc/m41t62: Add support for M41T82 with HT (Halt Update)
  SPL: ARM: spear: Add SPL support for SPEAr600 platform
  Makefile: Add u-boot.spr build target (SPEAr)
  SPL: ARM: spear: Remove some objects from SPL build
  SPL: lib/Makefile: Add crc32.c to SPL build
  SPL: common/Makefile: Add image.c to SPL build
  arm: Don't use printf() in SPL builds
  GPIO: Add SPEAr GPIO driver
  net: Multiple updates/enhancements to designware.c
  cleanup/SPEAr: Define configuration flags more elegantly
  cleanup/SPEAr: Remove unnecessary parenthesis
  SPEAr: Correct SoC ID offset in misc configuration space
  SPEAr: explicitly select clk src for UART
  SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
  SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
  SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
  SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
  SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
  SPEAr: Enable dcache for fast file transfer
  SPEAr: Enable autoneg for ethernet
  SPEAr: Enable udc and usb-console support only for usbtty configuration
  SPEAr: Enable usb device high speed support
  SPEAr: Initialize SNOR in early_board_init_f
  SPEAr: Change the default environment variables
  SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
  SPEAr: Add configuration options for spear3xx and spear6xx boards
  SPEAr: Add basic arch related support for SPEAr SoCs
  SPEAr: Add interface information in initialization
  SPEAr: Add macb driver support for spear310 and spear320
  SPEAr: Configure network support for spear SoCs
  SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
  SPEAr: Eliminate dependency on Xloader table
  SPEAr: Fix ARM relocation support
  st_smi: Fixed page size for Winbond W25Q128FV flash
  st_smi: Change timeout loop implementation
  st_smi: Fix bug in flash_print_info()
  st_smi: Change the flash probing method
  st_smi: Removed no needed dependency on ST_M25Pxx_ID
  st_smi: Fix smi read status
  st_smi: Move status register read before modifying ctrl register
  st_smi: Read status until timeout happens
  st_smi: Enhance the error handling
  st_smi: Change SMI timeout values
  st_smi: Return error in case TFF is not set
  st_smi: Add support for SPEAr SMI driver
  mtd/NAND: Remove obsolete SPEAr specific NAND drivers
  SPEAr: Configure FSMC driver for NAND interface
  mtd/NAND: Add FSMC driver support
  arm/km: remove calls to kw_gpio_* in board_early_init_f
  arm/km: add implementation for read_dip_switch
  arm/km: support the 2 PCIe fpga resets
  arm/km: skip FPGA config when already configured
  arm/km: redefine piggy 4 reg names to avoid conflicts
  arm/km: cleanup km_kirkwood boards
  arm/km: enable BOCO2 FPGA download support
  arm/km: remove portl2.h and use km_kirkwood instead
  arm/km: convert mgcoge3un target to km_kirkwood
  arm/km: add kmcoge5un board support
  arm/km: add kmnusa board support
  arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
  cm-t35: fix incorrect NAND_ECC layout selection
  ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
  ARM: OMAP4/5: Move USB pads to essential list.
  ARM: OMAP4/5: Move USB clocks to essential group.
  ARM: OMAP4/5: Move gpmc clocks to essential group.
  ARM: OMAP4+: Move external phy initialisations to arch specific place.
  omap4: Use a smaller M,N couple for IVA DPLL
  da850/omap-l138: Enable auto negotiation in RMII mode
  omap: am33xx: accomodate input clocks other than 24 Mhz
  omap: emif: fix bug in manufacturer code test
  omap: emif: deal with rams that return duplicate mr data on all byte lanes
  OMAP4+: Force DDR in self-refresh after warm reset
  OMAP4+: Handle sdram init after warm reset
  ARM: OMAP3+: Detect reset type
  arm: bugfix: Move vector table before jumping relocated code
  Kirkwood: Add support for Ka-Ro TK71
  arm/km: use spi claim bus to switch between SPI and NAND
  arm/kirkwood: protect the ENV_SPI #defines
  ARM: don't probe PHY address for LaCie boards
  lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
  lacie_kw: fix SDRAM banks number for net2big_v2
  Kirkwood: add lschlv2 and lsxhl board support
  net: add helper to generate random mac address
  net: use common rand()/srand() functions
  lib: add rand() function
  kwboot: boot kirkwood SoCs over a serial link
  kw_spi: add weak functions board_spi_claim/release_bus
  kw_spi: support spi_claim/release_bus functions
  kw_spi: backup and reset the MPP of the chosen CS pin
  kirkwood: fix calls to kirkwood_mpp_conf
  kirkwood: add save functionality kirkwood_mpp_conf function
  km_arm: use filesize for erase in update command
  arm/km: enable mii cmd
  arm/km: remove CONFIG_RESET_PHY_R
  arm/km: change maintainer for mgcoge3un
  arm/km: fix wrong comment in SDRAM config for mgcoge3un
  arm/km: use ARRAY_SIZE macro
  arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
  arm/km: add piggy mac adress offset for mgcoge3un
  arm/km: add board type to boards.cfg
  AT91SAM9*: Change kernel address in dataflash to match u-boot's size
  ATMEL/PIO: Enable new feature of PIO on Atmel device
  ehci-atmel: fix compiler warning
  AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
  Atmel : usb : add EHCI driver for Atmel SoC
  Fix: AT91SAM9263 nor flash usage
  Fix: broken boot message at serial line on AT91SAM9263-EK board
  i.MX6 USDHC: Use the ESDHC clock
  mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
  i.MX28: Add function to adjust memory parameters
  mx28evk: Fix PSWITCH key position
  mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
  mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
  imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove unused CONFIG_MII_GASKET
  mx6: Avoid writing to read-only bits in imximage.cfg
  m28evk: use same notation to alloc the 128kB stack
  ...

Signed-off-by: Wolfgang Denk <wd@denx.de>

39 files changed, 2338 insertions, 132 deletions

diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
index 5b39484501..0e45426fbc 100644
--- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
@@ -523,9 +523,8 @@ VTPLock:
 
 	ldr	r6, DDRVTPR
 	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	and	r8, r7, $0x3e0
-	orr	r8, r7, r8
+	mov	r8, r7, LSL #32-10
+	mov	r8, r8, LSR #32-10        /* grab low 10 bits  */
 	ldr	r7, VTP_RECAL
 	orr	r8, r7, r8
 	ldr	r7, VTP_EN
@@ -644,7 +643,7 @@ VTP_LOCK_COUNT:
 VTP_MASK:
 	.word	0xffffdfff
 VTP_RECAL:
-	.word	0x40000
+	.word	0x08000
 VTP_EN:
 	.word	0x02000
 CFGTEST:
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
index 3da6c98d11..03eb2de520 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
@@ -31,7 +31,7 @@ static u32 kirkwood_variant(void)
 #define MPP_CTRL(i)	(KW_MPP_BASE + (i* 4))
 #define MPP_NR_REGS	(1 + MPP_MAX/8)
 
-void kirkwood_mpp_conf(u32 *mpp_list)
+void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save)
 {
 	u32 mpp_ctrl[MPP_NR_REGS];
 	unsigned int variant_mask;
@@ -52,6 +52,7 @@ void kirkwood_mpp_conf(u32 *mpp_list)
 	while (*mpp_list) {
 		unsigned int num = MPP_NUM(*mpp_list);
 		unsigned int sel = MPP_SEL(*mpp_list);
+		unsigned int sel_save;
 		int shift;
 
 		if (num > MPP_MAX) {
@@ -66,6 +67,13 @@ void kirkwood_mpp_conf(u32 *mpp_list)
 		}
 
 		shift = (num & 7) << 2;
+
+		if (mpp_save) {
+			sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf;
+			*mpp_save = num | (sel_save << 8) | variant_mask;
+			mpp_save++;
+		}
+
 		mpp_ctrl[num / 8] &= ~(0xf << shift);
 		mpp_ctrl[num / 8] |= sel << shift;
 
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
index a82ff2564b..ff25772099 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -153,7 +153,6 @@ int arch_misc_init(void)
 }
 #endif
 
-#ifdef	CONFIG_ARCH_CPU_INIT
 int arch_cpu_init(void)
 {
 	struct mx28_clkctrl_regs *clkctrl_regs =
@@ -187,7 +186,6 @@ int arch_cpu_init(void)
 
 	return 0;
 }
-#endif
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index 9fa5d29e6c..e17a4d7c7f 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -82,10 +82,18 @@ uint32_t dram_vals[] = {
 	0x00000000, 0x00010001
 };
 
+void __mx28_adjust_memory_params(uint32_t *dram_vals)
+{
+}
+void mx28_adjust_memory_params(uint32_t *dram_vals)
+	__attribute__((weak, alias("__mx28_adjust_memory_params")));
+
 void init_m28_200mhz_ddr2(void)
 {
 	int i;
 
+	mx28_adjust_memory_params(dram_vals);
+
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index f32ec4ccf3..d06f03d080 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -25,16 +25,27 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	:= reset.o \
+COBJS-y	:= cpu.o \
+	   reset.o \
 	   timer.o
-SOBJS	:=
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= spl.o spl_boot.o
+COBJS-$(CONFIG_SPEAR600) += spear600.o
+COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
+COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+endif
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+SRCS	:= $(START:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
 
 #########################################################################
 
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
new file mode 100644
index 0000000000..e299de3137
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+
+int arch_cpu_init(void)
+{
+	struct misc_regs *const misc_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 periph1_clken, periph_clk_cfg;
+
+	periph1_clken = readl(&misc_p->periph1_clken);
+
+#if defined(CONFIG_SPEAR3XX)
+	periph1_clken |= MISC_GPT2ENB;
+#elif defined(CONFIG_SPEAR600)
+	periph1_clken |= MISC_GPT3ENB;
+#endif
+
+#if defined(CONFIG_PL011_SERIAL)
+	periph1_clken |= MISC_UART0ENB;
+
+	periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
+	periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
+	periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+	writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
+#endif
+#if defined(CONFIG_DESIGNWARE_ETH)
+	periph1_clken |= MISC_ETHENB;
+#endif
+#if defined(CONFIG_DW_UDC)
+	periph1_clken |= MISC_USBDENB;
+#endif
+#if defined(CONFIG_DW_I2C)
+	periph1_clken |= MISC_I2CENB;
+#endif
+#if defined(CONFIG_ST_SMI)
+	periph1_clken |= MISC_SMIENB;
+#endif
+#if defined(CONFIG_NAND_FSMC)
+	periph1_clken |= MISC_FSMCENB;
+#endif
+
+	writel(periph1_clken, &misc_p->periph1_clken);
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+#ifdef CONFIG_SPEAR300
+	printf("CPU:   SPEAr300\n");
+#elif defined(CONFIG_SPEAR310)
+	printf("CPU:   SPEAr310\n");
+#elif defined(CONFIG_SPEAR320)
+	printf("CPU:   SPEAr320\n");
+#elif defined(CONFIG_SPEAR600)
+	printf("CPU:   SPEAr600\n");
+#else
+#error CPU not supported in spear platform
+#endif
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c
new file mode 100644
index 0000000000..ff52131b09
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spear600.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2000-2009
+ * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_defs.h>
+
+#define FALSE				0
+#define TRUE				(!FALSE)
+
+static void sel_1v8(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddr1v8, ddr2v5;
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000003;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000010;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
+		;
+}
+
+static void sel_2v5(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddr1v8, ddr2v5;
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000003;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000010;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
+		;
+}
+
+/*
+ * plat_ddr_init:
+ */
+void plat_ddr_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddrpad;
+	u32 core3v3, ddr1v8, ddr2v5;
+
+	/* DDR pad register configurations */
+	ddrpad = readl(&misc_p->ddr_pad);
+	ddrpad &= ~DDR_PAD_CNF_MSK;
+
+#if (CONFIG_DDR_HCLK)
+	ddrpad |= 0xEAAB;
+#elif (CONFIG_DDR_2HCLK)
+	ddrpad |= 0xEAAD;
+#elif (CONFIG_DDR_PLL2)
+	ddrpad |= 0xEAAD;
+#endif
+	writel(ddrpad, &misc_p->ddr_pad);
+
+	/* Compensation register configurations */
+	core3v3 = readl(&misc_p->core_3v3_compensation);
+	core3v3 &= 0x8080ffe0;
+	core3v3 |= 0x78000002;
+	writel(core3v3, &misc_p->core_3v3_compensation);
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000004;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000004;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
+		/* Software memory configuration */
+		if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
+			sel_1v8();
+		else
+			sel_2v5();
+	} else {
+		/* Hardware memory configuration */
+		if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
+			sel_1v8();
+		else
+			sel_2v5();
+	}
+}
+
+/*
+ * soc_init:
+ */
+void soc_init(void)
+{
+	/* Nothing to be done for SPEAr600 */
+}
+
+/*
+ * xxx_boot_selected:
+ *
+ * return TRUE if the particular booting option is selected
+ * return FALSE otherwise
+ */
+static u32 read_bootstrap(void)
+{
+	return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
+		& CONFIG_SPEAR_BOOTSTRAPMASK;
+}
+
+int snor_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (SNOR_BOOT_SUPPORTED) {
+		/* Check whether SNOR boot is selected */
+		if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
+			CONFIG_SPEAR_ONLYSNORBOOT)
+			return TRUE;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND8BOOT)
+			return TRUE;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND16BOOT)
+			return TRUE;
+	}
+
+	return FALSE;
+}
+
+int nand_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (NAND_BOOT_SUPPORTED) {
+		/* Check whether NAND boot is selected */
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND8BOOT)
+			return TRUE;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND16BOOT)
+			return TRUE;
+	}
+
+	return FALSE;
+}
+
+int pnor_boot_selected(void)
+{
+	/* Parallel NOR boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int usb_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (USB_BOOT_SUPPORTED) {
+		/* Check whether USB boot is selected */
+		if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
+			return TRUE;
+	}
+
+	return FALSE;
+}
+
+int tftp_boot_selected(void)
+{
+	/* TFTP boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int uart_boot_selected(void)
+{
+	/* UART boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int spi_boot_selected(void)
+{
+	/* SPI boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int i2c_boot_selected(void)
+{
+	/* I2C boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int mmc_boot_selected(void)
+{
+	return FALSE;
+}
+
+void plat_late_init(void)
+{
+	spear_late_init();
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
new file mode 100644
index 0000000000..48e6efbc47
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_syscntl.h>
+
+inline void hang(void)
+{
+	serial_puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+static void ddr_clock_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 clkenb, ddrpll;
+
+	clkenb = readl(&misc_p->periph1_clken);
+	clkenb &= ~PERIPH_MPMCMSK;
+	clkenb |= PERIPH_MPMC_WE;
+
+	/* Intentionally done twice */
+	writel(clkenb, &misc_p->periph1_clken);
+	writel(clkenb, &misc_p->periph1_clken);
+
+	ddrpll = readl(&misc_p->pll_ctr_reg);
+	ddrpll &= ~MEM_CLK_SEL_MSK;
+#if (CONFIG_DDR_HCLK)
+	ddrpll |= MEM_CLK_HCLK;
+#elif (CONFIG_DDR_2HCLK)
+	ddrpll |= MEM_CLK_2HCLK;
+#elif (CONFIG_DDR_PLL2)
+	ddrpll |= MEM_CLK_PLL2;
+#else
+#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
+#endif
+	writel(ddrpll, &misc_p->pll_ctr_reg);
+
+	writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
+			&misc_p->periph1_clken);
+}
+
+static void mpmc_init_values(void)
+{
+	u32 i;
+	u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+	u32 *mpmc_val_p = &mpmc_conf_vals[0];
+
+	for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
+		writel(*mpmc_val_p, mpmc_reg_p);
+
+	mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+
+	/*
+	 * MPMC controller start
+	 * MPMC waiting for DLLLOCKREG high
+	 */
+	writel(0x01000100, &mpmc_reg_p[7]);
+
+	while (!(readl(&mpmc_reg_p[3]) & 0x10000))
+		;
+}
+
+static void mpmc_init(void)
+{
+	/* Clock related settings for DDR */
+	ddr_clock_init();
+
+	/*
+	 * DDR pad register bits are different for different SoCs
+	 * Compensation values are also handled separately
+	 */
+	plat_ddr_init();
+
+	/* Initialize mpmc register values */
+	mpmc_init_values();
+}
+
+static void pll_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	/* Initialize PLLs */
+	writel(FREQ_332, &misc_p->pll1_frq);
+	writel(0x1C0A, &misc_p->pll1_cntl);
+	writel(0x1C0E, &misc_p->pll1_cntl);
+	writel(0x1C06, &misc_p->pll1_cntl);
+	writel(0x1C0E, &misc_p->pll1_cntl);
+
+	writel(FREQ_332, &misc_p->pll2_frq);
+	writel(0x1C0A, &misc_p->pll2_cntl);
+	writel(0x1C0E, &misc_p->pll2_cntl);
+	writel(0x1C06, &misc_p->pll2_cntl);
+	writel(0x1C0E, &misc_p->pll2_cntl);
+
+	/* wait for pll locks */
+	while (!(readl(&misc_p->pll1_cntl) & 0x1))
+		;
+	while (!(readl(&misc_p->pll2_cntl) & 0x1))
+		;
+}
+
+static void mac_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
+			&misc_p->periph1_clken);
+
+	writel(SYNTH23, &misc_p->gmac_synth_clk);
+
+	switch (get_socrev()) {
+	case SOC_SPEAR600_AA:
+	case SOC_SPEAR600_AB:
+	case SOC_SPEAR600_BA:
+	case SOC_SPEAR600_BB:
+	case SOC_SPEAR600_BC:
+	case SOC_SPEAR600_BD:
+		writel(0x0, &misc_p->gmac_ctr_reg);
+		break;
+
+	case SOC_SPEAR300:
+	case SOC_SPEAR310:
+	case SOC_SPEAR320:
+		writel(0x4, &misc_p->gmac_ctr_reg);
+		break;
+	}
+
+	writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
+			&misc_p->periph1_clken);
+
+	writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
+			&misc_p->periph1_rst);
+	writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
+			&misc_p->periph1_rst);
+}
+
+static void sys_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct syscntl_regs *syscntl_p =
+		(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+	/* Set system state to SLOW */
+	writel(SLOW, &syscntl_p->scctrl);
+	writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
+
+	/* Initialize PLLs */
+	pll_init();
+
+	/*
+	 * Ethernet configuration
+	 * To be done only if the tftp boot is not selected already
+	 * Boot code ensures the correct configuration in tftp booting
+	 */
+	if (!tftp_boot_selected())
+		mac_init();
+
+	writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
+	writel(0x555, &misc_p->amba_clk_cfg);
+
+	writel(NORMAL, &syscntl_p->scctrl);
+
+	/* Wait for system to switch to normal mode */
+	while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
+		!= NORMAL)
+		;
+}
+
+/*
+ * get_socrev
+ *
+ * Get SoC Revision.
+ * @return SOC_SPEARXXX
+ */
+int get_socrev(void)
+{
+#if defined(CONFIG_SPEAR600)
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 soc_id = readl(&misc_p->soc_core_id);
+	u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
+	u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
+
+	if ((pri_socid == 'B') && (sec_socid == 'B'))
+		return SOC_SPEAR600_BB;
+	else if ((pri_socid == 'B') && (sec_socid == 'C'))
+		return SOC_SPEAR600_BC;
+	else if ((pri_socid == 'B') && (sec_socid == 'D'))
+		return SOC_SPEAR600_BD;
+	else if (soc_id == 0)
+		return SOC_SPEAR600_BA;
+	else
+		return SOC_SPEAR_NA;
+#elif defined(CONFIG_SPEAR300)
+	return SOC_SPEAR300;
+#elif defined(CONFIG_SPEAR310)
+	return SOC_SPEAR310;
+#elif defined(CONFIG_SPEAR320)
+	return SOC_SPEAR320;
+#endif
+}
+
+void lowlevel_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	const char *u_boot_rev = U_BOOT_VERSION;
+
+	/* Initialize PLLs */
+	sys_init();
+
+	/* Initialize UART */
+	serial_init();
+
+	/* Print U-Boot SPL version string */
+	serial_puts("\nU-Boot SPL ");
+	/* Avoid a second "U-Boot" coming from this string */
+	u_boot_rev = &u_boot_rev[7];
+	serial_puts(u_boot_rev);
+	serial_puts(" (");
+	serial_puts(U_BOOT_DATE);
+	serial_puts(" - ");
+	serial_puts(U_BOOT_TIME);
+	serial_puts(")\n");
+
+#if defined(CONFIG_OS_BOOT)
+	writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
+			&misc_p->periph1_clken);
+#endif
+
+	/* Enable IPs (release reset) */
+	writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
+
+	/* Initialize MPMC */
+	serial_puts("Configure DDR\n");
+	mpmc_init();
+
+	/* SoC specific initialization */
+	soc_init();
+}
+
+void spear_late_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	writel(0x80000007, &misc_p->arb_icm_ml1);
+	writel(0x80000007, &misc_p->arb_icm_ml2);
+	writel(0x80000007, &misc_p->arb_icm_ml3);
+	writel(0x80000007, &misc_p->arb_icm_ml4);
+	writel(0x80000007, &misc_p->arb_icm_ml5);
+	writel(0x80000007, &misc_p->arb_icm_ml6);
+	writel(0x80000007, &misc_p->arb_icm_ml7);
+	writel(0x80000007, &misc_p->arb_icm_ml8);
+	writel(0x80000007, &misc_p->arb_icm_ml9);
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
new file mode 100644
index 0000000000..f2f9a4974e
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <image.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/arch/spr_defs.h>
+#include <linux/mtd/st_smi.h>
+
+static const char kernel_name[] = "Linux";
+static const char loader_name[] = "U-Boot";
+
+int image_check_header(image_header_t *hdr, const char *name)
+{
+	if (image_check_magic(hdr) &&
+	    (!strncmp(image_get_name(hdr), name, strlen(name))) &&
+	    image_check_hcrc(hdr)) {
+		return 1;
+	}
+	return 0;
+}
+
+int image_check_data(image_header_t *hdr)
+{
+	if (image_check_dcrc(hdr))
+		return 1;
+
+	return 0;
+}
+
+/*
+ * SNOR (Serial NOR flash) related functions
+ */
+void snor_init(void)
+{
+	struct smi_regs *const smicntl =
+		(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+
+	/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
+	writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+	       &smicntl->smi_cr1);
+}
+
+static int snor_image_load(u8 *load_addr, void (**image_p)(void),
+			   const char *image_name)
+{
+	image_header_t *header;
+
+	/*
+	 * Since calculating the crc in the SNOR flash does not
+	 * work, we copy the image to the destination address
+	 * minus the header size. And point the header to this
+	 * new destination. This will not work for address 0
+	 * of course.
+	 */
+	header = (image_header_t *)load_addr;
+	memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)),
+	       (const ulong *)load_addr,
+	       image_get_data_size(header) + sizeof(image_header_t));
+	header = (image_header_t *)(image_get_load(header) -
+				    sizeof(image_header_t));
+
+	if (image_check_header(header, image_name)) {
+		if (image_check_data(header)) {
+			/* Jump to boot image */
+			*image_p = (void *)image_get_load(header);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static void boot_image(void (*image)(void))
+{
+	void (*funcp)(void) __noreturn = (void *)image;
+
+	(*funcp)();
+}
+
+/*
+ * spl_boot:
+ *
+ * All supported booting types of all supported SoCs are listed here.
+ * Generic readback APIs are provided for each supported booting type
+ * eg. nand_read_skip_bad
+ */
+u32 spl_boot(void)
+{
+	void (*image)(void);
+
+#ifdef CONFIG_SPEAR_USBTTY
+	plat_late_init();
+	return 1;
+#endif
+
+	/*
+	 * All the supported booting devices are listed here. Each of
+	 * the booting type supported by the platform would define the
+	 * macro xxx_BOOT_SUPPORTED to TRUE.
+	 */
+
+	if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
+		/* SNOR-SMI initialization */
+		snor_init();
+
+		serial_puts("Booting via SNOR\n");
+		/* Serial NOR booting */
+		if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
+					    &image, loader_name)) {
+			/* Platform related late initialasations */
+			plat_late_init();
+
+			/* Jump to boot image */
+			serial_puts("Jumping to U-Boot\n");
+			boot_image(image);
+			return 1;
+		}
+	}
+
+	if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
+		/* NAND booting */
+		/* Not ported from XLoader to SPL yet */
+		return 0;
+	}
+
+	if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
+		/* PNOR booting */
+		/* Not ported from XLoader to SPL yet */
+		return 0;
+	}
+
+	if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) {
+		/* MMC booting */
+		/* Not ported from XLoader to SPL yet */
+		return 0;
+	}
+
+	if (SPI_BOOT_SUPPORTED && spi_boot_selected()) {
+		/* SPI booting */
+		/* Not supported for any platform as of now */
+		return 0;
+	}
+
+	if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) {
+		/* I2C booting */
+		/* Not supported for any platform as of now */
+		return 0;
+	}
+
+	/*
+	 * All booting types without memory are listed as below
+	 * Control has to be returned to BootROM in case of all
+	 * the following booting scenarios
+	 */
+
+	if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
+		plat_late_init();
+		return 1;
+	}
+
+	if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
+		plat_late_init();
+		return 1;
+	}
+
+	if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
+		plat_late_init();
+		return 1;
+	}
+
+	/* Ideally, the control should not reach here. */
+	hang();
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
new file mode 100644
index 0000000000..5edc115d10
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000001,
+	0x00000000,
+	0x01000000,
+	0x00000101,
+	0x00000001,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x00010001,
+	0x00000003,
+	0x01000201,
+	0x06000202,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000404,
+	0x02030202,
+	0x03000204,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x08080a01,
+	0x0000023f,
+	0x00040800,
+	0x00000000,
+	0x00000f02,
+	0x00001b1b,
+	0x7f000000,
+	0x005f0000,
+	0x1c040b6a,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x000007ff,
+	0x00000000,
+	0x47ec00c8,
+	0x00c8001f,
+	0x00000000,
+	0x0000cd98,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00270000,
+	0x00250027,
+	0x00300000,
+	0x008900b7,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
new file mode 100644
index 0000000000..616b86194d
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+	0x00000001,
+	0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+	0x02020201,
+	0x02020202,
+#endif
+	0x01000000,
+	0x00000101,
+	0x00000101,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x01010001,
+	0x00000201,
+	0x01000101,
+	0x06000002,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000405,
+	0x03040202,
+	0x04000305,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x0a0a0a01,
+	0x0000023f,
+	0x00050a00,
+	0x11000000,
+	0x00001302,
+	0x00000A0A,
+	0x72000000,
+	0x00550000,
+	0x2b050e86,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00000a24,
+	0x43C20000,
+	0x5b1c00c8,
+	0x00c8002e,
+	0x00000000,
+	0x0001046b,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00210000,
+	0x00010021,
+	0x00200000,
+	0x006c0090,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
new file mode 100644
index 0000000000..b89f77deb0
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x03030301,
+	0x03030303,
+	0x01000000,
+	0x00000101,
+	0x00000001,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x00010001,
+	0x00000003,
+	0x01000201,
+	0x06000202,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000404,
+	0x02020202,
+	0x03000203,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x08080a01,
+	0x0000023f,
+	0x00030600,
+	0x00000000,
+	0x00000a02,
+	0x00001c1c,
+	0x7f000000,
+	0x005f0000,
+	0x12030743,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x0000050e,
+	0x00000000,
+	0x2d8900c8,
+	0x00c80014,
+	0x00000000,
+	0x00008236,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00400000,
+	0x003a0040,
+	0x00680000,
+	0x00d80120,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
new file mode 100644
index 0000000000..0c39cd1059
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+	0x00000001,
+	0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+	0x02020201,
+	0x02020202,
+#endif
+	0x01000000,
+	0x00000101,
+	0x00000101,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x01010001,
+	0x00000201,
+	0x01000101,
+	0x06000002,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+#ifdef CONFIG_X600
+	0x02030206,
+#else
+	0x02010106,
+#endif
+	0x03000405,
+	0x03040202,
+	0x04000305,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x0a0a0a01,
+	0x0000023f,
+	0x00050a00,
+	0x11000000,
+	0x00001302,
+	0x00000A0A,
+#ifdef CONFIG_X600
+	0x7f000000,
+	0x005c0000,
+#else
+	0x72000000,
+	0x00550000,
+#endif
+	0x2b050e86,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00000a24,
+	0x43C20000,
+	0x5b1c00c8,
+	0x00c8002e,
+	0x00000000,
+	0x0001046b,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00210000,
+	0x00010021,
+	0x00200000,
+	0x006c0090,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S
new file mode 100644
index 0000000000..a103c0f4ab
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/start.S
@@ -0,0 +1,122 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+
+.globl _start
+_start:
+	b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+_software_interrupt:
+_prefetch_abort:
+_data_abort:
+_not_used:
+_irq:
+_fiq:
+	.word infinite_loop
+
+infinite_loop:
+	b	infinite_loop
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * Below are the critical initializations already taken place in BootROM.
+ * So, these are not taken care in Xloader
+ * 1. Relocation to RAM
+ * 2. Initializing stacks
+ *
+ *************************************************************************
+ */
+
+/*
+ * the actual reset code
+ */
+
+reset:
+/*
+ * Xloader has to return back to BootROM in a few cases.
+ * eg. Ethernet boot, UART boot, USB boot
+ * Saving registers for returning back
+ */
+	stmdb	sp!, {r0-r12,r14}
+	bl	cpu_init_crit
+/*
+ * Clearing bss area is not done in Xloader.
+ * BSS area lies in the DDR location which is not yet initialized
+ * bss is assumed to be uninitialized.
+ */
+	bl	spl_boot
+	ldmia	sp!, {r0-r12,pc}
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * enable instruction cache
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	stmdb	sp!, {lr}
+	bl	lowlevel_init	/* go setup pll,mux,memory */
+	ldmia	sp!, {pc}
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
new file mode 100644
index 0000000000..afd3381e16
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/arm926ejs/spear/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+	_end = .;
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynsym*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.hash*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 6b7a494d7c..71309a7f47 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -40,6 +40,22 @@ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 #define UART_SMART_IDLE_EN	(0x1 << 0x3)
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+/* Initialize timer */
+static void init_timer(void)
+{
+	/* Reset the Timer */
+	writel(0x2, (&timer_base->tscir));
+
+	/* Wait until the reset is done */
+	while (readl(&timer_base->tiocp_cfg) & 1)
+		;
+
+	/* Start the Timer */
+	writel(0x1, (&timer_base->tclr));
+}
+#endif
+
 /*
  * early system init of muxing and clocks.
  */
@@ -88,20 +104,6 @@ void s_init(void)
 	enable_mmc0_pin_mux();
 }
 
-/* Initialize timer */
-void init_timer(void)
-{
-	/* Reset the Timer */
-	writel(0x2, (&timer_base->tscir));
-
-	/* Wait until the reset is done */
-	while (readl(&timer_base->tiocp_cfg) & 1)
-		;
-
-	/* Start the Timer */
-	writel(0x1, (&timer_base->tclr));
-}
-
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index c6fa8ef136..9eb484af18 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -36,9 +36,15 @@
 #include <asm/system.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
+#include <linux/compiler.h>
 
-void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
+void __naked save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
 {
+	/*
+	 * Stack pointer is not yet initialized
+	 * Don't save anything to stack even if compiled with -O0
+	 */
+	asm("bx lr");
 }
 
 void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
index 90ec2bd404..9119961d95 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= clock.o power.o soc.o system.o
+COBJS	+= clock.o power.o soc.o system.o pinmux.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
new file mode 100644
index 0000000000..d2b7d2cba7
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics.
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sromc.h>
+
+static void exynos5_uart_config(int peripheral)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	struct s5p_gpio_bank *bank;
+	int i, start, count;
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+		bank = &gpio1->a0;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART1:
+		bank = &gpio1->a0;
+		start = 4;
+		count = 4;
+		break;
+	case PERIPH_ID_UART2:
+		bank = &gpio1->a1;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART3:
+		bank = &gpio1->a1;
+		start = 4;
+		count = 2;
+		break;
+	}
+	for (i = start; i < start + count; i++) {
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+	}
+}
+
+static int exynos5_mmc_config(int peripheral, int flags)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	struct s5p_gpio_bank *bank, *bank_ext;
+	int i;
+
+	switch (peripheral) {
+	case PERIPH_ID_SDMMC0:
+		bank = &gpio1->c0;
+		bank_ext = &gpio1->c1;
+		break;
+	case PERIPH_ID_SDMMC1:
+		bank = &gpio1->c1;
+		bank_ext = NULL;
+		break;
+	case PERIPH_ID_SDMMC2:
+		bank = &gpio1->c2;
+		bank_ext = &gpio1->c3;
+		break;
+	case PERIPH_ID_SDMMC3:
+		bank = &gpio1->c3;
+		bank_ext = NULL;
+		break;
+	}
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+		debug("SDMMC device %d does not support 8bit mode",
+				peripheral);
+		return -1;
+	}
+	if (flags & PINMUX_FLAG_8BIT_MODE) {
+		for (i = 3; i <= 6; i++) {
+			s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		}
+	}
+	for (i = 0; i < 2; i++) {
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+	for (i = 3; i <= 6; i++) {
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+	return 0;
+}
+
+static void exynos5_sromc_config(int flags)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	int i;
+
+	/*
+	 * SROM:CS1 and EBI
+	 *
+	 * GPY0[0]	SROM_CSn[0]
+	 * GPY0[1]	SROM_CSn[1](2)
+	 * GPY0[2]	SROM_CSn[2]
+	 * GPY0[3]	SROM_CSn[3]
+	 * GPY0[4]	EBI_OEn(2)
+	 * GPY0[5]	EBI_EEn(2)
+	 *
+	 * GPY1[0]	EBI_BEn[0](2)
+	 * GPY1[1]	EBI_BEn[1](2)
+	 * GPY1[2]	SROM_WAIT(2)
+	 * GPY1[3]	EBI_DATA_RDn(2)
+	 */
+	s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
+				GPIO_FUNC(2));
+	s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
+	s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+
+	for (i = 0; i < 4; i++)
+		s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+
+	/*
+	 * EBI: 8 Addrss Lines
+	 *
+	 * GPY3[0]	EBI_ADDR[0](2)
+	 * GPY3[1]	EBI_ADDR[1](2)
+	 * GPY3[2]	EBI_ADDR[2](2)
+	 * GPY3[3]	EBI_ADDR[3](2)
+	 * GPY3[4]	EBI_ADDR[4](2)
+	 * GPY3[5]	EBI_ADDR[5](2)
+	 * GPY3[6]	EBI_ADDR[6](2)
+	 * GPY3[7]	EBI_ADDR[7](2)
+	 *
+	 * EBI: 16 Data Lines
+	 *
+	 * GPY5[0]	EBI_DATA[0](2)
+	 * GPY5[1]	EBI_DATA[1](2)
+	 * GPY5[2]	EBI_DATA[2](2)
+	 * GPY5[3]	EBI_DATA[3](2)
+	 * GPY5[4]	EBI_DATA[4](2)
+	 * GPY5[5]	EBI_DATA[5](2)
+	 * GPY5[6]	EBI_DATA[6](2)
+	 * GPY5[7]	EBI_DATA[7](2)
+	 *
+	 * GPY6[0]	EBI_DATA[8](2)
+	 * GPY6[1]	EBI_DATA[9](2)
+	 * GPY6[2]	EBI_DATA[10](2)
+	 * GPY6[3]	EBI_DATA[11](2)
+	 * GPY6[4]	EBI_DATA[12](2)
+	 * GPY6[5]	EBI_DATA[13](2)
+	 * GPY6[6]	EBI_DATA[14](2)
+	 * GPY6[7]	EBI_DATA[15](2)
+	 */
+	for (i = 0; i < 8; i++) {
+		s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
+		s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+
+		s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
+		s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+
+		s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
+		s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+	}
+}
+
+static int exynos5_pinmux_config(int peripheral, int flags)
+{
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+		exynos5_uart_config(peripheral);
+		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC3:
+		return exynos5_mmc_config(peripheral, flags);
+	case PERIPH_ID_SROMC:
+		exynos5_sromc_config(flags);
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	}
+
+	return 0;
+}
+
+int exynos_pinmux_config(int peripheral, int flags)
+{
+	if (cpu_is_exynos5())
+		return exynos5_pinmux_config(peripheral, flags);
+	else {
+		debug("pinmux functionality not supported\n");
+		return -1;
+	}
+}
diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/cpu/armv7/imx-common/speed.c
index 2187e8ee5d..80989c4983 100644
--- a/arch/arm/cpu/armv7/imx-common/speed.c
+++ b/arch/arm/cpu/armv7/imx-common/speed.c
@@ -35,7 +35,11 @@ DECLARE_GLOBAL_DATA_PTR;
 int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_USDHC
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#else
 	gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
 #endif
+#endif
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index fc2406bcad..64862b31f1 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -843,7 +843,7 @@ void mxc_set_sata_internal_clock(void)
 
 	set_usb_phy1_clk();
 
-	writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
+	writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
 }
 #endif
 
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 90f208809b..84b458c7eb 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -43,7 +43,6 @@ u32 get_cpu_rev(void)
 	return system_rev;
 }
 
-#ifdef CONFIG_ARCH_CPU_INIT
 void init_aips(void)
 {
 	struct aipstz_regs *aips1, *aips2;
@@ -113,7 +112,6 @@ int arch_cpu_init(void)
 
 	return 0;
 }
-#endif
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 10d286a6d4..b1fd277d6d 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -299,8 +299,12 @@ static void setup_dplls(void)
 	 * Core DPLL will be locked after setting up EMIF
 	 * using the FREQ_UPDATE method(freq_update_core())
 	 */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
-								"core");
+	if (omap_revision() != OMAP5432_ES1_0)
+		do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+							DPLL_NO_LOCK, "core");
+	else
+		do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+							DPLL_LOCK, "core");
 	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
 	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
 	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index db509c9295..30dcf1b0b0 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -31,6 +31,28 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
 #include <asm/utils.h>
+#include <linux/compiler.h>
+
+void set_lpmode_selfrefresh(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 reg;
+
+	reg = readl(&emif->emif_pwr_mgmt_ctrl);
+	reg &= ~EMIF_REG_LP_MODE_MASK;
+	reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
+	reg &= ~EMIF_REG_SR_TIM_MASK;
+	writel(reg, &emif->emif_pwr_mgmt_ctrl);
+
+	/* dummy read for the new SR_TIM to be loaded */
+	readl(&emif->emif_pwr_mgmt_ctrl);
+}
+
+void force_emif_self_refresh()
+{
+	set_lpmode_selfrefresh(EMIF1_BASE);
+	set_lpmode_selfrefresh(EMIF2_BASE);
+}
 
 inline u32 emif_num(u32 base)
 {
@@ -56,7 +78,12 @@ static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
 		mr = readl(&emif->emif_lpddr2_mode_reg_data);
 	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
 	      cs, mr_addr, mr);
-	return mr;
+	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
+	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
+		return mr & 0xff;
+	else
+		return mr;
 }
 
 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
@@ -114,9 +141,6 @@ static void do_lpddr2_init(u32 base, u32 cs)
 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-	u32 *ext_phy_ctrl_base = 0;
-	u32 *emif_ext_phy_ctrl_base = 0;
-	u32 i = 0;
 
 	/* Not NVM */
 	clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
@@ -134,29 +158,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
 	writel(regs->sdram_config_init, &emif->emif_sdram_config);
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 
-	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
-	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
-	if (omap_revision() >= OMAP5430_ES1_0) {
-		/* Configure external phy control timing registers */
-		for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
-			writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
-			/* Update shadow registers */
-			writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
-		}
-
-		/*
-		 * external phy 6-24 registers do not change with
-		 * ddr frequency
-		 */
-		for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
-			writel(ext_phy_ctrl_const_base[i],
-						emif_ext_phy_ctrl_base++);
-			/* Update shadow registers */
-			writel(ext_phy_ctrl_const_base[i],
-						emif_ext_phy_ctrl_base++);
-		}
-	}
+	do_ext_phy_settings(base, regs);
 
 	do_lpddr2_init(base, CS0);
 	if (regs->sdram_config & EMIF_REG_EBANK_MASK)
@@ -168,6 +170,10 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
 	/* Enable refresh now */
 	clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 
+	}
+
+__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
 }
 
 void emif_update_timings(u32 base, const struct emif_regs *regs)
@@ -190,7 +196,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
 	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 
-	if (omap_revision() == OMAP5430_ES1_0) {
+	if (omap_revision() >= OMAP5430_ES1_0) {
 		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 			&emif->emif_l3_config);
 	} else if (omap_revision() >= OMAP4460_ES1_0) {
@@ -202,6 +208,101 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
 	}
 }
 
+static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* keep sdram in self-refresh */
+	writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
+		& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+	__udelay(130);
+
+	/*
+	 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
+	 * Invert clock adds an additional half cycle delay on the command
+	 * interface.  The additional half cycle, is usually meant to enable
+	 * leveling in the situation that DQS is later than CK on the board.It
+	 * also helps provide some additional margin for leveling.
+	 */
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	__udelay(130);
+
+	writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
+		& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+
+	/* Launch Full leveling */
+	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+	/* Wait till full leveling is complete */
+	readl(&emif->emif_rd_wr_lvl_ctl);
+	__udelay(130);
+
+	/* Read data eye leveling no of samples */
+	config_data_eye_leveling_samples(base);
+
+	/* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
+	writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
+	__udelay(130);
+
+	/* Launch Incremental leveling */
+	writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
+	__udelay(130);
+}
+
+static void ddr3_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	u32 i = 0;
+
+	/*
+	 * Set SDRAM_CONFIG and PHY control registers to locked frequency
+	 * and RL =7. As the default values of the Mode Registers are not
+	 * defined, contents of mode Registers must be fully initialized.
+	 * H/W takes care of this initialization
+	 */
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+	/* Update timing registers */
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+
+	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+	/*
+	 * external phy 6-24 registers do not change with
+	 * ddr frequency
+	 */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+		writel(ddr3_ext_phy_ctrl_const_base[i],
+					emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ddr3_ext_phy_ctrl_const_base[i],
+					emif_ext_phy_ctrl_base++);
+	}
+
+	/* enable leveling */
+	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+
+	ddr3_leveling(base, regs);
+}
+
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 
@@ -826,7 +927,7 @@ static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
 	}
 
 	mr = get_mr(base, cs, LPDDR2_MR5);
-	if (mr >= 0xFF) {
+	if (mr > 0xFF) {
 		/* Mode register value bigger than 8 bit */
 		return 0;
 	}
@@ -895,7 +996,7 @@ struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 		return NULL;
 
 	/* Do the minimum init for mode register accesses */
-	if (!running_from_sdram()) {
+	if (!(running_from_sdram() || warm_reset())) {
 		phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
 		writel(phy, &emif->emif_ddr_phy_ctrl_1);
 	}
@@ -975,8 +1076,12 @@ static void do_sdram_init(u32 base)
 	 * Changing the timing registers in EMIF can happen(going from one
 	 * OPP to another)
 	 */
-	if (!in_sdram)
-		lpddr2_init(base, regs);
+	if (!(in_sdram || warm_reset())) {
+		if (omap_revision() != OMAP5432_ES1_0)
+			lpddr2_init(base, regs);
+		else
+			ddr3_init(base, regs);
+	}
 
 	/* Write to the shadow registers */
 	emif_update_timings(base, regs);
@@ -1133,6 +1238,7 @@ void dmm_init(u32 base)
 void sdram_init(void)
 {
 	u32 in_sdram, size_prog, size_detect;
+	u32 omap_rev = omap_revision();
 
 	debug(">>sdram_init()\n");
 
@@ -1142,25 +1248,34 @@ void sdram_init(void)
 	in_sdram = running_from_sdram();
 	debug("in_sdram = %d\n", in_sdram);
 
-	if (!in_sdram)
-		bypass_dpll(&prcm->cm_clkmode_dpll_core);
-
+	if (!(in_sdram || warm_reset())) {
+		if (omap_rev != OMAP5432_ES1_0)
+			bypass_dpll(&prcm->cm_clkmode_dpll_core);
+		else
+			writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
+	}
 
 	do_sdram_init(EMIF1_BASE);
 	do_sdram_init(EMIF2_BASE);
 
-	if (!in_sdram) {
+	if (!in_sdram)
 		dmm_init(DMM_BASE);
+
+	if (!(in_sdram || warm_reset())) {
 		emif_post_init_config(EMIF1_BASE);
 		emif_post_init_config(EMIF2_BASE);
 	}
 
 	/* for the shadow registers to take effect */
-	freq_update_core();
+	if (omap_rev != OMAP5432_ES1_0)
+		freq_update_core();
 
 	/* Do some testing after the init */
 	if (!in_sdram) {
 		size_prog = omap_sdram_size();
+		size_prog = log_2_n_round_down(size_prog);
+		size_prog = (1 << size_prog);
+
 		size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 						size_prog);
 		/* Compare with the size programmed */
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index cf71ab4443..459ebb55e5 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -111,6 +111,10 @@ static void init_boot_params(void)
 void s_init(void)
 {
 	init_omap_revision();
+#ifdef CONFIG_SPL_BUILD
+	if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+		force_emif_self_refresh();
+#endif
 	watchdog_init();
 	set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD
@@ -162,11 +166,16 @@ void watchdog_init(void)
  */
 u32 omap_sdram_size(void)
 {
-	u32 section, i, total_size = 0, size, addr;
+	u32 section, i, valid;
+	u64 sdram_start = 0, sdram_end = 0, addr,
+	    size, total_size = 0, trap_size = 0;
 
 	for (i = 0; i < 4; i++) {
 		section	= __raw_readl(DMM_BASE + i*4);
+		valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
+			(EMIF_SDRC_ADDRSPC_SHIFT);
 		addr = section & EMIF_SYS_ADDR_MASK;
+
 		/* See if the address is valid */
 		if ((addr >= DRAM_ADDR_SPACE_START) &&
 		    (addr < DRAM_ADDR_SPACE_END)) {
@@ -174,9 +183,20 @@ u32 omap_sdram_size(void)
 				   EMIF_SYS_SIZE_SHIFT);
 			size = 1 << size;
 			size *= SZ_16M;
-			total_size += size;
+
+			if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
+				if (!sdram_start || (addr < sdram_start))
+					sdram_start = addr;
+				if (!sdram_end || ((addr + size) > sdram_end))
+					sdram_end = addr + size;
+			} else {
+				trap_size = size;
+			}
+
 		}
+
 	}
+	total_size = (sdram_end - sdram_start) - (trap_size);
 
 	return total_size;
 }
diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c
index 234e90a868..587bb47745 100644
--- a/arch/arm/cpu/armv7/omap-common/reset.c
+++ b/arch/arm/cpu/armv7/omap-common/reset.c
@@ -34,3 +34,8 @@ void __weak reset_cpu(unsigned long ignored)
 {
 	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
 }
+
+u32 __weak warm_reset(void)
+{
+	return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
+}
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index c568951a91..5bd0a88fde 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -146,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
 	{727, 14, -1, -1, 4, 7, -1, -1},	/* 19.2 MHz */
 	{931, 25, -1, -1, 4, 7, -1, -1},	/* 26 MHz   */
 	{931, 26, -1, -1, 4, 7, -1, -1},	/* 27 MHz   */
-	{412, 16, -1, -1, 4, 7, -1, -1}		/* 38.4 MHz */
+	{291, 11, -1, -1, 4, 7, -1, -1}		/* 38.4 MHz */
 };
 
 /* ABE M & N values with sys_clk as source */
@@ -354,6 +354,7 @@ void enable_basic_clocks(void)
 	};
 
 	u32 *const clk_modules_hw_auto_essential[] = {
+		&prcm->cm_l3_2_gpmc_clkctrl,
 		&prcm->cm_memif_emif_1_clkctrl,
 		&prcm->cm_memif_emif_2_clkctrl,
 		&prcm->cm_l4cfg_l4_cfg_clkctrl,
@@ -363,9 +364,6 @@ void enable_basic_clocks(void)
 		&prcm->cm_l4per_gpio4_clkctrl,
 		&prcm->cm_l4per_gpio5_clkctrl,
 		&prcm->cm_l4per_gpio6_clkctrl,
-		&prcm->cm_l3init_usbphy_clkctrl,
-		&prcm->cm_clksel_usb_60mhz,
-		&prcm->cm_l3init_hsusbtll_clkctrl,
 		0
 	};
 
@@ -376,7 +374,6 @@ void enable_basic_clocks(void)
 		&prcm->cm_l4per_gptimer2_clkctrl,
 		&prcm->cm_wkup_wdtimer2_clkctrl,
 		&prcm->cm_l4per_uart3_clkctrl,
-		&prcm->cm_l3init_hsusbhost_clkctrl,
 		0
 	};
 
@@ -413,6 +410,9 @@ void enable_basic_uboot_clocks(void)
 	u32 *const clk_modules_hw_auto_essential[] = {
 		&prcm->cm_l3init_hsusbotg_clkctrl,
 		&prcm->cm_l3init_usbphy_clkctrl,
+		&prcm->cm_l3init_usbphy_clkctrl,
+		&prcm->cm_clksel_usb_60mhz,
+		&prcm->cm_l3init_hsusbtll_clkctrl,
 		0
 	};
 
@@ -422,6 +422,7 @@ void enable_basic_uboot_clocks(void)
 		&prcm->cm_l4per_i2c2_clkctrl,
 		&prcm->cm_l4per_i2c3_clkctrl,
 		&prcm->cm_l4per_i2c4_clkctrl,
+		&prcm->cm_l3init_hsusbhost_clkctrl,
 		0
 	};
 
@@ -452,12 +453,10 @@ void enable_non_essential_clocks(void)
 	};
 
 	u32 *const clk_modules_hw_auto_non_essential[] = {
-		&prcm->cm_l3_2_gpmc_clkctrl,
 		&prcm->cm_l3instr_l3_3_clkctrl,
 		&prcm->cm_l3instr_l3_instr_clkctrl,
 		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
 		&prcm->cm_l3init_hsi_clkctrl,
-		&prcm->cm_l3init_hsusbtll_clkctrl,
 		0
 	};
 
@@ -497,7 +496,6 @@ void enable_non_essential_clocks(void)
 		&prcm->cm_cam_fdif_clkctrl,
 		&prcm->cm_dss_dss_clkctrl,
 		&prcm->cm_sgx_sgx_clkctrl,
-		&prcm->cm_l3init_hsusbhost_clkctrl,
 		0
 	};
 
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index 187e93887b..2c34e48f42 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -118,6 +118,11 @@ void do_io_settings(void)
 }
 #endif
 
+/* dummy fuction for omap4 */
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+}
+
 void init_omap_revision(void)
 {
 	/*
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index b5389606b6..b9128faa56 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -91,7 +91,7 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
 };
 
 /* Dummy registers for OMAP44xx */
-const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
+const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
 
 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 	.dmm_lisa_map_0 = 0xFF020100,
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
index 1a59f265f7..eecfbade35 100644
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -260,20 +260,31 @@ const struct dpll_params *get_abe_dpll_params(void)
  */
 void scale_vcores(void)
 {
-	u32 volt;
+	u32 volt_core, volt_mpu, volt_mm;
 
 	omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
 
 	/* Palmas settings */
-	volt = VDD_CORE;
-	do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
-
-	volt = VDD_MPU;
-	do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
-
-	volt = VDD_MM;
-	do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
-
+	if (omap_revision() != OMAP5432_ES1_0) {
+		volt_core = VDD_CORE;
+		volt_mpu = VDD_MPU;
+		volt_mm = VDD_MM;
+	} else {
+		volt_core = VDD_CORE_5432;
+		volt_mpu = VDD_MPU_5432;
+		volt_mm = VDD_MM_5432;
+	}
+
+	do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
+	do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
+	do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
+
+	if (omap_revision() == OMAP5432_ES1_0) {
+		/* Configure LDO SRAM "magic" bits */
+		writel(2, &prcm->prm_sldo_core_setup);
+		writel(2, &prcm->prm_sldo_mpu_setup);
+		writel(2, &prcm->prm_sldo_mm_setup);
+	}
 }
 
 u32 get_offset_code(u32 volt_offset)
@@ -306,6 +317,7 @@ void enable_basic_clocks(void)
 	};
 
 	u32 *const clk_modules_hw_auto_essential[] = {
+		&prcm->cm_l3_2_gpmc_clkctrl,
 		&prcm->cm_memif_emif_1_clkctrl,
 		&prcm->cm_memif_emif_2_clkctrl,
 		&prcm->cm_l4cfg_l4_cfg_clkctrl,
@@ -382,6 +394,9 @@ void enable_basic_uboot_clocks(void)
 		&prcm->cm_l4per_i2c2_clkctrl,
 		&prcm->cm_l4per_i2c3_clkctrl,
 		&prcm->cm_l4per_i2c4_clkctrl,
+		&prcm->cm_l3init_hsusbtll_clkctrl,
+		&prcm->cm_l3init_hsusbhost_clkctrl,
+		&prcm->cm_l3init_fsusb_clkctrl,
 		0
 	};
 
@@ -416,12 +431,10 @@ void enable_non_essential_clocks(void)
 		&prcm->cm_ivahd_ivahd_clkctrl,
 		&prcm->cm_ivahd_sl2_clkctrl,
 		&prcm->cm_dsp_dsp_clkctrl,
-		&prcm->cm_l3_2_gpmc_clkctrl,
 		&prcm->cm_l3instr_l3_3_clkctrl,
 		&prcm->cm_l3instr_l3_instr_clkctrl,
 		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
 		&prcm->cm_l3init_hsi_clkctrl,
-		&prcm->cm_l3init_hsusbtll_clkctrl,
 		&prcm->cm_l4per_hdq1w_clkctrl,
 		0
 	};
@@ -460,8 +473,6 @@ void enable_non_essential_clocks(void)
 		&prcm->cm_cam_fdif_clkctrl,
 		&prcm->cm_dss_dss_clkctrl,
 		&prcm->cm_sgx_sgx_clkctrl,
-		&prcm->cm_l3init_hsusbhost_clkctrl,
-		&prcm->cm_l3init_fsusb_clkctrl,
 		0
 	};
 
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index d01cc81333..d0c3ff7021 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -35,6 +35,7 @@
 #include <asm/sizes.h>
 #include <asm/utils.h>
 #include <asm/arch/gpio.h>
+#include <asm/emif.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,6 +53,81 @@ static struct gpio_bank gpio_bank_54xx[6] = {
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
 
 #ifdef CONFIG_SPL_BUILD
+/* LPDDR2 specific IO settings */
+static void io_settings_lpddr2(void)
+{
+	struct omap_sys_ctrl_regs *ioregs_base =
+		      (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+				&(ioregs_base->control_ddrch1_0));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+				&(ioregs_base->control_ddrch1_1));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+				&(ioregs_base->control_ddrch2_0));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+				&(ioregs_base->control_ddrch2_1));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+				&(ioregs_base->control_lpddr2ch1_0));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+				&(ioregs_base->control_lpddr2ch1_1));
+	writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+				&(ioregs_base->control_ddrio_0));
+	writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+				&(ioregs_base->control_ddrio_1));
+	writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+				&(ioregs_base->control_ddrio_2));
+}
+
+/* DDR3 specific IO settings */
+static void io_settings_ddr3(void)
+{
+	u32 io_settings = 0;
+	struct omap_sys_ctrl_regs *ioregs_base =
+		      (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+	writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+				&(ioregs_base->control_ddr3ch1_0));
+	writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+				&(ioregs_base->control_ddrch1_0));
+	writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+				&(ioregs_base->control_ddrch1_1));
+
+	writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+				&(ioregs_base->control_ddr3ch2_0));
+	writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+				&(ioregs_base->control_ddrch2_0));
+	writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+				&(ioregs_base->control_ddrch2_1));
+
+	writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+				&(ioregs_base->control_ddrio_0));
+	writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+				&(ioregs_base->control_ddrio_1));
+	writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+				&(ioregs_base->control_ddrio_2));
+
+	/* omap5432 does not use lpddr2 */
+	writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
+	writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
+
+	writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+			&(ioregs_base->control_emif1_sdram_config_ext));
+	writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+			&(ioregs_base->control_emif2_sdram_config_ext));
+
+	/* Disable DLL select */
+	io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
+							& 0xFFEFFFFF);
+	writel(io_settings,
+		&(ioregs_base->control_port_emif1_sdram_config));
+
+	io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
+							& 0xFFEFFFFF);
+	writel(io_settings,
+		&(ioregs_base->control_port_emif2_sdram_config));
+}
+
 /*
  * Some tuning of IOs for optimal power and performance
  */
@@ -115,25 +191,10 @@ void do_io_settings(void)
 		       (sc_fast << 17) | (sc_fast << 14);
 	writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
 
-	/* LPDDR2 io settings */
-	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-					&(ioregs_base->control_ddrch1_0));
-	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-					&(ioregs_base->control_ddrch1_1));
-	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-					&(ioregs_base->control_ddrch2_0));
-	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-					&(ioregs_base->control_ddrch2_1));
-	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
-					&(ioregs_base->control_lpddr2ch1_0));
-	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
-					&(ioregs_base->control_lpddr2ch1_1));
-	writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
-					&(ioregs_base->control_ddrio_0));
-	writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
-					&(ioregs_base->control_ddrio_1));
-	writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
-					&(ioregs_base->control_ddrio_2));
+	if (omap_revision() <= OMAP5430_ES1_0)
+		io_settings_lpddr2();
+	else
+		io_settings_ddr3();
 
 	/* Efuse settings */
 	writel(EFUSE_1, &(ioregs_base->control_efuse_1));
@@ -143,6 +204,20 @@ void do_io_settings(void)
 }
 #endif
 
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+	struct omap_sys_ctrl_regs *ioregs_base =
+		(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+	/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
+	if (emif_base == EMIF1_BASE)
+		writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+			&(ioregs_base->control_emif1_sdram_config_ext));
+	else if (emif_base == EMIF2_BASE)
+		writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+			&(ioregs_base->control_emif2_sdram_config_ext));
+}
+
 void init_omap_revision(void)
 {
 	/*
@@ -154,7 +229,15 @@ void init_omap_revision(void)
 
 	switch (rev) {
 	case MIDR_CORTEX_A15_R0P0:
-		*omap_si_rev = OMAP5430_ES1_0;
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP5430_CONTROL_ID_CODE_ES1_0:
+			*omap_si_rev = OMAP5430_ES1_0;
+			break;
+		case OMAP5432_CONTROL_ID_CODE_ES1_0:
+		default:
+			*omap_si_rev = OMAP5432_ES1_0;
+			break;
+		}
 		break;
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index b2b5753e89..6ebdf5fbfd 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -86,11 +86,34 @@ const struct emif_regs emif_regs_266_mhz_2cs = {
 	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
 };
 
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
+	.sdram_config_init		= 0x61851B32,
+	.sdram_config			= 0x61851B32,
+	.ref_ctrl			= 0x00001035,
+	.sdram_tim1			= 0xCCCF36B3,
+	.sdram_tim2			= 0x308F7FDA,
+	.sdram_tim3			= 0x027F88A8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x0007190B,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0020420A,
+	.emif_ddr_phy_ctlr_1		= 0x0024420A,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000000,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000000,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00000000,
+	.emif_ddr_ext_phy_ctrl_5	= 0x04010040,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305
+};
+
 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 	.dmm_lisa_map_0 = 0x0,
-	.dmm_lisa_map_1 = 0,
-	.dmm_lisa_map_2 = 0,
-	.dmm_lisa_map_3 = 0x80740300
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80740300,
+	.dmm_lisa_map_3 = 0xFF020100
 };
 
 const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@@ -115,9 +138,34 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 	0x00000077
 };
 
+const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+	0x01004010,
+	0x00001004,
+	0x04010040,
+	0x01004010,
+	0x00001004,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x80080080,
+	0x00800800,
+	0x08102040,
+	0x00000002,
+	0x0,
+	0x0,
+	0x0,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000057
+};
+
 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 {
-	*regs = &emif_regs_532_mhz_2cs;
+	if (omap_revision() == OMAP5432_ES1_0)
+		*regs = &emif_regs_ddr3_532_mhz_1cs;
+	else
+		*regs = &emif_regs_532_mhz_2cs;
 }
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
@@ -156,6 +204,37 @@ void emif_get_device_details(u32 emif_nr,
 
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	u32 i = 0;
+
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+	/*
+	 * external phy 6-24 registers do not change with
+	 * ddr frequency
+	 */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+		writel(ext_phy_ctrl_const_base[i],
+					emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_base[i],
+					emif_ext_phy_ctrl_base++);
+	}
+}
+
 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 	.max_freq	= 532000000,
diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c
index 527f32deef..16427333ac 100644
--- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c
+++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c
@@ -48,8 +48,9 @@ int print_cpuinfo(void)
 {
 	char buf[32];
 
-	printf("CPU:\tS5P%X@%sMHz\n",
-			s5p_cpu_id, strmhz(buf, get_arm_clk()));
+	printf("CPU:\t%s%X@%sMHz\n",
+			s5p_get_cpu_name(), s5p_cpu_id,
+			strmhz(buf, get_arm_clk()));
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 261835b6c6..22a3cedcb0 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -277,6 +277,18 @@ jump_2_ram:
 	mcr     p15, 0, r0, c7, c10, 4	@ DSB
 	mcr     p15, 0, r0, c7, c5, 4	@ ISB
 #endif
+/*
+ * Move vector table
+ */
+#if !defined(CONFIG_TEGRA2)
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
+	/* Set vector address in CP15 VBAR register */
+	ldr     r0, =_start
+	add     r0, r0, r9
+	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
+#endif
+#endif /* !Tegra2 */
+
 	ldr	r0, _board_init_r_ofs
 	adr	r1, _start
 	add	lr, r0, r1
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index 698bfd0e17..1aad3879ee 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -77,8 +77,10 @@ static int ap20_cpu_is_cortexa9(void)
 
 void init_pllx(void)
 {
-	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct clk_pll_simple *pll =
+		&clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
 	u32 reg;
 
 	/* If PLLX is already enabled, just return */
@@ -312,9 +314,28 @@ void enable_scu(void)
 	writel(reg, &scu->scu_ctrl);
 }
 
+static u32 get_odmdata(void)
+{
+	/*
+	 * ODMDATA is stored in the BCT in IRAM by the BootROM.
+	 * The BCT start and size are stored in the BIT in IRAM.
+	 * Read the data @ bct_start + (bct_size - 12). This works
+	 * on T20 and T30 BCTs, which are locked down. If this changes
+	 * in new chips (T114, etc.), we can revisit this algorithm.
+	 */
+
+	u32 bct_start, odmdata;
+
+	bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+	odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
+
+	return odmdata;
+}
+
 void init_pmc_scratch(void)
 {
 	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+	u32 odmdata;
 	int i;
 
 	/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
@@ -322,7 +343,8 @@ void init_pmc_scratch(void)
 		writel(0, &pmc->pmc_scratch1+i);
 
 	/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
-	writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
+	odmdata = get_odmdata();
+	writel(odmdata, &pmc->pmc_scratch20);
 
 #ifdef CONFIG_TEGRA2_LP0
 	/* save Sdram params to PMC 2, 4, and 24 for WB0 */
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
index a50b1b988a..923678d063 100644
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -101,6 +101,22 @@ int arch_cpu_init(void)
 }
 #endif
 
+static int uart_configs[] = {
+#if defined(CONFIG_TEGRA2_UARTA_UAA_UAB)
+	FUNCMUX_UART1_UAA_UAB,
+#elif defined(CONFIG_TEGRA2_UARTA_GPU)
+	FUNCMUX_UART1_GPU,
+#elif defined(CONFIG_TEGRA2_UARTA_SDIO1)
+	FUNCMUX_UART1_SDIO1,
+#else
+	FUNCMUX_UART1_IRRX_IRTX,
+#endif
+	FUNCMUX_UART2_IRDA,
+	-1,
+	FUNCMUX_UART4_GMC,
+	-1,
+};
+
 /**
  * Set up the specified uarts
  *
@@ -120,7 +136,7 @@ static void setup_uarts(int uart_ids)
 		if (uart_ids & (1 << i)) {
 			enum periph_id id = id_for_uart[i];
 
-			funcmux_select(id, FUNCMUX_DEFAULT);
+			funcmux_select(id, uart_configs[i]);
 			clock_ll_start_uart(id);
 		}
 	}
diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c
index ccad351639..602589cde0 100644
--- a/arch/arm/cpu/armv7/tegra2/clock.c
+++ b/arch/arm/cpu/armv7/tegra2/clock.c
@@ -426,7 +426,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
 	struct clk_rst_ctlr *clkrst =
 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 
-	assert(clock_id_isvalid(clkid));
+	assert(clock_id_is_pll(clkid));
 	return &clkrst->crc_pll[clkid];
 }
 
@@ -439,7 +439,7 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
 	assert(clkid != CLOCK_ID_USB);
 
 	/* Safety check, adds to code size but is small */
-	if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB)
+	if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
 		return -1;
 	data = readl(&pll->pll_base);
 	*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk
index fe9ef5b763..4dd8cb8442 100644
--- a/arch/arm/cpu/armv7/tegra2/config.mk
+++ b/arch/arm/cpu/armv7/tegra2/config.mk
@@ -24,10 +24,13 @@
 # MA 02111-1307 USA
 #
 
-# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this
-# file with compatible flags
+# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these
+# files with compatible flags
 ifdef CONFIG_TEGRA2
 CFLAGS_arch/arm/lib/board.o += -march=armv4t
+CFLAGS_arch/arm/lib/memset.o += -march=armv4t
+CFLAGS_lib/string.o += -march=armv4t
+CFLAGS_common/cmd_nvedit.o += -march=armv4t
 endif
 
 USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c
index 0ef7753021..820ba4e902 100644
--- a/arch/arm/cpu/armv7/tegra2/funcmux.c
+++ b/arch/arm/cpu/armv7/tegra2/funcmux.c
@@ -31,11 +31,32 @@ int funcmux_select(enum periph_id id, int config)
 
 	switch (id) {
 	case PERIPH_ID_UART1:
-		if (config == FUNCMUX_UART1_IRRX_IRTX) {
+		switch (config) {
+		case FUNCMUX_UART1_IRRX_IRTX:
 			pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
 			pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
 			pinmux_tristate_disable(PINGRP_IRRX);
 			pinmux_tristate_disable(PINGRP_IRTX);
+			break;
+		case FUNCMUX_UART1_UAA_UAB:
+			pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
+			pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PINGRP_UAA);
+			pinmux_tristate_disable(PINGRP_UAB);
+			bad_config = 0;
+			break;
+		case FUNCMUX_UART1_GPU:
+			pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PINGRP_GPU);
+			bad_config = 0;
+			break;
+		case FUNCMUX_UART1_SDIO1:
+			pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PINGRP_SDIO1);
+			bad_config = 0;
+			break;
+		}
+		if (!bad_config) {
 			/*
 			 * Tegra appears to boot with function UARTA pre-
 			 * selected on mux group SDB. If two mux groups are
@@ -106,6 +127,13 @@ int funcmux_select(enum periph_id id, int config)
 		}
 		break;
 
+	case PERIPH_ID_SDMMC1:
+		if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
+			pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+			pinmux_tristate_disable(PINGRP_SDIO1);
+		}
+		break;
+
 	case PERIPH_ID_SDMMC2:
 		if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
 			pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);