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authorTom Rini <trini@konsulko.com>2021-04-05 11:29:57 -0400
committerTom Rini <trini@konsulko.com>2021-04-05 11:29:57 -0400
commit90eba245a66aa20589404ba537215faf2012c1a3 (patch)
treec581cd1f00dd162aeac4262bb4e74c2a9fea98c9 /arch/arm/dts/zynqmp-zcu216-revA.dts
parentb46dd116ce03e235f2a7d4843c6278e1da44b5e1 (diff)
parentdb8b46120aed6554d1ff405260ea6d2cc2439fcc (diff)
downloadu-boot-90eba245a66aa20589404ba537215faf2012c1a3.tar.gz
Merge branch 'next'
Diffstat (limited to 'arch/arm/dts/zynqmp-zcu216-revA.dts')
-rw-r--r--arch/arm/dts/zynqmp-zcu216-revA.dts63
1 files changed, 52 insertions, 11 deletions
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 511727fa95..2302b07c48 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -120,6 +120,20 @@
compatible = "iio-hwmon";
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
};
+
+ /* 48MHz reference crystal */
+ ref48: ref48M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+};
+
+&psgtr {
+ status = "okay";
+ /* pcie, sata, usb3, dp */
+ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ clock-names = "ref0", "ref1", "ref2", "ref3";
};
&dcc {
@@ -408,10 +422,41 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u43 */
- compatible = "si5341";
+ compatible = "silabs,si5341";
reg = <0x36>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&ref48>;
+ clock-names = "xtal";
+ clock-output-names = "si5341";
+
+ si5341_2: out@2 {
+ /* refclk2 for PS-GT, used for USB3 */
+ reg = <2>;
+ always-on; /* assigned-clocks does not enable, so do it here */
+ };
+ si5341_3: out@3 {
+ /* refclk3 for PS-GT, used for SATA */
+ reg = <3>;
+ always-on; /* assigned-clocks does not enable, so do it here */
+ };
+ si5341_5: out@5 {
+ /* refclk5 PL CLK100 */
+ reg = <5>;
+ always-on; /* assigned-clocks does not enable, so do it here */
+ };
+ si5341_6: out@6 {
+ /* refclk6 PL CLK125 */
+ reg = <6>;
+ always-on; /* assigned-clocks does not enable, so do it here */
+ };
+ si5341_9: out@9 {
+ /* refclk9 used for PS_REF_CLK 33.3 MHz */
+ reg = <9>;
+ always-on; /* assigned-clocks does not enable, so do it here */
+ };
};
-
};
i2c_si570_user_c0: i2c@2 {
#address-cells = <1>;
@@ -445,7 +490,10 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- /* U409B - 8a34001 */
+ idt_8a34001: phc@5b {
+ compatible = "idt,8a34001"; /* u409B */
+ reg = <0x5b>;
+ };
};
i2c_clk104: i2c@5 {
#address-cells = <1>;
@@ -557,8 +605,7 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
- phy-names = "sata-phy";
- phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* SD1 with level shifter */
@@ -572,10 +619,6 @@
xlnx,mio-bank = <1>;
};
-&serdes {
- status = "okay";
-};
-
&uart0 {
status = "okay";
};
@@ -589,6 +632,4 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
- phy-names = "usb3-phy";
- phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
};