diff options
| author | Priyanka Jain <priyanka.jain@nxp.com> | 2018-10-29 09:11:29 +0000 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-12-06 14:37:19 -0800 |
| commit | d6fdec211f7913c97917ba262fa257fdcb6b000e (patch) | |
| tree | d4cbd076e35f9c0584230916eb94e5cd88173dda /arch/arm/include/asm/arch-fsl-layerscape | |
| parent | db1e3df7ce71369a6b48382550df661f41dd5826 (diff) | |
| download | u-boot-d6fdec211f7913c97917ba262fa257fdcb6b000e.tar.gz | |
armv8:fsl-layerscape: Add support for Chassis 3.2
NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.
Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 13 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 |
2 files changed, 22 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 3926aa3039..eaa9ed251e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * Copyright 2014-2015, Freescale Semiconductor */ @@ -12,15 +12,19 @@ #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#endif #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#endif #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 @@ -40,8 +44,15 @@ #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#ifdef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 +#else #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#endif #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 8ddff55dac..ba37b89b3a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright (C) 2017 NXP Semiconductors + * Copyright 2017-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -21,7 +21,9 @@ #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#endif #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 @@ -45,6 +47,12 @@ #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#ifdef CONFIG_NXP_LSCH3_2 +#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) +#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) +#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) +#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) +#endif #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) @@ -83,7 +91,7 @@ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) #ifdef CONFIG_TFABOOT -#ifdef CONFIG_FSL_LSCH3_2 +#ifdef CONFIG_NXP_LSCH3_2 /* RCW_SRC field in Power-On Reset Control Register 1 */ #define RCW_SRC_MASK 0x07800000 #define RCW_SRC_BIT 23 |