diff options
author | Nicolas Ferre <nicolas.ferre@microchip.com> | 2019-08-08 07:48:23 +0000 |
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committer | Eugen Hristev <eugen.hristev@microchip.com> | 2019-10-08 09:16:11 +0300 |
commit | 00561e7d24e0d1986a6ed896003a03618a9ca17c (patch) | |
tree | 71c8198335f36e217f5a80304606bc2c727d51a2 /arch/arm/mach-at91/armv7 | |
parent | 61ba1244b548463dbfb3c5285b6b22e7c772c5bd (diff) | |
download | u-boot-00561e7d24e0d1986a6ed896003a03618a9ca17c.tar.gz |
ARM: at91: Add the chip ID for SAMA5D2 LPDDR2 SiP
The SAMA5D2 LPDDR2 SiP (System in Package) is added for SoC
identification.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Diffstat (limited to 'arch/arm/mach-at91/armv7')
-rw-r--r-- | arch/arm/mach-at91/armv7/sama5d2_devices.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c index 59a0c44913..9e9d026c3e 100644 --- a/arch/arm/mach-at91/armv7/sama5d2_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -57,8 +57,16 @@ char *get_cpu_name(void) return "SAMA5D27 512M bits DDR2 SDRAM"; case ARCH_EXID_SAMA5D27C_D1G: return "SAMA5D27 1G bits DDR2 SDRAM"; + case ARCH_EXID_SAMA5D27C_LD1G: + return "SAMA5D27 1G bits LPDDR2 SDRAM"; + case ARCH_EXID_SAMA5D27C_LD2G: + return "SAMA5D27 2G bits LPDDR2 SDRAM"; case ARCH_EXID_SAMA5D28C_D1G: return "SAMA5D28 1G bits DDR2 SDRAM"; + case ARCH_EXID_SAMA5D28C_LD1G: + return "SAMA5D28 1G bits LPDDR2 SDRAM"; + case ARCH_EXID_SAMA5D28C_LD2G: + return "SAMA5D28 2G bits LPDDR2 SDRAM"; } } |