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authorMugunthan V N <mugunthanvnm@ti.com>2017-04-07 13:42:00 +0200
committerSimon Glass <sjg@chromium.org>2017-04-14 19:38:57 -0600
commit01a072c6cf0539e7b8e78cce7f1f53884121646a (patch)
treef0eba8cdb29569344f03edf18156c26e0969b3a3 /arch/arm/mach-omap2/omap5
parentfbeb33752999e7317113199ef89873d6b6916814 (diff)
downloadu-boot-01a072c6cf0539e7b8e78cce7f1f53884121646a.tar.gz
arm: omap: sata: move enable sata clocks to enable_basic_clocks()
All the clocks which has to be enabled has to be done in enable_basic_clocks(), so moving enable sata clock to common clocks enable function. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap5')
-rw-r--r--arch/arm/mach-omap2/omap5/hw_data.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index 5d956b5b14..a8a6b8a869 100644
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -361,6 +361,9 @@ void enable_basic_clocks(void)
(*prcm)->cm_l4per_gpio6_clkctrl,
(*prcm)->cm_l4per_gpio7_clkctrl,
(*prcm)->cm_l4per_gpio8_clkctrl,
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ (*prcm)->cm_l3init_ocp2scp3_clkctrl,
+#endif
0
};
@@ -379,6 +382,9 @@ void enable_basic_clocks(void)
#ifdef CONFIG_TI_QSPI
(*prcm)->cm_l4per_qspi_clkctrl,
#endif
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ (*prcm)->cm_l3init_sata_clkctrl,
+#endif
0
};
@@ -411,6 +417,12 @@ void enable_basic_clocks(void)
setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
#endif
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ /* Enable optional functional clock for SATA */
+ setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+ SATA_CLKCTRL_OPTFCLKEN_MASK);
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);