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| author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | 2016-03-29 17:29:10 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2016-04-01 09:52:28 +0200 |
| commit | d96ebc468d0dff6eb6f069bba03b3f0e33aa22de (patch) | |
| tree | bea23e84de4e9fd04545a5b8c384fd4b13081229 /arch/arm/mach-sunxi/board.c | |
| parent | 0ea5a04fbcd72ebb37eb4b3f744374fdf551d3b7 (diff) | |
| download | u-boot-d96ebc468d0dff6eb6f069bba03b3f0e33aa22de.tar.gz | |
sunxi: Add support for Allwinner A64 SoCs
The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.
Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/mach-sunxi/board.c')
| -rw-r--r-- | arch/arm/mach-sunxi/board.c | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index bf58fa90ec..20149dabc8 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -40,6 +40,30 @@ struct fel_stash { struct fel_stash fel_stash __attribute__((section(".data"))); +#ifdef CONFIG_MACH_SUN50I +#include <asm/armv8/mmu.h> + +static struct mm_region sunxi_mem_map[] = { + { + /* SRAM, MMIO regions */ + .base = 0x0UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, { + /* RAM */ + .base = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; +struct mm_region *mem_map = sunxi_mem_map; +#endif + static int gpio_init(void) { #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) @@ -76,6 +100,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); @@ -265,7 +293,7 @@ void reset_cpu(ulong addr) #endif } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ |