net: replace the "xfi" phy-mode with "10gbase-r"

As part of the effort of making U-Boot work with the same device tree as
Linux, there is an issue with the "xfi" phy-mode. To be precise, in
Linux there was a discussion (for those who have time to read:
https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/)

which led to a patch:
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881

TL;DR: "xfi" was standardized in Linux as "10gbase-r".

This patch changes the relevant occurrences in U-Boot to use "10gbase-r"
instead of "xfi" wherever applicable.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

9 files changed, 28 insertions, 28 deletions

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d0103fc881..1a359d060e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1147,7 +1147,7 @@ int arch_early_init_r(void)
 #endif
 #ifdef CONFIG_SYS_FSL_HAS_RGMII
 	/* some dpmacs in armv8a based freescale layerscape SOCs can be
-	 * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
+	 * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
 	 * EC*_PMUX(rgmii) bits in RCW.
 	 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
 	 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index f33d05d053..f2efd4cc1d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features:
    - Hardware buffer management for buffer allocation and de-allocation (BMan)
    - Cryptography acceleration (SEC)
  - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
+   - Up to 1 x 10GBase-R supporting 10G interface
    - Up to 1 x QSGMII
    - Up to 4 x SGMII supporting 1000Mbps
    - Up to 2 x SGMII supporting 2500Mbps
@@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features:
    - Two PLLs per four-lane SerDes
    - Support for 10G operation
  - Ethernet interfaces by FMan
-   - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+   - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
    - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
    - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
    - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
@@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features:
   Single WRIOP tile supporting 130Gbps using 18 MACs
   Support for 10G-SXGMII (aka USXGMII).
   Support for SGMII (and 1000Base-KX)
-  Support for XFI (and 10GBase-KR)
+  Support for 10GBase-R (and 10GBase-KR)
   Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
   Support for XLAUI (and 40GBase-KR4) for 40G.
   Support for two RGMII parallel interfaces.
@@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features:
   Ethernet interfaces
   Support for 10G-SXGMII (aka USXGMII).
   Support for SGMII (and 1000Base-KX)
-  Support for XFI (and 10GBase-KR)
+  Support for 10GBase-R (and 10GBase-KR)
   Support for CAUI2 (50G) and 25G-AUI(25G).
   Support for XLAUI (and 40GBase-KR4) for 40G.
   Support for two RGMII parallel interfaces.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
index 280afbbf98..26f8a49826 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
@@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
 	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 	/*
-	 * LS1044A/1048A  support only one XFI port
+	 * LS1044A/1048A  support only one 10GBase-R port
 	 * Disable MAC1 for LS1044A/1048A
 	 */
 	if (serdes == FSL_SRDS_1 && lane == 2) {
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
index e0a6c04835..df39cca696 100644
--- a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
@@ -9,12 +9,12 @@
 
 &dpmac1 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac2 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac4 {
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
index 65e95300ab..99f74c2fc4 100644
--- a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
@@ -9,10 +9,10 @@
 
 &dpmac1 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac2 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
index ccbb5de1ea..72297f48ca 100644
--- a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
+++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
@@ -9,40 +9,40 @@
 
 &dpmac1 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac2 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac3 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac4 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac5 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac6 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac7 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac8 {
 	status = "okay";
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index 179ed19bf2..9e68c147e6 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -24,49 +24,49 @@
 &dpmac1 {
 	status = "okay";
 	phy-handle = <&mdio1_phy1>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac2 {
 	status = "okay";
 	phy-handle = <&mdio1_phy2>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac3 {
 	status = "okay";
 	phy-handle = <&mdio1_phy3>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac4 {
 	status = "okay";
 	phy-handle = <&mdio1_phy4>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac5 {
 	status = "okay";
 	phy-handle = <&mdio2_phy1>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac6 {
 	status = "okay";
 	phy-handle = <&mdio2_phy2>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac7 {
 	status = "okay";
 	phy-handle = <&mdio2_phy3>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &dpmac8 {
 	status = "okay";
 	phy-handle = <&mdio2_phy4>;
-	phy-connection-type = "xfi";
+	phy-connection-type = "10gbase-r";
 };
 
 &emdio1 {
diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi
index 2f1e63a6ae..3aa7fddc32 100644
--- a/arch/arm/dts/fsl-sch-30841.dtsi
+++ b/arch/arm/dts/fsl-sch-30841.dtsi
@@ -9,7 +9,7 @@
  * SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
  * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
  * together on a single lane or mapped 1:1 to serdes lanes.
- * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
+ * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, 10GBase-R.
  * PHY addresses are 0x00 - 0x03.
  * On the card the first port is the bottom port (closest to PEX connector).
  */
diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi
index 6a68b1849e..b3c0c2bc35 100644
--- a/arch/arm/dts/fsl-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-sch-30842.dtsi
@@ -8,7 +8,7 @@
 /*
  * SCH-30842 is a single port add-on card used with various FSL QDS boards.
  * It integrates a AQR112 PHY, which supports several protocols - SGMII,
- * SGMII-2500, USXGMII, XFI.
+ * SGMII-2500, USXGMII, 10GBase-R.
  * PHY address is 0x02.
  */
 phy@02 {