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| author | Tom Rini <trini@konsulko.com> | 2018-05-15 08:29:24 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-15 08:29:24 -0400 |
| commit | c75990889d35a87d0a14bd385e484756d72d29cd (patch) | |
| tree | 98f9a454f3acb9506be5ddc6b5f934a56d3078c5 /arch/arm | |
| parent | b70fe965bb4c780f27efcc7aac0fd845c1825305 (diff) | |
| parent | 3ecec5aadd3c3039adfde6928bbe0104af4929d5 (diff) | |
| download | u-boot-c75990889d35a87d0a14bd385e484756d72d29cd.tar.gz | |
Merge branch 'master' of git://git.denx.de/u-boot-video
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/sun50i-a64.dtsi | 9 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/gpio.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/pwm.h | 12 |
3 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 65a344d9ce..a82a3d89af 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -319,6 +319,15 @@ }; }; + pwm: pwm@01c21400 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; + reg = <0x01c21400 0x8>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 3334fb51f0..e4fe54d8b8 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -172,6 +172,7 @@ enum sunxi_gpio_number { #define SUN8I_GPD_SDC1 3 #define SUNXI_GPD_LCD0 2 #define SUNXI_GPD_LVDS0 3 +#define SUNXI_GPD_PWM 2 #define SUN5I_GPE_SDC2 3 #define SUN8I_GPE_TWI2 3 diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h index 47eb433fb6..dca283c7a9 100644 --- a/arch/arm/include/asm/arch-sunxi/pwm.h +++ b/arch/arm/include/asm/arch-sunxi/pwm.h @@ -10,8 +10,15 @@ #define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4) #define SUNXI_PWM_CTRL_PRESCALE0(x) ((x) & 0xf) +#define SUNXI_PWM_CTRL_PRESCALE0_MASK 0xf #define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4) #define SUNXI_PWM_CTRL_POLARITY0(x) ((x) << 5) +#define SUNXI_PWM_CTRL_CH0_ACT_STA BIT(5) +#define SUNXI_PWM_CTRL_CLK_GATE BIT(6) + +#define SUNXI_PWM_CH0_PERIOD_MAX (0xffff) +#define SUNXI_PWM_CH0_PERIOD_PRD(x) ((x & 0xffff) << 16) +#define SUNXI_PWM_CH0_PERIOD_DUTY(x) ((x) & 0xffff) #define SUNXI_PWM_PERIOD_80PCT 0x04af03c0 @@ -30,4 +37,9 @@ #define SUNXI_PWM_MUX SUN8I_GPH_PWM #endif +struct sunxi_pwm { + u32 ctrl; + u32 ch0_period; +}; + #endif |