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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2022-10-25 23:03:50 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-11-03 13:27:56 +0800 |
| commit | a5dfa3b8a0f7ad555495bad1386613d2de4ba619 (patch) | |
| tree | 74a91e18cd008f381c12d615587912630530bed3 /arch/riscv/lib | |
| parent | c8d9ff634fc429db5acf2f5386ea937f0fef1ae7 (diff) | |
| download | u-boot-a5dfa3b8a0f7ad555495bad1386613d2de4ba619.tar.gz | |
riscv: Rename Andes PLIC to PLICSW
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib')
| -rw-r--r-- | arch/riscv/lib/Makefile | 2 | ||||
| -rw-r--r-- | arch/riscv/lib/andes_plicsw.c (renamed from arch/riscv/lib/andes_plic.c) | 26 |
2 files changed, 14 insertions, 14 deletions
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 06020fcc2a..d6a8ae9728 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -13,7 +13,7 @@ obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o -obj-$(CONFIG_ANDES_PLIC) += andes_plic.o +obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o else obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plicsw.c index 1eabcacd09..324eb445aa 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -37,8 +37,8 @@ static int enable_ipi(int hart) unsigned int en; en = ENABLE_HART_IPI << hart; - writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); - writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart)); return 0; } @@ -46,14 +46,14 @@ static int enable_ipi(int hart) int riscv_init_ipi(void) { int ret; - long *base = syscon_get_first_range(RISCV_SYSCON_PLIC); + long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW); ofnode node; struct udevice *dev; u32 reg; if (IS_ERR(base)) return PTR_ERR(base); - gd->arch.plic = base; + gd->arch.plicsw = base; ret = uclass_find_first_device(UCLASS_CPU, &dev); if (ret) @@ -88,7 +88,7 @@ int riscv_send_ipi(int hart) { unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); - writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, + writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw, gd->arch.boot_hart)); return 0; @@ -98,8 +98,8 @@ int riscv_clear_ipi(int hart) { u32 source_id; - source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); - writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart)); + source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plicsw, hart)); + writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plicsw, hart)); return 0; } @@ -108,21 +108,21 @@ int riscv_get_ipi(int hart, int *pending) { unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); - *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, gd->arch.boot_hart)); *pending = !!(*pending & ipi); return 0; } -static const struct udevice_id andes_plic_ids[] = { - { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC }, +static const struct udevice_id andes_plicsw_ids[] = { + { .compatible = "andestech,plicsw", .data = RISCV_SYSCON_PLICSW }, { } }; -U_BOOT_DRIVER(andes_plic) = { - .name = "andes_plic", +U_BOOT_DRIVER(andes_plicsw) = { + .name = "andes_plicsw", .id = UCLASS_SYSCON, - .of_match = andes_plic_ids, + .of_match = andes_plicsw_ids, .flags = DM_FLAG_PRE_RELOC, }; |