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authorTom Rini <trini@konsulko.com>2017-08-01 15:38:32 -0400
committerTom Rini <trini@konsulko.com>2017-08-01 15:38:32 -0400
commit07d778382200a05a8b86cc135f79ec48e386f25a (patch)
tree624dc01190640212a9a8a45f4d12d4bd7489145d /board/google
parent5c6631beb27491f3f78b6a0ad888d38810e3d96b (diff)
parent24357dfd2aec4118b9178d8bf639fb8fc02e1859 (diff)
downloadu-boot-07d778382200a05a8b86cc135f79ec48e386f25a.tar.gz
Merge git://git.denx.de/u-boot-x86
Diffstat (limited to 'board/google')
-rw-r--r--board/google/chromebook_link/Kconfig1
-rw-r--r--board/google/chromebook_link/link.c16
-rw-r--r--board/google/chromebook_samus/Kconfig1
-rw-r--r--board/google/chromebook_samus/samus.c11
-rw-r--r--board/google/chromebox_panther/Kconfig1
-rw-r--r--board/google/chromebox_panther/panther.c11
6 files changed, 3 insertions, 38 deletions
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 8999b58294..944716d002 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_IVYBRIDGE
select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
+ select SPI_FLASH_WINBOND
config PCIE_ECAM_BASE
default 0xf0000000
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 42615e1e23..dc22592095 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -5,19 +5,3 @@
*/
#include <common.h>
-#include <cros_ec.h>
-#include <dm.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
- return 0;
-}
-
-int board_early_init_f(void)
-{
- return 0;
-}
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
index f2b9481563..afbfe53deb 100644
--- a/board/google/chromebook_samus/Kconfig
+++ b/board/google/chromebook_samus/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select INTEL_BROADWELL
select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
+ select SPI_FLASH_WINBOND
config PCIE_ECAM_BASE
default 0xf0000000
diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c
index 3c3f5d4833..5b5eb19ee8 100644
--- a/board/google/chromebook_samus/samus.c
+++ b/board/google/chromebook_samus/samus.c
@@ -5,14 +5,3 @@
*/
#include <common.h>
-#include <asm/cpu.h>
-
-int arch_early_init_r(void)
-{
- return cpu_run_reference_code();
-}
-
-int board_early_init_f(void)
-{
- return 0;
-}
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index 2af3aa9e74..875df9d59f 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_IVYBRIDGE
select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
+ select SPI_FLASH_WINBOND
config SYS_CAR_ADDR
hex
diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c
index e3baf88783..2adc202be0 100644
--- a/board/google/chromebox_panther/panther.c
+++ b/board/google/chromebox_panther/panther.c
@@ -5,14 +5,3 @@
*/
#include <common.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
- return 0;
-}
-
-int board_early_init_f(void)
-{
- return 0;
-}