diff options
| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2023-05-03 08:38:16 +0200 |
|---|---|---|
| committer | Christophe Leroy <christophe.leroy@csgroup.eu> | 2023-05-04 10:58:07 +0200 |
| commit | 019b39b7366e5591949f6d41aeac474b632be704 (patch) | |
| tree | 141ca7c4bfc5b1bbfd681333de99fc4c6e493d9e /board | |
| parent | 756af9ab830dea30e8f5f4f4962050d87575820f (diff) | |
| download | u-boot-019b39b7366e5591949f6d41aeac474b632be704.tar.gz | |
board: cssi: Load CMPC885's motherboard FPGA earlier
In order to know the motherboard type earlier, perform I/O ports
initialisation and FPGA loading in board_early_init_f() instead
of board_early_init_r().
This is needed to be able to load mpc8xx CPM microcode base on
motherboard type and before starting to use the CPM.
Console is not available yet so remove the printfs.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Diffstat (limited to 'board')
| -rw-r--r-- | board/cssi/cmpc885/cmpc885.c | 25 |
1 files changed, 5 insertions, 20 deletions
diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c index 02da4d9a87..40128f170a 100644 --- a/board/cssi/cmpc885/cmpc885.c +++ b/board/cssi/cmpc885/cmpc885.c @@ -586,13 +586,8 @@ void iop_setup_miae(void) setbits_be32(&cp->cp_peso, 0x00031980); } -int board_early_init_f(void) -{ - return 0; -} - /* Specific board initialization */ -int board_early_init_r(void) +int board_early_init_f(void) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; iop8xx_t __iomem *iop = &immr->im_ioport; @@ -864,8 +859,6 @@ int board_early_init_r(void) /* Check if fpga firmware is loaded */ if (!(in_be32(&cp->cp_pedat) & 0x00000001)) { - printf("Reloading FPGA firmware.\n"); - /* Load fpga firmware */ /* Activate PROG_FPGA_FIRMWARE for 1 usec */ clrbits_be32(&cp->cp_pedat, 0x00000002); @@ -874,12 +867,8 @@ int board_early_init_r(void) /* Wait 200 msec and check DONE_FPGA_FIRMWARE */ mdelay(200); - if (!(in_be32(&cp->cp_pedat) & 0x00000001)) { - for (;;) { - printf("error loading firmware.\n"); - mdelay(500); - } - } + if (!(in_be32(&cp->cp_pedat) & 0x00000001)) + hang(); /* Send a reset signal and wait for 20 msec */ clrbits_be16(ADDR_CPLD_R_RESET, R_RST_STATUS); @@ -889,12 +878,8 @@ int board_early_init_r(void) /* Wait 300 msec and check the reset state */ mdelay(300); - if (!(in_be16(ADDR_CPLD_R_RESET) & R_RESET_STATUS)) { - for (;;) { - printf("Could not reset FPGA.\n"); - mdelay(500); - } - } + if (!(in_be16(ADDR_CPLD_R_RESET) & R_RESET_STATUS)) + hang(); iop_setup_common(); } else { |