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| author | Tom Rini <trini@konsulko.com> | 2022-03-15 08:42:36 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-03-15 08:42:36 -0400 |
| commit | ababaa4a275b473bb4463b70d93e8faeebb24698 (patch) | |
| tree | 3703f5bba5b169ff2cc78b7a0d14b77df72b33a7 /drivers/video | |
| parent | 4dc9b1771b152838ddfc4ae86a0ab9fd53ea16f7 (diff) | |
| parent | 19fbe102b2e21db949a66d9020da097769bbdb3c (diff) | |
| download | u-boot-ababaa4a275b473bb4463b70d93e8faeebb24698.tar.gz | |
Merge tag 'u-boot-stm32-20220315' of https://source.denx.de/u-boot/custodians/u-boot-stm
mtd: add NAND write protect support to stm32_fmc2_nand
stm32mp1 bsec: Add permanent lock write support
stm32mp1 bsec: Add dev in function description
cmd_stboard: Update test on misc_read() result
video: fix the check of return value of clk_set_rate in stm32_ltdc
DT: Alignment with kernel v5.17 for stm32mp15
DT: Add USB OTG pinctrl and regulator in SPL for DHCOR
DT: Move vdd_io extras into Avenger96 extras
DT: Add DFU support for DHCOM recovery
ram: stm32mp1: Unconditionally enable ASR
psci: Implement PSCI system suspend and DRAM SSR for stm32mp
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/stm32/stm32_ltdc.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 87e5fd54d9..e741e74739 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -338,6 +338,7 @@ static int stm32_ltdc_probe(struct udevice *dev) struct display_timing timings; struct clk pclk; struct reset_ctl rst; + ulong rate; int ret; priv->regs = (void *)dev_read_addr(dev); @@ -375,13 +376,13 @@ static int stm32_ltdc_probe(struct udevice *dev) } } - ret = clk_set_rate(&pclk, timings.pixelclock.typ); - if (ret) - dev_warn(dev, "fail to set pixel clock %d hz\n", - timings.pixelclock.typ); + rate = clk_set_rate(&pclk, timings.pixelclock.typ); + if (IS_ERR_VALUE(rate)) + dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n", + timings.pixelclock.typ, rate); dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n", - timings.pixelclock.typ, clk_get_rate(&pclk)); + timings.pixelclock.typ, rate); ret = reset_get_by_index(dev, 0, &rst); if (ret) { |