summaryrefslogtreecommitdiff
path: root/include/dt-bindings
diff options
context:
space:
mode:
authorRyan Chen <ryan_chen@aspeedtech.com>2020-12-14 13:54:23 +0800
committerTom Rini <trini@konsulko.com>2021-01-18 15:14:56 -0500
commita3c85990c36508cf7a5e7be82a275b2033400118 (patch)
treed1de5da91c489c8baf897bc819cfd1e1b69596d3 /include/dt-bindings
parent34a5addb7b57cb5a0ad5940ff7ef1df7edb0ff55 (diff)
downloadu-boot-a3c85990c36508cf7a5e7be82a275b2033400118.tar.gz
clk: aspeed: Add AST2600 clock support
This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/ast2600-clock.h62
1 files changed, 62 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
new file mode 100644
index 0000000000..36294a5140
--- /dev/null
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#define ASPEED_CLK_GATE_ECLK 0
+#define ASPEED_CLK_GATE_GCLK 1
+#define ASPEED_CLK_GATE_MCLK 2
+#define ASPEED_CLK_GATE_VCLK 3
+#define ASPEED_CLK_GATE_BCLK 4
+#define ASPEED_CLK_GATE_DCLK 5
+#define ASPEED_CLK_GATE_LCLK 6
+#define ASPEED_CLK_GATE_YCLK 7
+#define ASPEED_CLK_GATE_LHCCLK 8
+#define ASPEED_CLK_GATE_REFCLK 9
+#define ASPEED_CLK_GATE_ESPICLK 10
+#define ASPEED_CLK_GATE_UART1CLK 11
+#define ASPEED_CLK_GATE_UART2CLK 12
+#define ASPEED_CLK_GATE_UART3CLK 13
+#define ASPEED_CLK_GATE_UART4CLK 14
+#define ASPEED_CLK_GATE_UART5CLK 15
+#define ASPEED_CLK_GATE_UART6CLK 16
+#define ASPEED_CLK_GATE_UART7CLK 17
+#define ASPEED_CLK_GATE_UART8CLK 18
+#define ASPEED_CLK_GATE_UART9CLK 19
+#define ASPEED_CLK_GATE_UART10CLK 20
+#define ASPEED_CLK_GATE_UART11CLK 21
+#define ASPEED_CLK_GATE_UART12CLK 22
+#define ASPEED_CLK_GATE_UART13CLK 23
+#define ASPEED_CLK_GATE_MAC1CLK 24
+#define ASPEED_CLK_GATE_MAC2CLK 25
+#define ASPEED_CLK_GATE_MAC3CLK 26
+#define ASPEED_CLK_GATE_MAC4CLK 27
+#define ASPEED_CLK_GATE_RSACLK 28
+#define ASPEED_CLK_GATE_SDCLK 29
+#define ASPEED_CLK_GATE_SDEXTCLK 30
+#define ASPEED_CLK_GATE_EMMCCLK 31
+#define ASPEED_CLK_GATE_EMMCEXTCLK 32
+#define ASPEED_CLK_GATE_USBUHCICLK 33
+#define ASPEED_CLK_GATE_USBPORT1CLK 34
+#define ASPEED_CLK_GATE_USBPORT2CLK 35
+#define ASPEED_CLK_GATE_FSICLK 36
+
+#define ASPEED_CLK_APLL 37
+#define ASPEED_CLK_EPLL 38
+#define ASPEED_CLK_DPLL 39
+#define ASPEED_CLK_HPLL 40
+#define ASPEED_CLK_AHB 41
+#define ASPEED_CLK_APB1 42
+#define ASPEED_CLK_APB2 43
+#define ASPEED_CLK_UART 44
+#define ASPEED_CLK_SDIO 45
+#define ASPEED_CLK_ECLK 46
+#define ASPEED_CLK_ECLK_MUX 47
+#define ASPEED_CLK_LHCLK 48
+#define ASPEED_CLK_MAC 49
+#define ASPEED_CLK_BCLK 50
+#define ASPEED_CLK_MPLL 51
+#define ASPEED_CLK_24M 52
+#define ASPEED_CLK_EMMC 53
+#define ASPEED_CLK_UARTX 54
+#define ASPEED_CLK_HUARTX 55