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authorTom Rini <trini@konsulko.com>2019-01-21 11:59:21 -0500
committerTom Rini <trini@konsulko.com>2019-01-21 11:59:21 -0500
commite8ddbefccd0193340ebbe6fe53c5490624b7c110 (patch)
tree7d42f09133a50b773ffd2ba213883b23c5f4265f /include
parent27fb313dd639efc72beb08124fe4aa37bfd2c299 (diff)
parent0e31666dfa043ab71fb1fbbba4feacfe8af3e06b (diff)
downloadu-boot-e8ddbefccd0193340ebbe6fe53c5490624b7c110.tar.gz
Merge git://git.denx.de/u-boot-marvell
- Sync Armada-38x dts with Linux 4.20 from Chris - Misc changes and enhancements to Turris Mox (v4) from Marek - Reserve PSCI area for Armada 8k from Heinrich - New Allied Telesis x530 board (Armada-385) from Chris - Misc minor changes (defconfig etc)
Diffstat (limited to 'include')
-rw-r--r--include/configs/turris_mox.h2
-rw-r--r--include/configs/x530.h134
2 files changed, 136 insertions, 0 deletions
diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h
index 0aebe2100b..82cdccecc1 100644
--- a/include/configs/turris_mox.h
+++ b/include/configs/turris_mox.h
@@ -8,6 +8,8 @@
#ifndef _CONFIG_TURRIS_MOX_H
#define _CONFIG_TURRIS_MOX_H
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
#define CONFIG_LAST_STAGE_INIT
/*
diff --git a/include/configs/x530.h b/include/configs/x530.h
new file mode 100644
index 0000000000..a1ef301d35
--- /dev/null
+++ b/include/configs/x530.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Allied Telesis Labs
+ */
+
+#ifndef _CONFIG_X530_H
+#define _CONFIG_X530_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
+#endif
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_PCI
+
+/* NAND */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define BBT_CUSTOM_SCAN
+#define BBT_CUSTOM_SCAN_PAGE 0
+#define BBT_CUSTOM_SCAN_POSITION 2048
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
+#define MTDPARTS_MTDOOPS "errlog"
+
+/* Partition support */
+
+/* Additional FS support/configuration */
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* NAND */
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_SYS_MALLOC_LEN (4 << 20)
+
+#include <asm/arch/config.h>
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Keep device tree and initrd in low memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+#define CONFIG_SYS_LOAD_ADDR 0x1000000
+#define CONFIG_UBI_PART user
+#define CONFIG_UBIFS_VOLUME user
+
+/* SPL */
+
+/* Defines for SPL */
+#define CONFIG_SPL_SIZE (140 << 10)
+#define CONFIG_SPL_TEXT_BASE 0x40000030
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+
+#endif /* _CONFIG_X530_H */