Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

1 files changed, 43 insertions, 34 deletions

diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c
index 16eeb61d85..9c356901b1 100644
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -27,51 +27,61 @@
 #include <asm/immap_85xx.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_law.h>
+#include <asm/global_data.h>
 
-#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); }
+DECLARE_GLOBAL_DATA_PTR;
 
 unsigned long ddr_freq_mhz;
 
 void sdram_init(void)
 {
 	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+	/* mask off E bit */
+	u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
 
-	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
-	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
-	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
-	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
-	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
 
 	if (ddr_freq_mhz < 700) {
-		out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667);
-		out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667);
-		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667);
-		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667);
-		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667);
-		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667);
-		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667);
-		out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667);
-		out_be32(&ddr->ddr_wrlvl_cntl,
-				CONFIG_SYS_DDR_WRLVL_CONTROL_667);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
+		__raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
+		__raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
+		__raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
+		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
+		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
 	} else {
-		out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800);
-		out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800);
-		out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800);
-		out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800);
-		out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800);
-		out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800);
-		out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800);
-		out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800);
-		out_be32(&ddr->ddr_wrlvl_cntl,
-				CONFIG_SYS_DDR_WRLVL_CONTROL_800);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+		__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+		__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+		__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+		__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
 	}
 
-	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
-	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
-	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+
+	/* P1014 and it's derivatives support max 16bit DDR width */
+	if (svr == SVR_P1014) {
+		__raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
+		__raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
+		/* For CS0_BNDS we divide the start and end address by 2, so we can just
+		 * shift the entire register to achieve the desired result and the mask
+		 * the value so we don't write reserved fields */
+		__raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
+	}
 
-	/* mimic 500us delay, with busy isync() loop */
-	udelay(100);
+	udelay(500);
 
 	/* Let the controller go */
 	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
@@ -82,20 +92,19 @@ void sdram_init(void)
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio, ddr_ratio;
-	unsigned long bus_clk;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
 	/* initialize selected port with appropriate baud rate */
 	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
-	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
 
 	ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
 	ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 	ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
 
 	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-			bus_clk / 16 / CONFIG_BAUDRATE);
+			gd->bus_clk / 16 / CONFIG_BAUDRATE);
 
 	puts("\nNAND boot... ");