diff options
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/board.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/secure_reg_helper.h | 19 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/smc_api.h | 13 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/mailbox_s10.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/reset_manager_s10.c | 13 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/secure_reg_helper.c | 89 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/smc_api.c | 56 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 |
11 files changed, 291 insertions, 4 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 26f2cf8e47..4d4ff16337 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,7 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE + select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -79,7 +79,7 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE + select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX choice diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543b20..82b681d870 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -70,6 +72,9 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += firewall.o obj-y += spl_agilex.o endif +else +obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o +obj-$(CONFIG_SPL_ATF) += smc_api.o endif ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 340abf9305..7993c27646 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -13,7 +13,7 @@ #include <asm/arch/clock_manager.h> #include <asm/arch/misc.h> #include <asm/io.h> - +#include <log.h> #include <usb.h> #include <usb/dwc2_udc.h> @@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void) return 1; } #endif + +#ifdef CONFIG_SPL_BUILD +__weak int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h new file mode 100644 index 0000000000..d5a11122c7 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Intel Corporation <www.intel.com> + * + */ + +#ifndef _SECURE_REG_HELPER_H_ +#define _SECURE_REG_HELPER_H_ + +#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1 +#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2 +#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3 +#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4 + +int socfpga_secure_reg_read32(u32 id, u32 *val); +int socfpga_secure_reg_write32(u32 id, u32 val); +int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val); + +#endif /* _SECURE_REG_HELPER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h b/arch/arm/mach-socfpga/include/mach/smc_api.h new file mode 100644 index 0000000000..bbefdd8dd9 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/smc_api.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Intel Corporation + */ + +#ifndef _SMC_API_H_ +#define _SMC_API_H_ + +int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len); +int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, + u32 *resp_buf); + +#endif /* _SMC_API_H_ */ diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S new file mode 100644 index 0000000000..612ea8a037 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +wait_for_atf: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, slave_wait_atf + br x5 +slave_wait_atf: + branch_if_slave x0, wait_for_atf +#else + branch_if_slave x0, 1f +#endif + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + +#ifdef CONFIG_ARMV8_MULTIENTRY + branch_if_master x0, x1, 2f + + /* + * Slave should wait for master clearing spin table. + * This sync prevent slaves observing incorrect + * value of spin table and jumping to wrong place. + */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* + * All slaves will enter EL2 and optionally EL1. + */ + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el2 + +lowlevel_in_el2: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el1 + +lowlevel_in_el1: +#endif + +#endif /* CONFIG_ARMV8_MULTIENTRY */ + +2: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 18d44924e6..429444f069 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -11,6 +11,7 @@ #include <asm/arch/mailbox_s10.h> #include <asm/arch/system_manager.h> #include <asm/secure.h> +#include <asm/system.h> DECLARE_GLOBAL_DATA_PTR; @@ -398,6 +399,9 @@ error: int mbox_reset_cold(void) { +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + psci_system_reset(); +#else int ret; ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT, @@ -406,6 +410,7 @@ int mbox_reset_cold(void) /* mailbox sent failure, wait for watchdog to kick in */ hang(); } +#endif return 0; } diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 3746e6a60c..af8f2c0873 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -5,11 +5,14 @@ */ #include <common.h> +#include <hang.h> #include <asm/io.h> #include <asm/arch/reset_manager.h> +#include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> #include <dt-bindings/reset/altr,rst-mgr-s10.h> #include <linux/iopoll.h> +#include <linux/intel-smc.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,6 +58,15 @@ void socfpga_per_reset_all(void) void socfpga_bridges_reset(int enable) { +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + u64 arg = enable; + + int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); + if (ret) { + printf("SMC call failed with error %d in %s.\n", ret, __func__); + return; + } +#else u32 reg; if (enable) { @@ -101,6 +113,7 @@ void socfpga_bridges_reset(int enable) /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } +#endif } /* diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-socfpga/secure_reg_helper.c new file mode 100644 index 0000000000..0d4f45f33d --- /dev/null +++ b/arch/arm/mach-socfpga/secure_reg_helper.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <hang.h> +#include <asm/io.h> +#include <asm/system.h> +#include <asm/arch/misc.h> +#include <asm/arch/secure_reg_helper.h> +#include <asm/arch/smc_api.h> +#include <asm/arch/system_manager.h> +#include <linux/errno.h> +#include <linux/intel-smc.h> + +int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr) +{ + switch (id) { + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC: + *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC; + break; + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0: + *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0; + break; + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1: + *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1; + break; + case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2: + *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2; + break; + default: + return -EADDRNOTAVAIL; + } + return 0; +} + +int socfpga_secure_reg_read32(u32 id, u32 *val) +{ + int ret; + u64 ret_arg; + u64 args[1]; + + phys_addr_t reg_addr; + ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr); + if (ret) + return ret; + + args[0] = (u64)reg_addr; + ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1); + if (ret) + return ret; + + *val = (u32)ret_arg; + + return 0; +} + +int socfpga_secure_reg_write32(u32 id, u32 val) +{ + int ret; + u64 args[2]; + + phys_addr_t reg_addr; + ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr); + if (ret) + return ret; + + args[0] = (u64)reg_addr; + args[1] = val; + return invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0); +} + +int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val) +{ + int ret; + u64 args[3]; + + phys_addr_t reg_addr; + ret = socfpga_secure_convert_reg_id_to_addr(id, ®_addr); + if (ret) + return ret; + + args[0] = (u64)reg_addr; + args[1] = mask; + args[2] = val; + return invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0); +} diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c new file mode 100644 index 0000000000..085daba162 --- /dev/null +++ b/arch/arm/mach-socfpga/smc_api.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/ptrace.h> +#include <asm/system.h> +#include <linux/intel-smc.h> + +int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len) +{ + struct pt_regs regs; + + memset(®s, 0, sizeof(regs)); + regs.regs[0] = func_id; + + if (args) + memcpy(®s.regs[1], args, arg_len * sizeof(*args)); + + smc_call(®s); + + if (ret_arg) + memcpy(ret_arg, ®s.regs[1], ret_len * sizeof(*ret_arg)); + + return regs.regs[0]; +} + +int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, + u32 *resp_buf) +{ + int ret; + u64 args[6]; + u64 resp[3]; + + args[0] = cmd; + args[1] = (u64)arg; + args[2] = len; + args[3] = urgent; + args[4] = (u64)resp_buf; + if (resp_buf_len) + args[5] = *resp_buf_len; + else + args[5] = 0; + + ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args), + resp, ARRAY_SIZE(resp)); + + if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) { + if (!resp[0]) + *resp_buf_len = resp[1]; + } + + return (int)resp[0]; +} diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index 3da85791a1..049c5711a8 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -12,6 +12,7 @@ const struct cm_config * const cm_get_default_config(void) { +#ifdef CONFIG_SPL_BUILD struct cm_config *cm_handoff_cfg = (struct cm_config *) (S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA); u32 *conversion = (u32 *)cm_handoff_cfg; @@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void) } else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) { return cm_handoff_cfg; } - +#endif return NULL; } |