summaryrefslogtreecommitdiff
path: root/arch/riscv/cpu/ax25/Kconfig
Commit message (Expand)AuthorAgeFilesLines
* riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang2023-02-171-15/+0
* configs: ae350: Enable v5l2 cache for AE350 platforms in SPLYu Chien Peter Lin2023-02-171-0/+1
* riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang2023-02-171-10/+0
* riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin2022-11-031-1/+1
* cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass2021-03-271-1/+1
* timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson2020-10-261-1/+1
* riscv: Rework riscv timer driver to only support S-modeSean Anderson2020-09-301-1/+1
* riscv: ax25: add SPL supportRick Chen2019-12-101-1/+3
* riscv: ax25: add imply v5l2 cache controllerRick Chen2019-09-031-0/+1
* riscv: add run mode configuration for SPLLukas Auer2019-08-261-3/+3
* riscv: ax25: Andes specific cache shall only support in M-modeRick Chen2019-04-081-0/+1
* riscv: ax25: Add platform-specific Kconfig optionsRick Chen2019-04-081-0/+6
* riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng2018-12-181-5/+12
* riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen2018-11-261-0/+7
View Lorry Controller Status