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path: root/arch/riscv/cpu/start.S
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* riscv: fix the wrong swap value registerBrad Kim2020-12-141-1/+1
* riscv: Add some comments to start.SSean Anderson2020-09-301-2/+17
* riscv: Ensure gp is NULL or points to valid dataSean Anderson2020-09-301-3/+25
* riscv: Consolidate fences into AMOs for available_harts_lockSean Anderson2020-09-301-6/+3
* Revert "riscv: Clear pending interrupts before enabling IPIs"Sean Anderson2020-09-301-2/+0
* riscv: Fix linking error when building u-boot-spl with no SMP supportLeo Yu-Chi Liang2020-07-241-0/+2
* riscv: Clear pending interrupts before enabling IPIsSean Anderson2020-07-011-0/+2
* riscv: Provide a mechanism to fix DT for reserved memoryAtish Patra2020-04-231-0/+1
* riscv: Introduce SPL_SMP Kconfig option for U-Boot SPLBin Meng2020-04-231-7/+7
* riscv: Merge unnecessary SMP ifdefs in start.SBin Meng2020-04-231-4/+0
* riscv: Remove unnecessary instructionSean Anderson2020-02-101-3/+2
* common: Move relocate_code() to init.hSimon Glass2020-01-171-1/+1
* riscv: add option to wait for ack from secondary harts in smp functionsLukas Auer2019-12-101-0/+2
* riscv: Fix clear bss loop in the start-up codeRick Chen2019-12-101-2/+2
* riscv: update fix_rela_dynMarcus Comstedt2019-09-031-5/+5
* riscv: support SPL stack and global data relocationLukas Auer2019-08-261-1/+34
* riscv: add SPL supportLukas Auer2019-08-261-1/+22
* riscv: add run mode configuration for SPLLukas Auer2019-08-261-3/+3
* riscv: Access CSRs using CSR numbersBin Meng2019-08-151-2/+1
* riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen2019-05-091-0/+2
* riscv: Introduce CONFIG_XIP to support booting from flashRick Chen2019-05-091-0/+6
* riscv: hang if relocation of secondary harts failsLukas Auer2019-04-081-1/+12
* riscv: do not rely on hart ID passed by previous boot stageLukas Auer2019-04-081-0/+4
* riscv: add support for multi-hart systemsLukas Auer2019-04-081-1/+133
* riscv: save hart ID in register tp instead of s0Lukas Auer2019-04-081-2/+2
* riscv: delay initialization of caches and debug UARTLukas Auer2019-04-081-8/+8
* riscv: Save boot hart id to the global dataBin Meng2018-12-181-0/+4
* riscv: Move trap handler codes to mtrap.SBin Meng2018-12-181-89/+0
* riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen2018-12-051-2/+0
* riscv: Add kconfig option to run U-Boot in S-modeAnup Patel2018-12-051-8/+15
* riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen2018-11-261-0/+6
* riscv: save hart ID and device tree passed by prior boot stageLukas Auer2018-11-261-2/+10
* riscv: do not blindly modify the mstatus CSRLukas Auer2018-11-261-4/+4
* riscv: remove unused labels in start.SLukas Auer2018-11-261-9/+0
* Drop CONFIG_INIT_CRITICALBin Meng2018-11-261-13/+0
* riscv: align mtvec on a 4-byte boundaryLukas Auer2018-11-261-1/+1
* riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer2018-11-261-161/+161
* riscv: Make start.S available for all targetsBin Meng2018-10-031-0/+292
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