Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | watchdog: versal: Include header file needed for dev_ functions | Ashok Reddy Soma | 2021-08-26 | 1 | -0/+1 |
* | clk: zynq: Add dummy clock enable function | Michal Simek | 2021-02-23 | 1 | -2/+1 |
* | dm: Avoid accessing seq directly | Simon Glass | 2020-12-18 | 1 | -1/+1 |
* | dm: treewide: Rename ..._platdata variables to just ..._plat | Simon Glass | 2020-12-13 | 1 | -4/+4 |
* | dm: treewide: Rename ofdata_to_platdata() to of_to_plat() | Simon Glass | 2020-12-13 | 1 | -2/+2 |
* | dm: treewide: Rename dev_get_platdata() to dev_get_plat() | Simon Glass | 2020-12-13 | 1 | -2/+2 |
* | dm: treewide: Rename 'platdata' variables to just 'plat' | Simon Glass | 2020-12-13 | 1 | -7/+7 |
* | dm: treewide: Rename auto_alloc_size members to be shorter | Simon Glass | 2020-12-13 | 1 | -2/+2 |
* | watchdog: versal: Add support for Xilinx window watchdog | Ashok Reddy Soma | 2020-04-06 | 1 | -0/+179 |