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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2016 Freescale Semiconductor
*/
/include/ "skeleton64.dtsi"
/ {
compatible = "fsl,ls1012a";
interrupt-parent = <&gic>;
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
gic: interrupt-controller@1400000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x1401000 0 0x1000>, /* GICD */
<0x0 0x1402000 0 0x2000>, /* GICC */
<0x0 0x1404000 0 0x2000>, /* GICH */
<0x0 0x1406000 0 0x2000>; /* GICV */
interrupts = <1 9 0xf08>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1012a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 64 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
num-cs = <6>;
big-endian;
status = "disabled";
};
esdhc0: esdhc@1560000 {
compatible = "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
interrupts = <0 62 0x4>;
big-endian;
bus-width = <4>;
};
esdhc1: esdhc@1580000 {
compatible = "fsl,esdhc";
reg = <0x0 0x1580000 0x0 0x10000>;
interrupts = <0 65 0x4>;
big-endian;
non-removable;
bus-width = <4>;
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c1: i2c@2190000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <0 57 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <0 54 0x4>;
clocks = <&clockgen 4 0>;
};
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <0 54 0x4>;
clocks = <&clockgen 4 0>;
};
qspi: quadspi@1550000 {
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x4000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
status = "disabled";
};
pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
0x00 0x03480000 0x0 0x40000 /* lut registers */
0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
0x40 0x00000000 0x0 0x20000>; /* configuration space */
reg-names = "dbi", "lut", "ctrl", "config";
big-endian;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
sata: sata@3200000 {
compatible = "fsl,ls1012a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x0 0x20140520 0x0 0x4>; /* ecc sata addr */
reg-names = "sata-base", "ecc-addr";
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
};
usb0: usb2@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
interrupts = <0 139 0x4>;
dr_mode = "host";
fsl,usb-erratum-a005697;
};
usb1: usb3@2f00000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <0 61 0x4>;
dr_mode = "host";
};
};
};
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