blob: aaa490a74a7a07d989879e914ef8ac6072520e20 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
|
/*
* (C Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Setting IOMUXC */
DATA 4 0x73FA88a0 0x200
DATA 4 0x73FA850c 0x20c5
DATA 4 0x73FA8510 0x20c5
DATA 4 0x73FA883c 0x2
DATA 4 0x73FA8848 0x2
DATA 4 0x73FA84b8 0xe7
DATA 4 0x73FA84bc 0x45
DATA 4 0x73FA84c0 0x45
DATA 4 0x73FA84c4 0x45
DATA 4 0x73FA84c8 0x45
DATA 4 0x73FA8820 0x0
DATA 4 0x73FA84a4 0x3
DATA 4 0x73FA84a8 0x3
DATA 4 0x73FA84ac 0xe3
DATA 4 0x73FA84b0 0xe3
DATA 4 0x73FA84b4 0xe3
DATA 4 0x73FA84cc 0xe3
DATA 4 0x73FA84d0 0xe2
DATA 4 0x73FA882c 0x6
DATA 4 0x73FA88a4 0x6
DATA 4 0x73FA88ac 0x6
DATA 4 0x73FA88b8 0x6
/*
* Setting DDR for micron
* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
* CAS=3 BL=4
*/
/* ESDCTL_ESDCTL0 */
DATA 4 0x83FD9000 0x82a20000
/* ESDCTL_ESDCTL1 */
DATA 4 0x83FD9008 0x82a20000
/* ESDCTL_ESDMISC */
DATA 4 0x83FD9010 0x000ad0d0
/* ESDCTL_ESDCFG0 */
DATA 4 0x83FD9004 0x333574aa
/* ESDCTL_ESDCFG1 */
DATA 4 0x83FD900C 0x333574aa
/* Init DRAM on CS0 */
/* ESDCTL_ESDSCR */
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x0000801a
DATA 4 0x83FD9014 0x0000801b
DATA 4 0x83FD9014 0x00448019
DATA 4 0x83FD9014 0x07328018
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x00008010
DATA 4 0x83FD9014 0x00008010
DATA 4 0x83FD9014 0x06328018
DATA 4 0x83FD9014 0x03808019
DATA 4 0x83FD9014 0x00408019
DATA 4 0x83FD9014 0x00008000
/* Init DRAM on CS1 */
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x0000801e
DATA 4 0x83FD9014 0x0000801f
DATA 4 0x83FD9014 0x0000801d
DATA 4 0x83FD9014 0x0732801c
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x00008014
DATA 4 0x83FD9014 0x00008014
DATA 4 0x83FD9014 0x0632801c
DATA 4 0x83FD9014 0x0380801d
DATA 4 0x83FD9014 0x0040801d
DATA 4 0x83FD9014 0x00008004
/* Write to CTL0 */
DATA 4 0x83FD9000 0xb2a20000
/* Write to CTL1 */
DATA 4 0x83FD9008 0xb2a20000
/* ESDMISC */
DATA 4 0x83FD9010 0x000ad6d0
/* ESDCTL_ESDCDLYGD */
DATA 4 0x83FD9034 0x90000000
DATA 4 0x83FD9014 0x00000000
|
