blob: f3416b534b230d0ab2498ee75fc1f4f9e78fd329 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <linux/sizes.h>
#include "tegra30-common.h"
/* VDD core PMIC */
#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
/* High-level configuration options */
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
#define BOARD_EXTRA_ENV_SETTINGS \
"board_name=cardhu-a04\0" \
"fdtfile=tegra30-cardhu-a04.dtb\0"
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */
#define CONFIG_TEGRA_SLINK_CTRLS 6
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
|
