diff options
| author | Ilia Mirkin <imirkin@alum.mit.edu> | 2019-10-12 16:00:15 -0400 |
|---|---|---|
| committer | Ilia Mirkin <imirkin@alum.mit.edu> | 2019-10-12 20:45:34 -0400 |
| commit | 856572319fadeeadf58d782ab6f3f2d230822d67 (patch) | |
| tree | c60961a34d88fa1efccca307ccde8467fe1b3563 | |
| parent | a5f04582cecb1a649bb46b8af9f2889247788d00 (diff) | |
| download | xorg-driver-xf86-video-nouveau-856572319fadeeadf58d782ab6f3f2d230822d67.tar.gz | |
nv4/exa: tiling is unsupported pre-nv10, reduce alignment requirements
Commit 8c8f15c9d3 added increased pitch alignment requirements to handle
nv10-nv40 tiling (which must have a small number * PoT pitch). While
NV4/NV5 do have tiling, this was never supported in nouveau.
This change enables 1920x1200 resolutions since the maximum surface
pitch has to be strictly less than 8192. The current logic will align
1920*4 up to 8192 unnecessarily.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Marcin Kościelnicki <koriakin@0x04.net>
Cc: Francisco Jerez <currojerez@riseup.net>
| -rw-r--r-- | src/nouveau_dri2.c | 5 | ||||
| -rw-r--r-- | src/nv_driver.c | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/nouveau_dri2.c b/src/nouveau_dri2.c index 3d53785..ce0a573 100644 --- a/src/nouveau_dri2.c +++ b/src/nouveau_dri2.c @@ -62,7 +62,10 @@ nouveau_dri2_create_buffer2(ScreenPtr pScreen, DrawablePtr pDraw, unsigned int a ppix->refcnt++; } else { int bpp; - unsigned int usage_hint = NOUVEAU_CREATE_PIXMAP_TILED; + unsigned int usage_hint = 0; + + if (pNv->Architecture >= NV_ARCH_10) + usage_hint |= NOUVEAU_CREATE_PIXMAP_TILED; /* 'format' is just depth (or 0, or maybe it depends on the caller) */ bpp = round_up_pow2(format ? format : pDraw->depth); diff --git a/src/nv_driver.c b/src/nv_driver.c index 42eb9db..a63674c 100644 --- a/src/nv_driver.c +++ b/src/nv_driver.c @@ -1082,7 +1082,8 @@ NVPreInit(ScrnInfoPtr pScrn, int flags) pNv->wfb_enabled = xf86ReturnOptValBool( pNv->Options, OPTION_WFB, FALSE); - pNv->tiled_scanout = TRUE; + if (pNv->Architecture >= NV_ARCH_10) + pNv->tiled_scanout = TRUE; } pNv->ce_enabled = |