Check in generated files from the Python script added in [1937].

While I prefer not to have generated files in the source repository,
do this for now in the interest of sanity on the Windows side (to allow
building directly from a SVN checkout).

An alternative might be to require Python on Windows when building from
SVN.  If at some point we decide to go that route, it will be easy enough
to remove these files and add the necessary bits to Mkfiles/vc and
Mkfiles/vc8.

svn path=/trunk/yasm/; revision=1938

3 files changed, 3144 insertions, 0 deletions

diff --git a/x86insn_gas.gperf b/x86insn_gas.gperf
new file mode 100644
index 00000000..84e65247
--- /dev/null
+++ b/x86insn_gas.gperf
@@ -0,0 +1,1272 @@
+%ignore-case
+%language=ANSI-C
+%compare-strncmp
+%readonly-tables
+%enum
+%struct-type
+%define hash-function-name insnprefix_gas_hash
+%define lookup-function-name insnprefix_gas_find
+struct insnprefix_parse_data;
+%%
+aaa,	onebyte_insn,	(0x000037UL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+aad,	aadm_insn,	(0x01UL<<8)|NELEMS(aadm_insn),	CPU_Not64,	NONE
+aam,	aadm_insn,	(0x00UL<<8)|NELEMS(aadm_insn),	CPU_Not64,	NONE
+aas,	onebyte_insn,	(0x00003FUL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+adc,	arith_insn,	(0x0210UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+adcb,	arith_insn,	(0x0210UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_B
+adcl,	arith_insn,	(0x0210UL<<8)|NELEMS(arith_insn),	CPU_386,	SUF_L
+adcq,	arith_insn,	(0x0210UL<<8)|NELEMS(arith_insn),	CPU_64,	SUF_Q
+adcw,	arith_insn,	(0x0210UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_W
+add,	arith_insn,	(0x0000UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+addb,	arith_insn,	(0x0000UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_B
+addl,	arith_insn,	(0x0000UL<<8)|NELEMS(arith_insn),	CPU_386,	SUF_L
+addq,	arith_insn,	(0x0000UL<<8)|NELEMS(arith_insn),	CPU_64,	SUF_Q
+addw,	arith_insn,	(0x0000UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_W
+addpd,	ssess_insn,	(0x6658UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+addps,	sseps_insn,	(0x58UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+addr16,	NULL,	X86_ADDRSIZE,	0x10,	NONE
+addr32,	NULL,	X86_ADDRSIZE,	0x20,	NONE
+addr64,	NULL,	X86_ADDRSIZE,	0x40,	NONE
+addsd,	ssess_insn,	(0xF258UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+addss,	ssess_insn,	(0xF358UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+addsubpd,	ssess_insn,	(0x66D0UL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+addsubps,	ssess_insn,	(0xF2D0UL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+adword,	NULL,	X86_ADDRSIZE,	0x20,	NONE
+and,	arith_insn,	(0x0420UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+andb,	arith_insn,	(0x0420UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_B
+andl,	arith_insn,	(0x0420UL<<8)|NELEMS(arith_insn),	CPU_386,	SUF_L
+andq,	arith_insn,	(0x0420UL<<8)|NELEMS(arith_insn),	CPU_64,	SUF_Q
+andw,	arith_insn,	(0x0420UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_W
+andnpd,	ssess_insn,	(0x6655UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+andnps,	sseps_insn,	(0x55UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+andpd,	ssess_insn,	(0x6654UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+andps,	sseps_insn,	(0x54UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+aqword,	NULL,	X86_ADDRSIZE,	0x40,	NONE
+arpl,	arpl_insn,	(0UL<<8)|NELEMS(arpl_insn),	CPU_286|CPU_Not64|CPU_Prot,	NONE
+arplw,	arpl_insn,	(0UL<<8)|NELEMS(arpl_insn),	CPU_286|CPU_Not64|CPU_Prot,	SUF_W
+aword,	NULL,	X86_ADDRSIZE,	0x10,	NONE
+blendpd,	sse4imm_insn,	(0x0DUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+blendps,	sse4imm_insn,	(0x0CUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+blendvpd,	sse4xmm0_insn,	(0x15UL<<8)|NELEMS(sse4xmm0_insn),	CPU_SSE41,	NONE
+blendvps,	sse4xmm0_insn,	(0x14UL<<8)|NELEMS(sse4xmm0_insn),	CPU_SSE41,	NONE
+bound,	bound_insn,	(0UL<<8)|NELEMS(bound_insn),	CPU_186|CPU_Not64,	NONE
+boundl,	bound_insn,	(0UL<<8)|NELEMS(bound_insn),	CPU_386|CPU_Not64,	SUF_L
+boundw,	bound_insn,	(0UL<<8)|NELEMS(bound_insn),	CPU_186|CPU_Not64,	SUF_W
+bsf,	bsfr_insn,	(0xBCUL<<8)|NELEMS(bsfr_insn),	CPU_386,	NONE
+bsfl,	bsfr_insn,	(0xBCUL<<8)|NELEMS(bsfr_insn),	CPU_386,	SUF_L
+bsfq,	bsfr_insn,	(0xBCUL<<8)|NELEMS(bsfr_insn),	CPU_386|CPU_64,	SUF_Q
+bsfw,	bsfr_insn,	(0xBCUL<<8)|NELEMS(bsfr_insn),	CPU_386,	SUF_W
+bsr,	bsfr_insn,	(0xBDUL<<8)|NELEMS(bsfr_insn),	CPU_386,	NONE
+bsrl,	bsfr_insn,	(0xBDUL<<8)|NELEMS(bsfr_insn),	CPU_386,	SUF_L
+bsrq,	bsfr_insn,	(0xBDUL<<8)|NELEMS(bsfr_insn),	CPU_386|CPU_64,	SUF_Q
+bsrw,	bsfr_insn,	(0xBDUL<<8)|NELEMS(bsfr_insn),	CPU_386,	SUF_W
+bswap,	bswap_insn,	(0UL<<8)|NELEMS(bswap_insn),	CPU_486,	NONE
+bswapl,	bswap_insn,	(0UL<<8)|NELEMS(bswap_insn),	CPU_486,	SUF_L
+bswapq,	bswap_insn,	(0UL<<8)|NELEMS(bswap_insn),	CPU_64,	SUF_Q
+bt,	bittest_insn,	(0x04A3UL<<8)|NELEMS(bittest_insn),	CPU_386,	NONE
+btl,	bittest_insn,	(0x04A3UL<<8)|NELEMS(bittest_insn),	CPU_386,	SUF_L
+btq,	bittest_insn,	(0x04A3UL<<8)|NELEMS(bittest_insn),	CPU_386|CPU_64,	SUF_Q
+btw,	bittest_insn,	(0x04A3UL<<8)|NELEMS(bittest_insn),	CPU_386,	SUF_W
+btc,	bittest_insn,	(0x07BBUL<<8)|NELEMS(bittest_insn),	CPU_386,	NONE
+btcl,	bittest_insn,	(0x07BBUL<<8)|NELEMS(bittest_insn),	CPU_386,	SUF_L
+btcq,	bittest_insn,	(0x07BBUL<<8)|NELEMS(bittest_insn),	CPU_386|CPU_64,	SUF_Q
+btcw,	bittest_insn,	(0x07BBUL<<8)|NELEMS(bittest_insn),	CPU_386,	SUF_W
+btr,	bittest_insn,	(0x06B3UL<<8)|NELEMS(bittest_insn),	CPU_386,	NONE
+btrl,	bittest_insn,	(0x06B3UL<<8)|NELEMS(bittest_insn),	CPU_386,	SUF_L
+btrq,	bittest_insn,	(0x06B3UL<<8)|NELEMS(bittest_insn),	CPU_386|CPU_64,	SUF_Q
+btrw,	bittest_insn,	(0x06B3UL<<8)|NELEMS(bittest_insn),	CPU_386,	SUF_W
+bts,	bittest_insn,	(0x05ABUL<<8)|NELEMS(bittest_insn),	CPU_386,	NONE
+btsl,	bittest_insn,	(0x05ABUL<<8)|NELEMS(bittest_insn),	CPU_386,	SUF_L
+btsq,	bittest_insn,	(0x05ABUL<<8)|NELEMS(bittest_insn),	CPU_386|CPU_64,	SUF_Q
+btsw,	bittest_insn,	(0x05ABUL<<8)|NELEMS(bittest_insn),	CPU_386,	SUF_W
+call,	call_insn,	(0UL<<8)|NELEMS(call_insn),	CPU_Any,	NONE
+calll,	call_insn,	(0UL<<8)|NELEMS(call_insn),	CPU_Not64,	NONE
+callq,	call_insn,	(0UL<<8)|NELEMS(call_insn),	CPU_64,	NONE
+cbtw,	onebyte_insn,	(0x001098UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cbw,	onebyte_insn,	(0x001098UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cdq,	onebyte_insn,	(0x002099UL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+cdqe,	onebyte_insn,	(0x004098UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+clc,	onebyte_insn,	(0x0000F8UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cld,	onebyte_insn,	(0x0000FCUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+clflush,	clflush_insn,	(0UL<<8)|NELEMS(clflush_insn),	CPU_P3,	NONE
+clgi,	threebyte_insn,	(0x0F01DDUL<<8)|NELEMS(threebyte_insn),	CPU_SVM,	NONE
+cli,	onebyte_insn,	(0x0000FAUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cltd,	onebyte_insn,	(0x002099UL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+cltq,	onebyte_insn,	(0x004098UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+clts,	twobyte_insn,	(0x0F06UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_Priv,	NONE
+cmc,	onebyte_insn,	(0x0000F5UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cmova,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmoval,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovaq,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovaw,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovae,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovael,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovaeq,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovaew,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovb,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovbl,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovbq,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovbw,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovbe,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovbel,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovbeq,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovbew,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovc,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovcl,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovcq,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovcw,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmove,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovel,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmoveq,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovew,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovg,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovgl,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovgq,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovgw,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovge,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovgel,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovgeq,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovgew,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovl,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovll,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovlq,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovlw,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovle,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovlel,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovleq,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovlew,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovna,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnal,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnaq,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnaw,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovnae,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnael,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnaeq,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnaew,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovnb,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnbl,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnbq,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnbw,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovnbe,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnbel,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnbeq,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnbew,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovnc,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovncl,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovncq,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovncw,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovne,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnel,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovneq,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnew,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovng,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovngl,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovngq,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovngw,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovnge,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovngel,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovngeq,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovngew,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovnl,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnll,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnlq,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnlw,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovnle,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnlel,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnleq,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnlew,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovno,	cmovcc_insn,	(0x01UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnol,	cmovcc_insn,	(0x01UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnoq,	cmovcc_insn,	(0x01UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnow,	cmovcc_insn,	(0x01UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovnp,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnpl,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnpq,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnpw,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovns,	cmovcc_insn,	(0x09UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnsl,	cmovcc_insn,	(0x09UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnsq,	cmovcc_insn,	(0x09UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnsw,	cmovcc_insn,	(0x09UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovnz,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnzl,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovnzq,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovnzw,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovo,	cmovcc_insn,	(0x00UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovol,	cmovcc_insn,	(0x00UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovoq,	cmovcc_insn,	(0x00UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovow,	cmovcc_insn,	(0x00UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovp,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovpl,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovpq,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovpw,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovpe,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovpel,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovpeq,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovpew,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovpo,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovpol,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovpoq,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovpow,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovs,	cmovcc_insn,	(0x08UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovsl,	cmovcc_insn,	(0x08UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovsq,	cmovcc_insn,	(0x08UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovsw,	cmovcc_insn,	(0x08UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmovz,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovzl,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_L
+cmovzq,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_64|CPU_686,	SUF_Q
+cmovzw,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	SUF_W
+cmp,	arith_insn,	(0x0738UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+cmpb,	arith_insn,	(0x0738UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_B
+cmpl,	arith_insn,	(0x0738UL<<8)|NELEMS(arith_insn),	CPU_386,	SUF_L
+cmpq,	arith_insn,	(0x0738UL<<8)|NELEMS(arith_insn),	CPU_64,	SUF_Q
+cmpw,	arith_insn,	(0x0738UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_W
+cmpeqpd,	ssecmpss_insn,	(0x0066UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpeqps,	ssecmpps_insn,	(0x00UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpeqsd,	ssecmpss_insn,	(0x00F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpeqss,	ssecmpss_insn,	(0x00F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmplepd,	ssecmpss_insn,	(0x0266UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpleps,	ssecmpps_insn,	(0x02UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmplesd,	ssecmpss_insn,	(0x02F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpless,	ssecmpss_insn,	(0x02F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpltpd,	ssecmpss_insn,	(0x0166UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpltps,	ssecmpps_insn,	(0x01UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpltsd,	ssecmpss_insn,	(0x01F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpltss,	ssecmpss_insn,	(0x01F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpneqpd,	ssecmpss_insn,	(0x0466UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpneqps,	ssecmpps_insn,	(0x04UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpneqsd,	ssecmpss_insn,	(0x04F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpneqss,	ssecmpss_insn,	(0x04F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpnlepd,	ssecmpss_insn,	(0x0666UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpnleps,	ssecmpps_insn,	(0x06UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpnlesd,	ssecmpss_insn,	(0x06F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpnless,	ssecmpss_insn,	(0x06F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpnltpd,	ssecmpss_insn,	(0x0566UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpnltps,	ssecmpps_insn,	(0x05UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpnltsd,	ssecmpss_insn,	(0x05F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpnltss,	ssecmpss_insn,	(0x05F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpordpd,	ssecmpss_insn,	(0x0766UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpordps,	ssecmpps_insn,	(0x07UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpordsd,	ssecmpss_insn,	(0x07F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpordss,	ssecmpss_insn,	(0x07F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmppd,	ssessimm_insn,	(0x66C2UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+cmpps,	ssepsimm_insn,	(0xC2UL<<8)|NELEMS(ssepsimm_insn),	CPU_SSE,	NONE
+cmpsb,	onebyte_insn,	(0x0000A6UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cmpsd,	cmpsd_insn,	(0UL<<8)|NELEMS(cmpsd_insn),	CPU_Any,	NONE
+cmpsl,	onebyte_insn,	(0x0020A7UL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+cmpsq,	onebyte_insn,	(0x0040A7UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+cmpss,	ssessimm_insn,	(0xF3C2UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE,	NONE
+cmpsw,	onebyte_insn,	(0x0010A7UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cmpunordpd,	ssecmpss_insn,	(0x0366UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpunordps,	ssecmpps_insn,	(0x03UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpunordsd,	ssecmpss_insn,	(0x03F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpunordss,	ssecmpss_insn,	(0x03F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpxchg,	cmpxchgxadd_insn,	(0xB0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	NONE
+cmpxchg16b,	cmpxchg16b_insn,	(0UL<<8)|NELEMS(cmpxchg16b_insn),	CPU_64,	NONE
+cmpxchg8b,	cmpxchg8b_insn,	(0UL<<8)|NELEMS(cmpxchg8b_insn),	CPU_586,	NONE
+cmpxchg8bq,	cmpxchg8b_insn,	(0UL<<8)|NELEMS(cmpxchg8b_insn),	CPU_586,	SUF_Q
+cmpxchgb,	cmpxchgxadd_insn,	(0xB0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	SUF_B
+cmpxchgl,	cmpxchgxadd_insn,	(0xB0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	SUF_L
+cmpxchgq,	cmpxchgxadd_insn,	(0xB0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486|CPU_64,	SUF_Q
+cmpxchgw,	cmpxchgxadd_insn,	(0xB0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	SUF_W
+comisd,	ssess_insn,	(0x662FUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+comiss,	sseps_insn,	(0x2FUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+cpuid,	twobyte_insn,	(0x0FA2UL<<8)|NELEMS(twobyte_insn),	CPU_486,	NONE
+cqo,	onebyte_insn,	(0x004099UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+cqto,	onebyte_insn,	(0x004099UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+crc32,	crc32_insn,	(0UL<<8)|NELEMS(crc32_insn),	CPU_386|CPU_SSE42,	NONE
+crc32b,	crc32_insn,	(0UL<<8)|NELEMS(crc32_insn),	CPU_386|CPU_SSE42,	SUF_B
+crc32l,	crc32_insn,	(0UL<<8)|NELEMS(crc32_insn),	CPU_386|CPU_SSE42,	SUF_L
+crc32q,	crc32_insn,	(0UL<<8)|NELEMS(crc32_insn),	CPU_64|CPU_SSE42,	SUF_Q
+crc32w,	crc32_insn,	(0UL<<8)|NELEMS(crc32_insn),	CPU_386|CPU_SSE42,	SUF_W
+cvtdq2pd,	cvt_xmm_xmm64_ss_insn,	(0xF3E6UL<<8)|NELEMS(cvt_xmm_xmm64_ss_insn),	CPU_SSE2,	NONE
+cvtdq2ps,	sseps_insn,	(0x5BUL<<8)|NELEMS(sseps_insn),	CPU_SSE2,	NONE
+cvtpd2dq,	ssess_insn,	(0xF2E6UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvtpd2pi,	cvt_mm_xmm_insn,	(0x662DUL<<8)|NELEMS(cvt_mm_xmm_insn),	CPU_SSE2,	NONE
+cvtpd2ps,	ssess_insn,	(0x665AUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvtpi2pd,	cvt_xmm_mm_ss_insn,	(0x662AUL<<8)|NELEMS(cvt_xmm_mm_ss_insn),	CPU_SSE2,	NONE
+cvtpi2ps,	cvt_xmm_mm_ps_insn,	(0x2AUL<<8)|NELEMS(cvt_xmm_mm_ps_insn),	CPU_SSE,	NONE
+cvtps2dq,	ssess_insn,	(0x665BUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvtps2pd,	cvt_xmm_xmm64_ps_insn,	(0x5AUL<<8)|NELEMS(cvt_xmm_xmm64_ps_insn),	CPU_SSE2,	NONE
+cvtps2pi,	cvt_mm_xmm64_insn,	(0x2DUL<<8)|NELEMS(cvt_mm_xmm64_insn),	CPU_SSE,	NONE
+cvtsd2si,	cvt_rx_xmm64_insn,	(0xF22DUL<<8)|NELEMS(cvt_rx_xmm64_insn),	CPU_386|CPU_SSE2,	NONE
+cvtsd2sil,	cvt_rx_xmm64_insn,	(0xF22DUL<<8)|NELEMS(cvt_rx_xmm64_insn),	CPU_386|CPU_SSE2,	SUF_L
+cvtsd2siq,	cvt_rx_xmm64_insn,	(0xF22DUL<<8)|NELEMS(cvt_rx_xmm64_insn),	CPU_64|CPU_SSE2,	SUF_Q
+cvtsd2ss,	cvt_xmm_xmm64_ss_insn,	(0xF25AUL<<8)|NELEMS(cvt_xmm_xmm64_ss_insn),	CPU_SSE2,	NONE
+cvtsi2sd,	cvt_xmm_rmx_insn,	(0xF22AUL<<8)|NELEMS(cvt_xmm_rmx_insn),	CPU_SSE2,	NONE
+cvtsi2sdl,	cvt_xmm_rmx_insn,	(0xF22AUL<<8)|NELEMS(cvt_xmm_rmx_insn),	CPU_SSE2,	SUF_L
+cvtsi2sdq,	cvt_xmm_rmx_insn,	(0xF22AUL<<8)|NELEMS(cvt_xmm_rmx_insn),	CPU_SSE2,	SUF_Q
+cvtsi2ss,	cvt_xmm_rmx_insn,	(0xF32AUL<<8)|NELEMS(cvt_xmm_rmx_insn),	CPU_386|CPU_SSE,	NONE
+cvtsi2ssl,	cvt_xmm_rmx_insn,	(0xF32AUL<<8)|NELEMS(cvt_xmm_rmx_insn),	CPU_386|CPU_SSE,	SUF_L
+cvtsi2ssq,	cvt_xmm_rmx_insn,	(0xF32AUL<<8)|NELEMS(cvt_xmm_rmx_insn),	CPU_64|CPU_SSE,	SUF_Q
+cvtss2sd,	cvt_xmm_xmm32_insn,	(0xF35AUL<<8)|NELEMS(cvt_xmm_xmm32_insn),	CPU_SSE2,	NONE
+cvtss2si,	cvt_rx_xmm32_insn,	(0xF32DUL<<8)|NELEMS(cvt_rx_xmm32_insn),	CPU_386|CPU_SSE,	NONE
+cvtss2sil,	cvt_rx_xmm32_insn,	(0xF32DUL<<8)|NELEMS(cvt_rx_xmm32_insn),	CPU_386|CPU_SSE,	SUF_L
+cvtss2siq,	cvt_rx_xmm32_insn,	(0xF32DUL<<8)|NELEMS(cvt_rx_xmm32_insn),	CPU_64|CPU_SSE,	SUF_Q
+cvttpd2dq,	ssess_insn,	(0x66E6UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvttpd2pi,	cvt_mm_xmm_insn,	(0x662CUL<<8)|NELEMS(cvt_mm_xmm_insn),	CPU_SSE2,	NONE
+cvttps2dq,	ssess_insn,	(0xF35BUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvttps2pi,	cvt_mm_xmm64_insn,	(0x2CUL<<8)|NELEMS(cvt_mm_xmm64_insn),	CPU_SSE,	NONE
+cvttsd2si,	cvt_rx_xmm64_insn,	(0xF22CUL<<8)|NELEMS(cvt_rx_xmm64_insn),	CPU_SSE2,	NONE
+cvttsd2sil,	cvt_rx_xmm64_insn,	(0xF22CUL<<8)|NELEMS(cvt_rx_xmm64_insn),	CPU_SSE2,	SUF_L
+cvttsd2siq,	cvt_rx_xmm64_insn,	(0xF22CUL<<8)|NELEMS(cvt_rx_xmm64_insn),	CPU_SSE2,	SUF_Q
+cvttss2si,	cvt_rx_xmm32_insn,	(0xF32CUL<<8)|NELEMS(cvt_rx_xmm32_insn),	CPU_386|CPU_SSE,	NONE
+cvttss2sil,	cvt_rx_xmm32_insn,	(0xF32CUL<<8)|NELEMS(cvt_rx_xmm32_insn),	CPU_386|CPU_SSE,	SUF_L
+cvttss2siq,	cvt_rx_xmm32_insn,	(0xF32CUL<<8)|NELEMS(cvt_rx_xmm32_insn),	CPU_64|CPU_SSE,	SUF_Q
+cwd,	onebyte_insn,	(0x001099UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cwde,	onebyte_insn,	(0x002098UL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+cwtd,	onebyte_insn,	(0x001099UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cwtl,	onebyte_insn,	(0x002098UL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+daa,	onebyte_insn,	(0x000027UL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+das,	onebyte_insn,	(0x00002FUL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+data16,	NULL,	X86_OPERSIZE,	0x10,	NONE
+data32,	NULL,	X86_OPERSIZE,	0x20,	NONE
+data64,	NULL,	X86_OPERSIZE,	0x40,	NONE
+dec,	incdec_insn,	(0x0148UL<<8)|NELEMS(incdec_insn),	CPU_Any,	NONE
+decb,	incdec_insn,	(0x0148UL<<8)|NELEMS(incdec_insn),	CPU_Any,	SUF_B
+decl,	incdec_insn,	(0x0148UL<<8)|NELEMS(incdec_insn),	CPU_386,	SUF_L
+decq,	incdec_insn,	(0x0148UL<<8)|NELEMS(incdec_insn),	CPU_64,	SUF_Q
+decw,	incdec_insn,	(0x0148UL<<8)|NELEMS(incdec_insn),	CPU_Any,	SUF_W
+div,	div_insn,	(0x06UL<<8)|NELEMS(div_insn),	CPU_Any,	NONE
+divb,	div_insn,	(0x06UL<<8)|NELEMS(div_insn),	CPU_Any,	SUF_B
+divl,	div_insn,	(0x06UL<<8)|NELEMS(div_insn),	CPU_386,	SUF_L
+divq,	div_insn,	(0x06UL<<8)|NELEMS(div_insn),	CPU_64,	SUF_Q
+divw,	div_insn,	(0x06UL<<8)|NELEMS(div_insn),	CPU_Any,	SUF_W
+divpd,	ssess_insn,	(0x665EUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+divps,	sseps_insn,	(0x5EUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+divsd,	ssess_insn,	(0xF25EUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+divss,	ssess_insn,	(0xF35EUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+dppd,	sse4imm_insn,	(0x41UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+dpps,	sse4imm_insn,	(0x40UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+dword,	NULL,	X86_OPERSIZE,	0x20,	NONE
+emms,	twobyte_insn,	(0x0F77UL<<8)|NELEMS(twobyte_insn),	CPU_MMX,	NONE
+enter,	enter_insn,	(0UL<<8)|NELEMS(enter_insn),	CPU_186,	NONE
+enterl,	enter_insn,	(0UL<<8)|NELEMS(enter_insn),	CPU_186|CPU_Not64,	SUF_L
+enterq,	enter_insn,	(0UL<<8)|NELEMS(enter_insn),	CPU_186|CPU_64,	SUF_Q
+enterw,	enter_insn,	(0UL<<8)|NELEMS(enter_insn),	CPU_186,	SUF_W
+extractps,	extractps_insn,	(0UL<<8)|NELEMS(extractps_insn),	CPU_386|CPU_SSE41,	NONE
+extrq,	extrq_insn,	(0UL<<8)|NELEMS(extrq_insn),	CPU_SSE41,	NONE
+f2xm1,	twobyte_insn,	(0xD9F0UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fabs,	twobyte_insn,	(0xD9E1UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fadd,	farith_insn,	(0x00C0C0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+faddl,	farith_insn,	(0x00C0C0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_L
+fadds,	farith_insn,	(0x00C0C0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_S
+faddp,	farithp_insn,	(0xC0UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+fbld,	fbldstp_insn,	(0x04UL<<8)|NELEMS(fbldstp_insn),	CPU_FPU,	NONE
+fbstp,	fbldstp_insn,	(0x06UL<<8)|NELEMS(fbldstp_insn),	CPU_FPU,	NONE
+fchs,	twobyte_insn,	(0xD9E0UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fclex,	threebyte_insn,	(0x9BDBE2UL<<8)|NELEMS(threebyte_insn),	CPU_FPU,	NONE
+fcmovb,	fcmovcc_insn,	(0xDAC0UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovbe,	fcmovcc_insn,	(0xDAD0UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmove,	fcmovcc_insn,	(0xDAC8UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovnb,	fcmovcc_insn,	(0xDBC0UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovnbe,	fcmovcc_insn,	(0xDBD0UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovne,	fcmovcc_insn,	(0xDBC8UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovnu,	fcmovcc_insn,	(0xDBD8UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovu,	fcmovcc_insn,	(0xDAD8UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcom,	fcom_insn,	(0x02D0UL<<8)|NELEMS(fcom_insn),	CPU_FPU,	NONE
+fcoml,	fcom_insn,	(0x02D0UL<<8)|NELEMS(fcom_insn),	CPU_FPU,	SUF_L
+fcoms,	fcom_insn,	(0x02D0UL<<8)|NELEMS(fcom_insn),	CPU_FPU,	SUF_S
+fcomi,	fcom2_insn,	(0xDBF0UL<<8)|NELEMS(fcom2_insn),	CPU_686|CPU_FPU,	NONE
+fcomip,	fcom2_insn,	(0xDFF0UL<<8)|NELEMS(fcom2_insn),	CPU_686|CPU_FPU,	NONE
+fcomp,	fcom_insn,	(0x03D8UL<<8)|NELEMS(fcom_insn),	CPU_FPU,	NONE
+fcompl,	fcom_insn,	(0x03D8UL<<8)|NELEMS(fcom_insn),	CPU_FPU,	SUF_L
+fcomps,	fcom_insn,	(0x03D8UL<<8)|NELEMS(fcom_insn),	CPU_FPU,	SUF_S
+fcompp,	twobyte_insn,	(0xDED9UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fcos,	twobyte_insn,	(0xD9FFUL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fdecstp,	twobyte_insn,	(0xD9F6UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fdiv,	farith_insn,	(0x06F0F8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fdivl,	farith_insn,	(0x06F0F8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_L
+fdivs,	farith_insn,	(0x06F0F8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_S
+fdivp,	farithp_insn,	(0xF0UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+fdivr,	farith_insn,	(0x07F8F0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fdivrl,	farith_insn,	(0x07F8F0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_L
+fdivrs,	farith_insn,	(0x07F8F0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_S
+fdivrp,	farithp_insn,	(0xF8UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+femms,	twobyte_insn,	(0x0F0EUL<<8)|NELEMS(twobyte_insn),	CPU_3DNow,	NONE
+ffree,	ffree_insn,	(0xDDUL<<8)|NELEMS(ffree_insn),	CPU_FPU,	NONE
+ffreep,	ffree_insn,	(0xDFUL<<8)|NELEMS(ffree_insn),	CPU_686|CPU_FPU|CPU_Undoc,	NONE
+fiadd,	fiarith_insn,	(0x00DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fiaddl,	fiarith_insn,	(0x00DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_L
+fiadds,	fiarith_insn,	(0x00DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_S
+ficom,	fiarith_insn,	(0x02DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+ficoml,	fiarith_insn,	(0x02DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_L
+ficoms,	fiarith_insn,	(0x02DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_S
+ficomp,	fiarith_insn,	(0x03DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+ficompl,	fiarith_insn,	(0x03DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_L
+ficomps,	fiarith_insn,	(0x03DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_S
+fidiv,	fiarith_insn,	(0x06DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fidivl,	fiarith_insn,	(0x06DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_L
+fidivs,	fiarith_insn,	(0x06DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_S
+fidivr,	fiarith_insn,	(0x07DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fidivrl,	fiarith_insn,	(0x07DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_L
+fidivrs,	fiarith_insn,	(0x07DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_S
+fild,	fildstp_insn,	(0x050200UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	NONE
+fildl,	fildstp_insn,	(0x050200UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	SUF_L
+fildq,	fildstp_insn,	(0x050200UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	SUF_Q
+filds,	fildstp_insn,	(0x050200UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	SUF_S
+fildll,	fbldstp_insn,	(0x05UL<<8)|NELEMS(fbldstp_insn),	CPU_FPU,	NONE
+fimul,	fiarith_insn,	(0x01DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fimull,	fiarith_insn,	(0x01DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_L
+fimuls,	fiarith_insn,	(0x01DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_S
+fincstp,	twobyte_insn,	(0xD9F7UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+finit,	threebyte_insn,	(0x9BDBE3UL<<8)|NELEMS(threebyte_insn),	CPU_FPU,	NONE
+fist,	fiarith_insn,	(0x02DBUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fistl,	fiarith_insn,	(0x02DBUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_L
+fists,	fiarith_insn,	(0x02DBUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_S
+fistp,	fildstp_insn,	(0x070203UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	NONE
+fistpl,	fildstp_insn,	(0x070203UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	SUF_L
+fistpq,	fildstp_insn,	(0x070203UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	SUF_Q
+fistps,	fildstp_insn,	(0x070203UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	SUF_S
+fistpll,	fbldstp_insn,	(0x07UL<<8)|NELEMS(fbldstp_insn),	CPU_FPU,	NONE
+fisttp,	fildstp_insn,	(0x010001UL<<8)|NELEMS(fildstp_insn),	CPU_SSE3,	NONE
+fisttpl,	fildstp_insn,	(0x010001UL<<8)|NELEMS(fildstp_insn),	CPU_SSE3,	SUF_L
+fisttpq,	fildstp_insn,	(0x010001UL<<8)|NELEMS(fildstp_insn),	CPU_SSE3,	SUF_Q
+fisttps,	fildstp_insn,	(0x010001UL<<8)|NELEMS(fildstp_insn),	CPU_SSE3,	SUF_S
+fisttpll,	fildstp_insn,	(0x000007UL<<8)|NELEMS(fildstp_insn),	CPU_SSE3,	SUF_Q
+fisub,	fiarith_insn,	(0x04DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fisubl,	fiarith_insn,	(0x04DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_L
+fisubs,	fiarith_insn,	(0x04DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_S
+fisubr,	fiarith_insn,	(0x05DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fisubrl,	fiarith_insn,	(0x05DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_L
+fisubrs,	fiarith_insn,	(0x05DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	SUF_S
+fld,	fld_insn,	(0UL<<8)|NELEMS(fld_insn),	CPU_FPU,	NONE
+fld1,	twobyte_insn,	(0xD9E8UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldl,	fld_insn,	(0UL<<8)|NELEMS(fld_insn),	CPU_FPU,	SUF_L
+flds,	fld_insn,	(0UL<<8)|NELEMS(fld_insn),	CPU_FPU,	SUF_S
+fldcw,	fldnstcw_insn,	(0x05UL<<8)|NELEMS(fldnstcw_insn),	CPU_FPU,	NONE
+fldcww,	fldnstcw_insn,	(0x05UL<<8)|NELEMS(fldnstcw_insn),	CPU_FPU,	SUF_W
+fldenv,	onebytemem_insn,	(0x04D9UL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	NONE
+fldenvl,	onebytemem_insn,	(0x04D9UL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	SUF_L
+fldenvs,	onebytemem_insn,	(0x04D9UL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	SUF_S
+fldl2e,	twobyte_insn,	(0xD9EAUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldl2t,	twobyte_insn,	(0xD9E9UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldlg2,	twobyte_insn,	(0xD9ECUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldln2,	twobyte_insn,	(0xD9EDUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldpi,	twobyte_insn,	(0xD9EBUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldt,	fldstpt_insn,	(0x05UL<<8)|NELEMS(fldstpt_insn),	CPU_FPU,	WEAK
+fldz,	twobyte_insn,	(0xD9EEUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fmul,	farith_insn,	(0x01C8C8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fmull,	farith_insn,	(0x01C8C8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_L
+fmuls,	farith_insn,	(0x01C8C8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_S
+fmulp,	farithp_insn,	(0xC8UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+fnclex,	twobyte_insn,	(0xDBE2UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fninit,	twobyte_insn,	(0xDBE3UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fnop,	twobyte_insn,	(0xD9D0UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fnsave,	onebytemem_insn,	(0x06DDUL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	NONE
+fnsavel,	onebytemem_insn,	(0x06DDUL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	SUF_L
+fnsaves,	onebytemem_insn,	(0x06DDUL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	SUF_S
+fnstcw,	fldnstcw_insn,	(0x07UL<<8)|NELEMS(fldnstcw_insn),	CPU_FPU,	NONE
+fnstcww,	fldnstcw_insn,	(0x07UL<<8)|NELEMS(fldnstcw_insn),	CPU_FPU,	SUF_W
+fnstenv,	onebytemem_insn,	(0x06D9UL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	NONE
+fnstenvl,	onebytemem_insn,	(0x06D9UL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	SUF_L
+fnstenvs,	onebytemem_insn,	(0x06D9UL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	SUF_S
+fnstsw,	fnstsw_insn,	(0UL<<8)|NELEMS(fnstsw_insn),	CPU_FPU,	NONE
+fnstsww,	fnstsw_insn,	(0UL<<8)|NELEMS(fnstsw_insn),	CPU_FPU,	SUF_W
+fpatan,	twobyte_insn,	(0xD9F3UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fprem,	twobyte_insn,	(0xD9F8UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fprem1,	twobyte_insn,	(0xD9F5UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fptan,	twobyte_insn,	(0xD9F2UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+frndint,	twobyte_insn,	(0xD9FCUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+frstor,	onebytemem_insn,	(0x04DDUL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	NONE
+frstorl,	onebytemem_insn,	(0x04DDUL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	SUF_L
+frstors,	onebytemem_insn,	(0x04DDUL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	SUF_S
+fsave,	twobytemem_insn,	(0x069BDDUL<<8)|NELEMS(twobytemem_insn),	CPU_FPU,	NONE
+fsavel,	twobytemem_insn,	(0x069BDDUL<<8)|NELEMS(twobytemem_insn),	CPU_FPU,	SUF_L
+fsaves,	twobytemem_insn,	(0x069BDDUL<<8)|NELEMS(twobytemem_insn),	CPU_FPU,	SUF_S
+fscale,	twobyte_insn,	(0xD9FDUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fsetpm,	twobyte_insn,	(0xDBE4UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU|CPU_Obs,	NONE
+fsin,	twobyte_insn,	(0xD9FEUL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fsincos,	twobyte_insn,	(0xD9FBUL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fsqrt,	twobyte_insn,	(0xD9FAUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fst,	fst_insn,	(0UL<<8)|NELEMS(fst_insn),	CPU_FPU,	NONE
+fstl,	fst_insn,	(0UL<<8)|NELEMS(fst_insn),	CPU_FPU,	SUF_L
+fsts,	fst_insn,	(0UL<<8)|NELEMS(fst_insn),	CPU_FPU,	SUF_S
+fstcw,	fstcw_insn,	(0UL<<8)|NELEMS(fstcw_insn),	CPU_FPU,	NONE
+fstcww,	fstcw_insn,	(0UL<<8)|NELEMS(fstcw_insn),	CPU_FPU,	SUF_W
+fstenv,	twobytemem_insn,	(0x069BD9UL<<8)|NELEMS(twobytemem_insn),	CPU_FPU,	NONE
+fstenvl,	twobytemem_insn,	(0x069BD9UL<<8)|NELEMS(twobytemem_insn),	CPU_FPU,	SUF_L
+fstenvs,	twobytemem_insn,	(0x069BD9UL<<8)|NELEMS(twobytemem_insn),	CPU_FPU,	SUF_S
+fstp,	fstp_insn,	(0UL<<8)|NELEMS(fstp_insn),	CPU_FPU,	NONE
+fstpl,	fstp_insn,	(0UL<<8)|NELEMS(fstp_insn),	CPU_FPU,	SUF_L
+fstps,	fstp_insn,	(0UL<<8)|NELEMS(fstp_insn),	CPU_FPU,	SUF_S
+fstpt,	fldstpt_insn,	(0x07UL<<8)|NELEMS(fldstpt_insn),	CPU_FPU,	WEAK
+fstsw,	fstsw_insn,	(0UL<<8)|NELEMS(fstsw_insn),	CPU_FPU,	NONE
+fstsww,	fstsw_insn,	(0UL<<8)|NELEMS(fstsw_insn),	CPU_FPU,	SUF_W
+fsub,	farith_insn,	(0x04E0E8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fsubl,	farith_insn,	(0x04E0E8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_L
+fsubs,	farith_insn,	(0x04E0E8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_S
+fsubp,	farithp_insn,	(0xE0UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+fsubr,	farith_insn,	(0x05E8E0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fsubrl,	farith_insn,	(0x05E8E0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_L
+fsubrs,	farith_insn,	(0x05E8E0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	SUF_S
+fsubrp,	farithp_insn,	(0xE8UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+ftst,	twobyte_insn,	(0xD9E4UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fucom,	fcom2_insn,	(0xDDE0UL<<8)|NELEMS(fcom2_insn),	CPU_286|CPU_FPU,	NONE
+fucomi,	fcom2_insn,	(0xDBE8UL<<8)|NELEMS(fcom2_insn),	CPU_686|CPU_FPU,	NONE
+fucomip,	fcom2_insn,	(0xDFE8UL<<8)|NELEMS(fcom2_insn),	CPU_686|CPU_FPU,	NONE
+fucomp,	fcom2_insn,	(0xDDE8UL<<8)|NELEMS(fcom2_insn),	CPU_286|CPU_FPU,	NONE
+fucompp,	twobyte_insn,	(0xDAE9UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fwait,	onebyte_insn,	(0x00009BUL<<8)|NELEMS(onebyte_insn),	CPU_FPU,	NONE
+fxam,	twobyte_insn,	(0xD9E5UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fxch,	fxch_insn,	(0UL<<8)|NELEMS(fxch_insn),	CPU_FPU,	NONE
+fxrstor,	twobytemem_insn,	(0x010FAEUL<<8)|NELEMS(twobytemem_insn),	CPU_686|CPU_FPU,	NONE
+fxrstorq,	twobytemem_insn,	(0x010FAEUL<<8)|NELEMS(twobytemem_insn),	CPU_686|CPU_FPU,	SUF_Q
+fxsave,	twobytemem_insn,	(0x000FAEUL<<8)|NELEMS(twobytemem_insn),	CPU_686|CPU_FPU,	NONE
+fxsaveq,	twobytemem_insn,	(0x000FAEUL<<8)|NELEMS(twobytemem_insn),	CPU_686|CPU_FPU,	SUF_Q
+fxtract,	twobyte_insn,	(0xD9F4UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fyl2x,	twobyte_insn,	(0xD9F1UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fyl2xp1,	twobyte_insn,	(0xD9F9UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+haddpd,	ssess_insn,	(0x667CUL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+haddps,	ssess_insn,	(0xF27CUL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+hlt,	onebyte_insn,	(0x0000F4UL<<8)|NELEMS(onebyte_insn),	CPU_Priv,	NONE
+hnt,	NULL,	X86_SEGREG,	0x2E,	NONE
+hsubpd,	ssess_insn,	(0x667DUL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+hsubps,	ssess_insn,	(0xF27DUL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+ht,	NULL,	X86_SEGREG,	0x3E,	NONE
+ibts,	ibts_insn,	(0UL<<8)|NELEMS(ibts_insn),	CPU_386|CPU_Obs|CPU_Undoc,	NONE
+idiv,	div_insn,	(0x07UL<<8)|NELEMS(div_insn),	CPU_Any,	NONE
+idivb,	div_insn,	(0x07UL<<8)|NELEMS(div_insn),	CPU_Any,	SUF_B
+idivl,	div_insn,	(0x07UL<<8)|NELEMS(div_insn),	CPU_386,	SUF_L
+idivq,	div_insn,	(0x07UL<<8)|NELEMS(div_insn),	CPU_64,	SUF_Q
+idivw,	div_insn,	(0x07UL<<8)|NELEMS(div_insn),	CPU_Any,	SUF_W
+imul,	imul_insn,	(0UL<<8)|NELEMS(imul_insn),	CPU_Any,	NONE
+imulb,	imul_insn,	(0UL<<8)|NELEMS(imul_insn),	CPU_Any,	SUF_B
+imull,	imul_insn,	(0UL<<8)|NELEMS(imul_insn),	CPU_386,	SUF_L
+imulq,	imul_insn,	(0UL<<8)|NELEMS(imul_insn),	CPU_64,	SUF_Q
+imulw,	imul_insn,	(0UL<<8)|NELEMS(imul_insn),	CPU_Any,	SUF_W
+in,	in_insn,	(0UL<<8)|NELEMS(in_insn),	CPU_Any,	NONE
+inb,	in_insn,	(0UL<<8)|NELEMS(in_insn),	CPU_Any,	SUF_B
+inl,	in_insn,	(0UL<<8)|NELEMS(in_insn),	CPU_386,	SUF_L
+inw,	in_insn,	(0UL<<8)|NELEMS(in_insn),	CPU_Any,	SUF_W
+inc,	incdec_insn,	(0x0040UL<<8)|NELEMS(incdec_insn),	CPU_Any,	NONE
+incb,	incdec_insn,	(0x0040UL<<8)|NELEMS(incdec_insn),	CPU_Any,	SUF_B
+incl,	incdec_insn,	(0x0040UL<<8)|NELEMS(incdec_insn),	CPU_386,	SUF_L
+incq,	incdec_insn,	(0x0040UL<<8)|NELEMS(incdec_insn),	CPU_64,	SUF_Q
+incw,	incdec_insn,	(0x0040UL<<8)|NELEMS(incdec_insn),	CPU_Any,	SUF_W
+insb,	onebyte_insn,	(0x00006CUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+insertps,	insertps_insn,	(0UL<<8)|NELEMS(insertps_insn),	CPU_SSE41,	NONE
+insertq,	insertq_insn,	(0UL<<8)|NELEMS(insertq_insn),	CPU_SSE41,	NONE
+insl,	onebyte_insn,	(0x00206DUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+insw,	onebyte_insn,	(0x00106DUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+int,	int_insn,	(0UL<<8)|NELEMS(int_insn),	CPU_Any,	NONE
+int3,	onebyte_insn,	(0x0000CCUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+into,	onebyte_insn,	(0x0000CEUL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+invd,	twobyte_insn,	(0x0F08UL<<8)|NELEMS(twobyte_insn),	CPU_486|CPU_Priv,	NONE
+invlpg,	twobytemem_insn,	(0x070F01UL<<8)|NELEMS(twobytemem_insn),	CPU_486|CPU_Priv,	NONE
+invlpga,	invlpga_insn,	(0UL<<8)|NELEMS(invlpga_insn),	CPU_SVM,	NONE
+iret,	onebyte_insn,	(0x0000CFUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+iretl,	onebyte_insn,	(0x0020CFUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+iretq,	onebyte_insn,	(0x0040CFUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+iretw,	onebyte_insn,	(0x0010CFUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+ja,	jcc_insn,	(0x07UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jae,	jcc_insn,	(0x03UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jb,	jcc_insn,	(0x02UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jbe,	jcc_insn,	(0x06UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jc,	jcc_insn,	(0x02UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jcxz,	jcxz_insn,	(0x10UL<<8)|NELEMS(jcxz_insn),	CPU_Any,	NONE
+je,	jcc_insn,	(0x04UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jecxz,	jcxz_insn,	(0x20UL<<8)|NELEMS(jcxz_insn),	CPU_386,	NONE
+jg,	jcc_insn,	(0x0FUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jge,	jcc_insn,	(0x0DUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jl,	jcc_insn,	(0x0CUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jle,	jcc_insn,	(0x0EUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jmp,	jmp_insn,	(0UL<<8)|NELEMS(jmp_insn),	CPU_Any,	NONE
+jna,	jcc_insn,	(0x06UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnae,	jcc_insn,	(0x02UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnb,	jcc_insn,	(0x03UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnbe,	jcc_insn,	(0x07UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnc,	jcc_insn,	(0x03UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jne,	jcc_insn,	(0x05UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jng,	jcc_insn,	(0x0EUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnge,	jcc_insn,	(0x0CUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnl,	jcc_insn,	(0x0DUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnle,	jcc_insn,	(0x0FUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jno,	jcc_insn,	(0x01UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnp,	jcc_insn,	(0x0BUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jns,	jcc_insn,	(0x09UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnz,	jcc_insn,	(0x05UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jo,	jcc_insn,	(0x00UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jp,	jcc_insn,	(0x0AUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jpe,	jcc_insn,	(0x0AUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jpo,	jcc_insn,	(0x0BUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jrcxz,	jcxz_insn,	(0x40UL<<8)|NELEMS(jcxz_insn),	CPU_64,	NONE
+js,	jcc_insn,	(0x08UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jz,	jcc_insn,	(0x04UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+lahf,	onebyte_insn,	(0x00009FUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+lar,	bsfr_insn,	(0x02UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	NONE
+larl,	bsfr_insn,	(0x02UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	SUF_L
+larq,	bsfr_insn,	(0x02UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	SUF_Q
+larw,	bsfr_insn,	(0x02UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	SUF_W
+lddqu,	lddqu_insn,	(0UL<<8)|NELEMS(lddqu_insn),	CPU_SSE3,	NONE
+ldmxcsr,	ldstmxcsr_insn,	(0x02UL<<8)|NELEMS(ldstmxcsr_insn),	CPU_SSE,	NONE
+lds,	ldes_insn,	(0xC5UL<<8)|NELEMS(ldes_insn),	CPU_Not64,	NONE
+ldsl,	ldes_insn,	(0xC5UL<<8)|NELEMS(ldes_insn),	CPU_386|CPU_Not64,	SUF_L
+ldsw,	ldes_insn,	(0xC5UL<<8)|NELEMS(ldes_insn),	CPU_Not64,	SUF_W
+lea,	lea_insn,	(0UL<<8)|NELEMS(lea_insn),	CPU_Any,	NONE
+leal,	lea_insn,	(0UL<<8)|NELEMS(lea_insn),	CPU_386,	SUF_L
+leaq,	lea_insn,	(0UL<<8)|NELEMS(lea_insn),	CPU_64,	SUF_Q
+leaw,	lea_insn,	(0UL<<8)|NELEMS(lea_insn),	CPU_Any,	SUF_W
+leave,	onebyte_insn,	(0x4000C9UL<<8)|NELEMS(onebyte_insn),	CPU_186,	NONE
+leavel,	onebyte_insn,	(0x4000C9UL<<8)|NELEMS(onebyte_insn),	CPU_186,	NONE
+leaveq,	onebyte_insn,	(0x4000C9UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+leavew,	onebyte_insn,	(0x0010C9UL<<8)|NELEMS(onebyte_insn),	CPU_186,	NONE
+les,	ldes_insn,	(0xC4UL<<8)|NELEMS(ldes_insn),	CPU_Not64,	NONE
+lesl,	ldes_insn,	(0xC4UL<<8)|NELEMS(ldes_insn),	CPU_386|CPU_Not64,	SUF_L
+lesw,	ldes_insn,	(0xC4UL<<8)|NELEMS(ldes_insn),	CPU_Not64,	SUF_W
+lfence,	threebyte_insn,	(0x0FAEE8UL<<8)|NELEMS(threebyte_insn),	CPU_P3,	NONE
+lfs,	lfgss_insn,	(0xB4UL<<8)|NELEMS(lfgss_insn),	CPU_386,	NONE
+lfsl,	lfgss_insn,	(0xB4UL<<8)|NELEMS(lfgss_insn),	CPU_386,	SUF_L
+lfsw,	lfgss_insn,	(0xB4UL<<8)|NELEMS(lfgss_insn),	CPU_386,	SUF_W
+lgdt,	twobytemem_insn,	(0x020F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	NONE
+lgdtl,	twobytemem_insn,	(0x020F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_L
+lgdtq,	twobytemem_insn,	(0x020F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_Q
+lgdtw,	twobytemem_insn,	(0x020F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_W
+lgs,	lfgss_insn,	(0xB5UL<<8)|NELEMS(lfgss_insn),	CPU_386,	NONE
+lgsl,	lfgss_insn,	(0xB5UL<<8)|NELEMS(lfgss_insn),	CPU_386,	SUF_L
+lgsw,	lfgss_insn,	(0xB5UL<<8)|NELEMS(lfgss_insn),	CPU_386,	SUF_W
+lidt,	twobytemem_insn,	(0x030F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	NONE
+lidtl,	twobytemem_insn,	(0x030F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_L
+lidtq,	twobytemem_insn,	(0x030F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_Q
+lidtw,	twobytemem_insn,	(0x030F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_W
+lldt,	prot286_insn,	(0x0200UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Priv|CPU_Prot,	NONE
+lldtw,	prot286_insn,	(0x0200UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Priv|CPU_Prot,	SUF_W
+lmsw,	prot286_insn,	(0x0601UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Priv,	NONE
+lmsww,	prot286_insn,	(0x0601UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Priv,	SUF_W
+loadall,	twobyte_insn,	(0x0F07UL<<8)|NELEMS(twobyte_insn),	CPU_386|CPU_Undoc,	NONE
+loadall286,	twobyte_insn,	(0x0F05UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_Undoc,	NONE
+lock,	NULL,	X86_LOCKREP,	0xF0,	NONE
+lodsb,	onebyte_insn,	(0x0000ACUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+lodsl,	onebyte_insn,	(0x0020ADUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+lodsq,	onebyte_insn,	(0x0040ADUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+lodsw,	onebyte_insn,	(0x0010ADUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+loop,	loop_insn,	(0x02UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+loope,	loop_insn,	(0x01UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+loopne,	loop_insn,	(0x00UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+loopnz,	loop_insn,	(0x00UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+loopz,	loop_insn,	(0x01UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+lretl,	retnf_insn,	(0x00CAUL<<8)|NELEMS(retnf_insn),	CPU_Any,	NONE
+lretq,	retnf_insn,	(0x40CAUL<<8)|NELEMS(retnf_insn),	CPU_64,	NONE
+lretw,	retnf_insn,	(0x10CAUL<<8)|NELEMS(retnf_insn),	CPU_Any,	NONE
+lsl,	bsfr_insn,	(0x03UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	NONE
+lsll,	bsfr_insn,	(0x03UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	SUF_L
+lslq,	bsfr_insn,	(0x03UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	SUF_Q
+lslw,	bsfr_insn,	(0x03UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	SUF_W
+lss,	lfgss_insn,	(0xB2UL<<8)|NELEMS(lfgss_insn),	CPU_386,	NONE
+lssl,	lfgss_insn,	(0xB2UL<<8)|NELEMS(lfgss_insn),	CPU_386,	SUF_L
+lssw,	lfgss_insn,	(0xB2UL<<8)|NELEMS(lfgss_insn),	CPU_386,	SUF_W
+ltr,	prot286_insn,	(0x0300UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Priv|CPU_Prot,	NONE
+ltrw,	prot286_insn,	(0x0300UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Priv|CPU_Prot,	SUF_W
+lzcnt,	cnt_insn,	(0xBDUL<<8)|NELEMS(cnt_insn),	CPU_686|CPU_AMD,	NONE
+lzcntl,	cnt_insn,	(0xBDUL<<8)|NELEMS(cnt_insn),	CPU_686|CPU_AMD,	SUF_L
+lzcntq,	cnt_insn,	(0xBDUL<<8)|NELEMS(cnt_insn),	CPU_686|CPU_AMD,	SUF_Q
+lzcntw,	cnt_insn,	(0xBDUL<<8)|NELEMS(cnt_insn),	CPU_686|CPU_AMD,	SUF_W
+maskmovdqu,	maskmovdqu_insn,	(0UL<<8)|NELEMS(maskmovdqu_insn),	CPU_SSE2,	NONE
+maskmovq,	maskmovq_insn,	(0UL<<8)|NELEMS(maskmovq_insn),	CPU_MMX|CPU_P3,	NONE
+maxpd,	ssess_insn,	(0x665FUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+maxps,	sseps_insn,	(0x5FUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+maxsd,	ssess_insn,	(0xF25FUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+maxss,	ssess_insn,	(0xF35FUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+mfence,	threebyte_insn,	(0x0FAEF0UL<<8)|NELEMS(threebyte_insn),	CPU_P3,	NONE
+minpd,	ssess_insn,	(0x665DUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+minps,	sseps_insn,	(0x5DUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+minsd,	ssess_insn,	(0xF25DUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+minss,	ssess_insn,	(0xF35DUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+monitor,	threebyte_insn,	(0x0F01C8UL<<8)|NELEMS(threebyte_insn),	CPU_SSE3,	NONE
+montmul,	padlock_insn,	(0xC0F3A6UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+mov,	mov_insn,	(0UL<<8)|NELEMS(mov_insn),	CPU_Any,	NONE
+movb,	mov_insn,	(0UL<<8)|NELEMS(mov_insn),	CPU_Any,	SUF_B
+movl,	mov_insn,	(0UL<<8)|NELEMS(mov_insn),	CPU_386,	SUF_L
+movq,	mov_insn,	(0UL<<8)|NELEMS(mov_insn),	CPU_Any,	SUF_Q
+movw,	mov_insn,	(0UL<<8)|NELEMS(mov_insn),	CPU_Any,	SUF_W
+movabs,	movabs_insn,	(0UL<<8)|NELEMS(movabs_insn),	CPU_64,	NONE
+movabsb,	movabs_insn,	(0UL<<8)|NELEMS(movabs_insn),	CPU_64,	SUF_B
+movabsl,	movabs_insn,	(0UL<<8)|NELEMS(movabs_insn),	CPU_64,	SUF_L
+movabsq,	movabs_insn,	(0UL<<8)|NELEMS(movabs_insn),	CPU_64,	SUF_Q
+movabsw,	movabs_insn,	(0UL<<8)|NELEMS(movabs_insn),	CPU_64,	SUF_W
+movapd,	movaupd_insn,	(0x28UL<<8)|NELEMS(movaupd_insn),	CPU_SSE2,	NONE
+movaps,	movaups_insn,	(0x28UL<<8)|NELEMS(movaups_insn),	CPU_SSE,	NONE
+movd,	movd_insn,	(0UL<<8)|NELEMS(movd_insn),	CPU_386|CPU_MMX,	NONE
+movddup,	cvt_xmm_xmm64_ss_insn,	(0xF212UL<<8)|NELEMS(cvt_xmm_xmm64_ss_insn),	CPU_SSE3,	NONE
+movdq2q,	movdq2q_insn,	(0UL<<8)|NELEMS(movdq2q_insn),	CPU_SSE2,	NONE
+movdqa,	movdqau_insn,	(0x66UL<<8)|NELEMS(movdqau_insn),	CPU_SSE2,	NONE
+movdqu,	movdqau_insn,	(0xF3UL<<8)|NELEMS(movdqau_insn),	CPU_SSE2,	NONE
+movhlps,	movhllhps_insn,	(0x12UL<<8)|NELEMS(movhllhps_insn),	CPU_SSE,	NONE
+movhpd,	movhlpd_insn,	(0x16UL<<8)|NELEMS(movhlpd_insn),	CPU_SSE2,	NONE
+movhps,	movhlps_insn,	(0x16UL<<8)|NELEMS(movhlps_insn),	CPU_SSE,	NONE
+movlhps,	movhllhps_insn,	(0x16UL<<8)|NELEMS(movhllhps_insn),	CPU_SSE,	NONE
+movlpd,	movhlpd_insn,	(0x12UL<<8)|NELEMS(movhlpd_insn),	CPU_SSE2,	NONE
+movlps,	movhlps_insn,	(0x12UL<<8)|NELEMS(movhlps_insn),	CPU_SSE,	NONE
+movmskpd,	movmskpd_insn,	(0UL<<8)|NELEMS(movmskpd_insn),	CPU_386|CPU_SSE2,	NONE
+movmskpdl,	movmskpd_insn,	(0UL<<8)|NELEMS(movmskpd_insn),	CPU_386|CPU_SSE2,	SUF_L
+movmskpdq,	movmskpd_insn,	(0UL<<8)|NELEMS(movmskpd_insn),	CPU_64|CPU_SSE2,	SUF_Q
+movmskps,	movmskps_insn,	(0UL<<8)|NELEMS(movmskps_insn),	CPU_386|CPU_SSE,	NONE
+movmskpsl,	movmskps_insn,	(0UL<<8)|NELEMS(movmskps_insn),	CPU_386|CPU_SSE,	SUF_L
+movmskpsq,	movmskps_insn,	(0UL<<8)|NELEMS(movmskps_insn),	CPU_64|CPU_SSE,	SUF_Q
+movntdq,	movntpddq_insn,	(0xE7UL<<8)|NELEMS(movntpddq_insn),	CPU_SSE2,	NONE
+movntdqa,	movntdqa_insn,	(0UL<<8)|NELEMS(movntdqa_insn),	CPU_SSE41,	NONE
+movnti,	movnti_insn,	(0UL<<8)|NELEMS(movnti_insn),	CPU_P4,	NONE
+movntil,	movnti_insn,	(0UL<<8)|NELEMS(movnti_insn),	CPU_P4,	SUF_L
+movntiq,	movnti_insn,	(0UL<<8)|NELEMS(movnti_insn),	CPU_64|CPU_P4,	SUF_Q
+movntpd,	movntpddq_insn,	(0x2BUL<<8)|NELEMS(movntpddq_insn),	CPU_SSE2,	NONE
+movntps,	movntps_insn,	(0UL<<8)|NELEMS(movntps_insn),	CPU_SSE,	NONE
+movntq,	movntq_insn,	(0UL<<8)|NELEMS(movntq_insn),	CPU_SSE,	NONE
+movntsd,	movntsd_insn,	(0UL<<8)|NELEMS(movntsd_insn),	CPU_SSE41,	NONE
+movntss,	movntss_insn,	(0UL<<8)|NELEMS(movntss_insn),	CPU_SSE41,	NONE
+movq2dq,	movq2dq_insn,	(0UL<<8)|NELEMS(movq2dq_insn),	CPU_SSE2,	NONE
+movsb,	onebyte_insn,	(0x0000A4UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+movsbl,	movszx_insn,	(0xBEUL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_B
+movsbq,	movszx_insn,	(0xBEUL<<8)|NELEMS(movszx_insn),	CPU_64,	SUF_B
+movsbw,	movszx_insn,	(0xBEUL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_B
+movsd,	movsd_insn,	(0UL<<8)|NELEMS(movsd_insn),	CPU_386,	NONE
+movshdup,	ssess_insn,	(0xF316UL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+movsl,	onebyte_insn,	(0x0020A5UL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+movsldup,	ssess_insn,	(0xF312UL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+movslq,	movsxd_insn,	(0UL<<8)|NELEMS(movsxd_insn),	CPU_64,	SUF_L
+movsq,	onebyte_insn,	(0x0040A5UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+movss,	movss_insn,	(0UL<<8)|NELEMS(movss_insn),	CPU_SSE,	NONE
+movsw,	onebyte_insn,	(0x0010A5UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+movswl,	movszx_insn,	(0xBEUL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_W
+movswq,	movszx_insn,	(0xBEUL<<8)|NELEMS(movszx_insn),	CPU_64,	SUF_W
+movsx,	movszx_insn,	(0xBEUL<<8)|NELEMS(movszx_insn),	CPU_386,	NONE
+movsxb,	movszx_insn,	(0xBEUL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_B
+movsxw,	movszx_insn,	(0xBEUL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_W
+movupd,	movaupd_insn,	(0x10UL<<8)|NELEMS(movaupd_insn),	CPU_SSE2,	NONE
+movups,	movaups_insn,	(0x10UL<<8)|NELEMS(movaups_insn),	CPU_SSE,	NONE
+movzbl,	movszx_insn,	(0xB6UL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_B
+movzbq,	movszx_insn,	(0xB6UL<<8)|NELEMS(movszx_insn),	CPU_64,	SUF_B
+movzbw,	movszx_insn,	(0xB6UL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_B
+movzwl,	movszx_insn,	(0xB6UL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_W
+movzwq,	movszx_insn,	(0xB6UL<<8)|NELEMS(movszx_insn),	CPU_64,	SUF_W
+movzx,	movszx_insn,	(0xB6UL<<8)|NELEMS(movszx_insn),	CPU_386,	NONE
+movzxb,	movszx_insn,	(0xB6UL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_B
+movzxw,	movszx_insn,	(0xB6UL<<8)|NELEMS(movszx_insn),	CPU_386,	SUF_W
+mpsadbw,	sse4imm_insn,	(0x42UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+mul,	f6_insn,	(0x04UL<<8)|NELEMS(f6_insn),	CPU_Any,	NONE
+mulb,	f6_insn,	(0x04UL<<8)|NELEMS(f6_insn),	CPU_Any,	SUF_B
+mull,	f6_insn,	(0x04UL<<8)|NELEMS(f6_insn),	CPU_386,	SUF_L
+mulq,	f6_insn,	(0x04UL<<8)|NELEMS(f6_insn),	CPU_64,	SUF_Q
+mulw,	f6_insn,	(0x04UL<<8)|NELEMS(f6_insn),	CPU_Any,	SUF_W
+mulpd,	ssess_insn,	(0x6659UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+mulps,	sseps_insn,	(0x59UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+mulsd,	ssess_insn,	(0xF259UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+mulss,	ssess_insn,	(0xF359UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+mwait,	threebyte_insn,	(0x0F01C9UL<<8)|NELEMS(threebyte_insn),	CPU_SSE3,	NONE
+neg,	f6_insn,	(0x03UL<<8)|NELEMS(f6_insn),	CPU_Any,	NONE
+negb,	f6_insn,	(0x03UL<<8)|NELEMS(f6_insn),	CPU_Any,	SUF_B
+negl,	f6_insn,	(0x03UL<<8)|NELEMS(f6_insn),	CPU_386,	SUF_L
+negq,	f6_insn,	(0x03UL<<8)|NELEMS(f6_insn),	CPU_64,	SUF_Q
+negw,	f6_insn,	(0x03UL<<8)|NELEMS(f6_insn),	CPU_Any,	SUF_W
+nop,	onebyte_insn,	(0x000090UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+not,	f6_insn,	(0x02UL<<8)|NELEMS(f6_insn),	CPU_Any,	NONE
+notb,	f6_insn,	(0x02UL<<8)|NELEMS(f6_insn),	CPU_Any,	SUF_B
+notl,	f6_insn,	(0x02UL<<8)|NELEMS(f6_insn),	CPU_386,	SUF_L
+notq,	f6_insn,	(0x02UL<<8)|NELEMS(f6_insn),	CPU_64,	SUF_Q
+notw,	f6_insn,	(0x02UL<<8)|NELEMS(f6_insn),	CPU_Any,	SUF_W
+or,	arith_insn,	(0x0108UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+orb,	arith_insn,	(0x0108UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_B
+orl,	arith_insn,	(0x0108UL<<8)|NELEMS(arith_insn),	CPU_386,	SUF_L
+orq,	arith_insn,	(0x0108UL<<8)|NELEMS(arith_insn),	CPU_64,	SUF_Q
+orw,	arith_insn,	(0x0108UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_W
+orpd,	ssess_insn,	(0x6656UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+orps,	sseps_insn,	(0x56UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+out,	out_insn,	(0UL<<8)|NELEMS(out_insn),	CPU_Any,	NONE
+outb,	out_insn,	(0UL<<8)|NELEMS(out_insn),	CPU_Any,	SUF_B
+outl,	out_insn,	(0UL<<8)|NELEMS(out_insn),	CPU_386,	SUF_L
+outw,	out_insn,	(0UL<<8)|NELEMS(out_insn),	CPU_Any,	SUF_W
+outsb,	onebyte_insn,	(0x00006EUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+outsl,	onebyte_insn,	(0x00206FUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+outsw,	onebyte_insn,	(0x00106FUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+pabsb,	ssse3_insn,	(0x1CUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pabsd,	ssse3_insn,	(0x1EUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pabsw,	ssse3_insn,	(0x1DUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+packssdw,	mmxsse2_insn,	(0x6BUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+packsswb,	mmxsse2_insn,	(0x63UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+packusdw,	sse4_insn,	(0x2BUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+packuswb,	mmxsse2_insn,	(0x67UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddb,	mmxsse2_insn,	(0xFCUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddd,	mmxsse2_insn,	(0xFEUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddq,	mmxsse2_insn,	(0xD4UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddsb,	mmxsse2_insn,	(0xECUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddsiw,	cyrixmmx_insn,	(0x51UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+paddsw,	mmxsse2_insn,	(0xEDUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddusb,	mmxsse2_insn,	(0xDCUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddusw,	mmxsse2_insn,	(0xDDUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddw,	mmxsse2_insn,	(0xFDUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+palignr,	ssse3imm_insn,	(0x0FUL<<8)|NELEMS(ssse3imm_insn),	CPU_SSSE3,	NONE
+pand,	mmxsse2_insn,	(0xDBUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pandn,	mmxsse2_insn,	(0xDFUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pause,	onebyte_prefix_insn,	(0xF390UL<<8)|NELEMS(onebyte_prefix_insn),	CPU_P4,	NONE
+paveb,	cyrixmmx_insn,	(0x50UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pavgb,	mmxsse2_insn,	(0xE0UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pavgusb,	now3d_insn,	(0xBFUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pavgw,	mmxsse2_insn,	(0xE3UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pblendvb,	sse4xmm0_insn,	(0x10UL<<8)|NELEMS(sse4xmm0_insn),	CPU_SSE41,	NONE
+pblendw,	sse4imm_insn,	(0x0EUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+pcmpeqb,	mmxsse2_insn,	(0x74UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpeqd,	mmxsse2_insn,	(0x76UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpeqq,	sse4_insn,	(0x29UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pcmpeqw,	mmxsse2_insn,	(0x75UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpestri,	sse4pcmpstr_insn,	(0x61UL<<8)|NELEMS(sse4pcmpstr_insn),	CPU_SSE42,	NONE
+pcmpestrm,	sse4pcmpstr_insn,	(0x60UL<<8)|NELEMS(sse4pcmpstr_insn),	CPU_SSE42,	NONE
+pcmpgtb,	mmxsse2_insn,	(0x64UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpgtd,	mmxsse2_insn,	(0x66UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpgtq,	sse4_insn,	(0x37UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pcmpgtw,	mmxsse2_insn,	(0x65UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpistri,	sse4pcmpstr_insn,	(0x63UL<<8)|NELEMS(sse4pcmpstr_insn),	CPU_SSE42,	NONE
+pcmpistrm,	sse4pcmpstr_insn,	(0x62UL<<8)|NELEMS(sse4pcmpstr_insn),	CPU_SSE42,	NONE
+pdistib,	cyrixmmx_insn,	(0x54UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pextrb,	pextrb_insn,	(0UL<<8)|NELEMS(pextrb_insn),	CPU_SSE41,	NONE
+pextrd,	pextrd_insn,	(0UL<<8)|NELEMS(pextrd_insn),	CPU_386|CPU_SSE41,	NONE
+pextrq,	pextrq_insn,	(0UL<<8)|NELEMS(pextrq_insn),	CPU_64|CPU_SSE41,	NONE
+pextrw,	pextrw_insn,	(0UL<<8)|NELEMS(pextrw_insn),	CPU_MMX|CPU_P3,	NONE
+pextrwl,	pextrw_insn,	(0UL<<8)|NELEMS(pextrw_insn),	CPU_MMX|CPU_P3,	SUF_L
+pextrwq,	pextrw_insn,	(0UL<<8)|NELEMS(pextrw_insn),	CPU_64|CPU_MMX|CPU_P3,	SUF_Q
+pf2id,	now3d_insn,	(0x1DUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pf2iw,	now3d_insn,	(0x1CUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+pfacc,	now3d_insn,	(0xAEUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfadd,	now3d_insn,	(0x9EUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfcmpeq,	now3d_insn,	(0xB0UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfcmpge,	now3d_insn,	(0x90UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfcmpgt,	now3d_insn,	(0xA0UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfmax,	now3d_insn,	(0xA4UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfmin,	now3d_insn,	(0x94UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfmul,	now3d_insn,	(0xB4UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfnacc,	now3d_insn,	(0x8AUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+pfpnacc,	now3d_insn,	(0x8EUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+pfrcp,	now3d_insn,	(0x96UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfrcpit1,	now3d_insn,	(0xA6UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfrcpit2,	now3d_insn,	(0xB6UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfrsqit1,	now3d_insn,	(0xA7UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfrsqrt,	now3d_insn,	(0x97UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfsub,	now3d_insn,	(0x9AUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfsubr,	now3d_insn,	(0xAAUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+phaddd,	ssse3_insn,	(0x02UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phaddsw,	ssse3_insn,	(0x03UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phaddw,	ssse3_insn,	(0x01UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phminposuw,	sse4_insn,	(0x41UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+phsubd,	ssse3_insn,	(0x06UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phsubsw,	ssse3_insn,	(0x07UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phsubw,	ssse3_insn,	(0x05UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pi2fd,	now3d_insn,	(0x0DUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pi2fw,	now3d_insn,	(0x0CUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+pinsrb,	pinsrb_insn,	(0UL<<8)|NELEMS(pinsrb_insn),	CPU_SSE41,	NONE
+pinsrd,	pinsrd_insn,	(0UL<<8)|NELEMS(pinsrd_insn),	CPU_386|CPU_SSE41,	NONE
+pinsrq,	pinsrq_insn,	(0UL<<8)|NELEMS(pinsrq_insn),	CPU_64|CPU_SSE41,	NONE
+pinsrw,	pinsrw_insn,	(0UL<<8)|NELEMS(pinsrw_insn),	CPU_MMX|CPU_P3,	NONE
+pinsrwl,	pinsrw_insn,	(0UL<<8)|NELEMS(pinsrw_insn),	CPU_MMX|CPU_P3,	SUF_L
+pinsrwq,	pinsrw_insn,	(0UL<<8)|NELEMS(pinsrw_insn),	CPU_64|CPU_MMX|CPU_P3,	SUF_Q
+pmachriw,	pmachriw_insn,	(0UL<<8)|NELEMS(pmachriw_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmaddubsw,	ssse3_insn,	(0x04UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pmaddwd,	mmxsse2_insn,	(0xF5UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pmagw,	cyrixmmx_insn,	(0x52UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmaxsb,	sse4_insn,	(0x3CUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmaxsd,	sse4_insn,	(0x3DUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmaxsw,	mmxsse2_insn,	(0xEEUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pmaxub,	mmxsse2_insn,	(0xDEUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pmaxud,	sse4_insn,	(0x3FUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmaxuw,	sse4_insn,	(0x3EUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pminsb,	sse4_insn,	(0x38UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pminsd,	sse4_insn,	(0x39UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pminsw,	mmxsse2_insn,	(0xEAUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pminub,	mmxsse2_insn,	(0xDAUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pminud,	sse4_insn,	(0x3BUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pminuw,	sse4_insn,	(0x3AUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmovmskb,	pmovmskb_insn,	(0UL<<8)|NELEMS(pmovmskb_insn),	CPU_MMX|CPU_P3,	NONE
+pmovmskbl,	pmovmskb_insn,	(0UL<<8)|NELEMS(pmovmskb_insn),	CPU_MMX|CPU_P3,	SUF_L
+pmovmskbq,	pmovmskb_insn,	(0UL<<8)|NELEMS(pmovmskb_insn),	CPU_64|CPU_MMX|CPU_P3,	SUF_Q
+pmovsxbd,	sse4m32_insn,	(0x21UL<<8)|NELEMS(sse4m32_insn),	CPU_SSE41,	NONE
+pmovsxbq,	sse4m16_insn,	(0x22UL<<8)|NELEMS(sse4m16_insn),	CPU_SSE41,	NONE
+pmovsxbw,	sse4m64_insn,	(0x20UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovsxdq,	sse4m64_insn,	(0x25UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovsxwd,	sse4m64_insn,	(0x23UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovsxwq,	sse4m32_insn,	(0x24UL<<8)|NELEMS(sse4m32_insn),	CPU_SSE41,	NONE
+pmovzxbd,	sse4m32_insn,	(0x31UL<<8)|NELEMS(sse4m32_insn),	CPU_SSE41,	NONE
+pmovzxbq,	sse4m16_insn,	(0x32UL<<8)|NELEMS(sse4m16_insn),	CPU_SSE41,	NONE
+pmovzxbw,	sse4m64_insn,	(0x30UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovzxdq,	sse4m64_insn,	(0x35UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovzxwd,	sse4m64_insn,	(0x33UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovzxwq,	sse4m32_insn,	(0x34UL<<8)|NELEMS(sse4m32_insn),	CPU_SSE41,	NONE
+pmuldq,	sse4_insn,	(0x28UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmulhriw,	cyrixmmx_insn,	(0x5DUL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmulhrsw,	ssse3_insn,	(0x0BUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pmulhrwa,	now3d_insn,	(0xB7UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pmulhrwc,	cyrixmmx_insn,	(0x59UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmulhuw,	mmxsse2_insn,	(0xE4UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pmulhw,	mmxsse2_insn,	(0xE5UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pmulld,	sse4_insn,	(0x40UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmullw,	mmxsse2_insn,	(0xD5UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pmuludq,	mmxsse2_insn,	(0xF4UL<<8)|NELEMS(mmxsse2_insn),	CPU_SSE2,	NONE
+pmvgezb,	cyrixmmx_insn,	(0x5CUL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmvlzb,	cyrixmmx_insn,	(0x5BUL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmvnzb,	cyrixmmx_insn,	(0x5AUL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmvzb,	cyrixmmx_insn,	(0x58UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pop,	pop_insn,	(0UL<<8)|NELEMS(pop_insn),	CPU_Any,	NONE
+popl,	pop_insn,	(0UL<<8)|NELEMS(pop_insn),	CPU_386|CPU_Not64,	SUF_L
+popq,	pop_insn,	(0UL<<8)|NELEMS(pop_insn),	CPU_64,	SUF_Q
+popw,	pop_insn,	(0UL<<8)|NELEMS(pop_insn),	CPU_Any,	SUF_W
+popa,	onebyte_insn,	(0x000061UL<<8)|NELEMS(onebyte_insn),	CPU_186|CPU_Not64,	NONE
+popal,	onebyte_insn,	(0x002061UL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Not64,	NONE
+popaw,	onebyte_insn,	(0x001061UL<<8)|NELEMS(onebyte_insn),	CPU_186|CPU_Not64,	NONE
+popcnt,	cnt_insn,	(0xB8UL<<8)|NELEMS(cnt_insn),	CPU_SSE42,	NONE
+popcntl,	cnt_insn,	(0xB8UL<<8)|NELEMS(cnt_insn),	CPU_SSE42,	SUF_L
+popcntq,	cnt_insn,	(0xB8UL<<8)|NELEMS(cnt_insn),	CPU_SSE42,	SUF_Q
+popcntw,	cnt_insn,	(0xB8UL<<8)|NELEMS(cnt_insn),	CPU_SSE42,	SUF_W
+popf,	onebyte_insn,	(0x40009DUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+popfl,	onebyte_insn,	(0x00209DUL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Not64,	NONE
+popfq,	onebyte_insn,	(0x40409DUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+popfw,	onebyte_insn,	(0x40109DUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+por,	mmxsse2_insn,	(0xEBUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+prefetch,	twobytemem_insn,	(0x000F0DUL<<8)|NELEMS(twobytemem_insn),	CPU_3DNow,	NONE
+prefetchnta,	twobytemem_insn,	(0x000F18UL<<8)|NELEMS(twobytemem_insn),	CPU_P3,	NONE
+prefetcht0,	twobytemem_insn,	(0x010F18UL<<8)|NELEMS(twobytemem_insn),	CPU_P3,	NONE
+prefetcht1,	twobytemem_insn,	(0x020F18UL<<8)|NELEMS(twobytemem_insn),	CPU_P3,	NONE
+prefetcht2,	twobytemem_insn,	(0x030F18UL<<8)|NELEMS(twobytemem_insn),	CPU_P3,	NONE
+prefetchw,	twobytemem_insn,	(0x010F0DUL<<8)|NELEMS(twobytemem_insn),	CPU_3DNow,	NONE
+psadbw,	mmxsse2_insn,	(0xF6UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pshufb,	ssse3_insn,	(0x00UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pshufd,	ssessimm_insn,	(0x6670UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+pshufhw,	ssessimm_insn,	(0xF370UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+pshuflw,	ssessimm_insn,	(0xF270UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+pshufw,	pshufw_insn,	(0UL<<8)|NELEMS(pshufw_insn),	CPU_MMX|CPU_P3,	NONE
+psignb,	ssse3_insn,	(0x08UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+psignd,	ssse3_insn,	(0x0AUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+psignw,	ssse3_insn,	(0x09UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pslld,	pshift_insn,	(0x0672F2UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+pslldq,	pslrldq_insn,	(0x07UL<<8)|NELEMS(pslrldq_insn),	CPU_SSE2,	NONE
+psllq,	pshift_insn,	(0x0673F3UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psllw,	pshift_insn,	(0x0671F1UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psrad,	pshift_insn,	(0x0472E2UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psraw,	pshift_insn,	(0x0471E1UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psrld,	pshift_insn,	(0x0272D2UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psrldq,	pslrldq_insn,	(0x03UL<<8)|NELEMS(pslrldq_insn),	CPU_SSE2,	NONE
+psrlq,	pshift_insn,	(0x0273D3UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psrlw,	pshift_insn,	(0x0271D1UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psubb,	mmxsse2_insn,	(0xF8UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubd,	mmxsse2_insn,	(0xFAUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubq,	mmxsse2_insn,	(0xFBUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubsb,	mmxsse2_insn,	(0xE8UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubsiw,	cyrixmmx_insn,	(0x55UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+psubsw,	mmxsse2_insn,	(0xE9UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubusb,	mmxsse2_insn,	(0xD8UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubusw,	mmxsse2_insn,	(0xD9UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubw,	mmxsse2_insn,	(0xF9UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pswapd,	now3d_insn,	(0xBBUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+ptest,	sse4_insn,	(0x17UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+punpckhbw,	mmxsse2_insn,	(0x68UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpckhdq,	mmxsse2_insn,	(0x6AUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpckhqdq,	ssess_insn,	(0x666DUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+punpckhwd,	mmxsse2_insn,	(0x69UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpcklbw,	mmxsse2_insn,	(0x60UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpckldq,	mmxsse2_insn,	(0x62UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpcklqdq,	ssess_insn,	(0x666CUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+punpcklwd,	mmxsse2_insn,	(0x61UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+push,	push_insn,	(0UL<<8)|NELEMS(push_insn),	CPU_Any,	NONE
+pushl,	push_insn,	(0UL<<8)|NELEMS(push_insn),	CPU_386,	SUF_L
+pushq,	push_insn,	(0UL<<8)|NELEMS(push_insn),	CPU_64,	SUF_Q
+pushw,	push_insn,	(0UL<<8)|NELEMS(push_insn),	CPU_Any,	SUF_W
+pusha,	onebyte_insn,	(0x000060UL<<8)|NELEMS(onebyte_insn),	CPU_186|CPU_Not64,	NONE
+pushal,	onebyte_insn,	(0x002060UL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Not64,	NONE
+pushaw,	onebyte_insn,	(0x001060UL<<8)|NELEMS(onebyte_insn),	CPU_186|CPU_Not64,	NONE
+pushf,	onebyte_insn,	(0x40009CUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+pushfl,	onebyte_insn,	(0x00209CUL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Not64,	NONE
+pushfq,	onebyte_insn,	(0x40409CUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+pushfw,	onebyte_insn,	(0x40109CUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+pxor,	mmxsse2_insn,	(0xEFUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+qword,	NULL,	X86_OPERSIZE,	0x40,	NONE
+rcl,	shift_insn,	(0x02UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+rclb,	shift_insn,	(0x02UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_B
+rcll,	shift_insn,	(0x02UL<<8)|NELEMS(shift_insn),	CPU_386,	SUF_L
+rclq,	shift_insn,	(0x02UL<<8)|NELEMS(shift_insn),	CPU_64,	SUF_Q
+rclw,	shift_insn,	(0x02UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_W
+rcpps,	sseps_insn,	(0x53UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+rcpss,	ssess_insn,	(0xF353UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+rcr,	shift_insn,	(0x03UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+rcrb,	shift_insn,	(0x03UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_B
+rcrl,	shift_insn,	(0x03UL<<8)|NELEMS(shift_insn),	CPU_386,	SUF_L
+rcrq,	shift_insn,	(0x03UL<<8)|NELEMS(shift_insn),	CPU_64,	SUF_Q
+rcrw,	shift_insn,	(0x03UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_W
+rdmsr,	twobyte_insn,	(0x0F32UL<<8)|NELEMS(twobyte_insn),	CPU_586|CPU_Priv,	NONE
+rdpmc,	twobyte_insn,	(0x0F33UL<<8)|NELEMS(twobyte_insn),	CPU_686,	NONE
+rdshr,	rdwrshr_insn,	(0x00UL<<8)|NELEMS(rdwrshr_insn),	CPU_686|CPU_Cyrix|CPU_SMM,	NONE
+rdtsc,	twobyte_insn,	(0x0F31UL<<8)|NELEMS(twobyte_insn),	CPU_586,	NONE
+rdtscp,	threebyte_insn,	(0x0F01F9UL<<8)|NELEMS(threebyte_insn),	CPU_686|CPU_AMD|CPU_Priv,	NONE
+rep,	NULL,	X86_LOCKREP,	0xF3,	NONE
+repe,	NULL,	X86_LOCKREP,	0xF3,	NONE
+repne,	NULL,	X86_LOCKREP,	0xF2,	NONE
+repnz,	NULL,	X86_LOCKREP,	0xF2,	NONE
+repz,	NULL,	X86_LOCKREP,	0xF3,	NONE
+ret,	retnf_insn,	(0x00C2UL<<8)|NELEMS(retnf_insn),	CPU_Any,	NONE
+retl,	retnf_insn,	(0x00C2UL<<8)|NELEMS(retnf_insn),	CPU_Not64,	NONE
+retq,	retnf_insn,	(0x00C2UL<<8)|NELEMS(retnf_insn),	CPU_64,	NONE
+retw,	retnf_insn,	(0x10C2UL<<8)|NELEMS(retnf_insn),	CPU_Any,	NONE
+rex,	NULL,	X86_REX,	0x40,	NONE
+rex64,	NULL,	X86_REX,	0x48,	NONE
+rex64x,	NULL,	X86_REX,	0x4C,	NONE
+rex64xy,	NULL,	X86_REX,	0x4E,	NONE
+rex64xyz,	NULL,	X86_REX,	0x4F,	NONE
+rex64xz,	NULL,	X86_REX,	0x4D,	NONE
+rex64y,	NULL,	X86_REX,	0x4A,	NONE
+rex64yz,	NULL,	X86_REX,	0x4B,	NONE
+rex64z,	NULL,	X86_REX,	0x49,	NONE
+rexx,	NULL,	X86_REX,	0x44,	NONE
+rexxy,	NULL,	X86_REX,	0x46,	NONE
+rexxyz,	NULL,	X86_REX,	0x47,	NONE
+rexxz,	NULL,	X86_REX,	0x45,	NONE
+rexy,	NULL,	X86_REX,	0x42,	NONE
+rexyz,	NULL,	X86_REX,	0x43,	NONE
+rexz,	NULL,	X86_REX,	0x41,	NONE
+rol,	shift_insn,	(0x00UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+rolb,	shift_insn,	(0x00UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_B
+roll,	shift_insn,	(0x00UL<<8)|NELEMS(shift_insn),	CPU_386,	SUF_L
+rolq,	shift_insn,	(0x00UL<<8)|NELEMS(shift_insn),	CPU_64,	SUF_Q
+rolw,	shift_insn,	(0x00UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_W
+ror,	shift_insn,	(0x01UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+rorb,	shift_insn,	(0x01UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_B
+rorl,	shift_insn,	(0x01UL<<8)|NELEMS(shift_insn),	CPU_386,	SUF_L
+rorq,	shift_insn,	(0x01UL<<8)|NELEMS(shift_insn),	CPU_64,	SUF_Q
+rorw,	shift_insn,	(0x01UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_W
+roundpd,	sse4imm_insn,	(0x09UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+roundps,	sse4imm_insn,	(0x08UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+roundsd,	sse4imm_insn,	(0x0BUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+roundss,	sse4imm_insn,	(0x0AUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+rsdc,	rsdc_insn,	(0UL<<8)|NELEMS(rsdc_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+rsldt,	cyrixsmm_insn,	(0x7BUL<<8)|NELEMS(cyrixsmm_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+rsm,	twobyte_insn,	(0x0FAAUL<<8)|NELEMS(twobyte_insn),	CPU_586|CPU_SMM,	NONE
+rsqrtps,	sseps_insn,	(0x52UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+rsqrtss,	ssess_insn,	(0xF352UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+rsts,	cyrixsmm_insn,	(0x7DUL<<8)|NELEMS(cyrixsmm_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+sahf,	onebyte_insn,	(0x00009EUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+sal,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+salb,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_B
+sall,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_386,	SUF_L
+salq,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_64,	SUF_Q
+salw,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_W
+salc,	onebyte_insn,	(0x0000D6UL<<8)|NELEMS(onebyte_insn),	CPU_Not64|CPU_Undoc,	NONE
+sar,	shift_insn,	(0x07UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+sarb,	shift_insn,	(0x07UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_B
+sarl,	shift_insn,	(0x07UL<<8)|NELEMS(shift_insn),	CPU_386,	SUF_L
+sarq,	shift_insn,	(0x07UL<<8)|NELEMS(shift_insn),	CPU_64,	SUF_Q
+sarw,	shift_insn,	(0x07UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_W
+sbb,	arith_insn,	(0x0318UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+sbbb,	arith_insn,	(0x0318UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_B
+sbbl,	arith_insn,	(0x0318UL<<8)|NELEMS(arith_insn),	CPU_386,	SUF_L
+sbbq,	arith_insn,	(0x0318UL<<8)|NELEMS(arith_insn),	CPU_64,	SUF_Q
+sbbw,	arith_insn,	(0x0318UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_W
+scasb,	onebyte_insn,	(0x0000AEUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+scasl,	onebyte_insn,	(0x0020AFUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+scasq,	onebyte_insn,	(0x0040AFUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+scasw,	onebyte_insn,	(0x0010AFUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+seta,	setcc_insn,	(0x07UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setab,	setcc_insn,	(0x07UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setae,	setcc_insn,	(0x03UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setaeb,	setcc_insn,	(0x03UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setb,	setcc_insn,	(0x02UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setbb,	setcc_insn,	(0x02UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setbe,	setcc_insn,	(0x06UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setbeb,	setcc_insn,	(0x06UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setc,	setcc_insn,	(0x02UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setcb,	setcc_insn,	(0x02UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+sete,	setcc_insn,	(0x04UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+seteb,	setcc_insn,	(0x04UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setg,	setcc_insn,	(0x0FUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setgb,	setcc_insn,	(0x0FUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setge,	setcc_insn,	(0x0DUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setgeb,	setcc_insn,	(0x0DUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setl,	setcc_insn,	(0x0CUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setlb,	setcc_insn,	(0x0CUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setle,	setcc_insn,	(0x0EUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setleb,	setcc_insn,	(0x0EUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setna,	setcc_insn,	(0x06UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnab,	setcc_insn,	(0x06UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setnae,	setcc_insn,	(0x02UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnaeb,	setcc_insn,	(0x02UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setnb,	setcc_insn,	(0x03UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnbb,	setcc_insn,	(0x03UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setnbe,	setcc_insn,	(0x07UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnbeb,	setcc_insn,	(0x07UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setnc,	setcc_insn,	(0x03UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setncb,	setcc_insn,	(0x03UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setne,	setcc_insn,	(0x05UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setneb,	setcc_insn,	(0x05UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setng,	setcc_insn,	(0x0EUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setngb,	setcc_insn,	(0x0EUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setnge,	setcc_insn,	(0x0CUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setngeb,	setcc_insn,	(0x0CUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setnl,	setcc_insn,	(0x0DUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnlb,	setcc_insn,	(0x0DUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setnle,	setcc_insn,	(0x0FUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnleb,	setcc_insn,	(0x0FUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setno,	setcc_insn,	(0x01UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnob,	setcc_insn,	(0x01UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setnp,	setcc_insn,	(0x0BUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnpb,	setcc_insn,	(0x0BUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setns,	setcc_insn,	(0x09UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnsb,	setcc_insn,	(0x09UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setnz,	setcc_insn,	(0x05UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnzb,	setcc_insn,	(0x05UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+seto,	setcc_insn,	(0x00UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setob,	setcc_insn,	(0x00UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setp,	setcc_insn,	(0x0AUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setpb,	setcc_insn,	(0x0AUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setpe,	setcc_insn,	(0x0AUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setpeb,	setcc_insn,	(0x0AUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setpo,	setcc_insn,	(0x0BUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setpob,	setcc_insn,	(0x0BUL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+sets,	setcc_insn,	(0x08UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setsb,	setcc_insn,	(0x08UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+setz,	setcc_insn,	(0x04UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setzb,	setcc_insn,	(0x04UL<<8)|NELEMS(setcc_insn),	CPU_386,	SUF_B
+sfence,	threebyte_insn,	(0x0FAEF8UL<<8)|NELEMS(threebyte_insn),	CPU_P3,	NONE
+sgdt,	twobytemem_insn,	(0x000F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	NONE
+sgdtl,	twobytemem_insn,	(0x000F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_L
+sgdtq,	twobytemem_insn,	(0x000F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_Q
+sgdtw,	twobytemem_insn,	(0x000F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_W
+shl,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+shlb,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_B
+shll,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_386,	SUF_L
+shlq,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_64,	SUF_Q
+shlw,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_W
+shld,	shlrd_insn,	(0xA4UL<<8)|NELEMS(shlrd_insn),	CPU_386,	NONE
+shldl,	shlrd_insn,	(0xA4UL<<8)|NELEMS(shlrd_insn),	CPU_386,	SUF_L
+shldq,	shlrd_insn,	(0xA4UL<<8)|NELEMS(shlrd_insn),	CPU_386|CPU_64,	SUF_Q
+shldw,	shlrd_insn,	(0xA4UL<<8)|NELEMS(shlrd_insn),	CPU_386,	SUF_W
+shr,	shift_insn,	(0x05UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+shrb,	shift_insn,	(0x05UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_B
+shrl,	shift_insn,	(0x05UL<<8)|NELEMS(shift_insn),	CPU_386,	SUF_L
+shrq,	shift_insn,	(0x05UL<<8)|NELEMS(shift_insn),	CPU_64,	SUF_Q
+shrw,	shift_insn,	(0x05UL<<8)|NELEMS(shift_insn),	CPU_Any,	SUF_W
+shrd,	shlrd_insn,	(0xACUL<<8)|NELEMS(shlrd_insn),	CPU_386,	NONE
+shrdl,	shlrd_insn,	(0xACUL<<8)|NELEMS(shlrd_insn),	CPU_386,	SUF_L
+shrdq,	shlrd_insn,	(0xACUL<<8)|NELEMS(shlrd_insn),	CPU_386|CPU_64,	SUF_Q
+shrdw,	shlrd_insn,	(0xACUL<<8)|NELEMS(shlrd_insn),	CPU_386,	SUF_W
+shufpd,	ssessimm_insn,	(0x66C6UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+shufps,	ssepsimm_insn,	(0xC6UL<<8)|NELEMS(ssepsimm_insn),	CPU_SSE,	NONE
+sidt,	twobytemem_insn,	(0x010F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	NONE
+sidtl,	twobytemem_insn,	(0x010F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_L
+sidtq,	twobytemem_insn,	(0x010F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_Q
+sidtw,	twobytemem_insn,	(0x010F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	SUF_W
+skinit,	skinit_insn,	(0UL<<8)|NELEMS(skinit_insn),	CPU_SVM,	NONE
+sldt,	sldtmsw_insn,	(0x0000UL<<8)|NELEMS(sldtmsw_insn),	CPU_286,	NONE
+sldtl,	sldtmsw_insn,	(0x0000UL<<8)|NELEMS(sldtmsw_insn),	CPU_386,	SUF_L
+sldtq,	sldtmsw_insn,	(0x0000UL<<8)|NELEMS(sldtmsw_insn),	CPU_286|CPU_64,	SUF_Q
+sldtw,	sldtmsw_insn,	(0x0000UL<<8)|NELEMS(sldtmsw_insn),	CPU_286,	SUF_W
+smi,	onebyte_insn,	(0x0000F1UL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Undoc,	NONE
+smint,	twobyte_insn,	(0x0F38UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_Cyrix,	NONE
+smintold,	twobyte_insn,	(0x0F7EUL<<8)|NELEMS(twobyte_insn),	CPU_486|CPU_Cyrix|CPU_Obs,	NONE
+smovb,	onebyte_insn,	(0x0000A4UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+smovl,	onebyte_insn,	(0x0020A5UL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+smovq,	onebyte_insn,	(0x0040A5UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+smovw,	onebyte_insn,	(0x0010A5UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+smsw,	sldtmsw_insn,	(0x0401UL<<8)|NELEMS(sldtmsw_insn),	CPU_286,	NONE
+smswl,	sldtmsw_insn,	(0x0401UL<<8)|NELEMS(sldtmsw_insn),	CPU_386,	SUF_L
+smswq,	sldtmsw_insn,	(0x0401UL<<8)|NELEMS(sldtmsw_insn),	CPU_286|CPU_64,	SUF_Q
+smsww,	sldtmsw_insn,	(0x0401UL<<8)|NELEMS(sldtmsw_insn),	CPU_286,	SUF_W
+sqrtpd,	ssess_insn,	(0x6651UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+sqrtps,	sseps_insn,	(0x51UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+sqrtsd,	ssess_insn,	(0xF251UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+sqrtss,	ssess_insn,	(0xF351UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+sscab,	onebyte_insn,	(0x0000AEUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+sscal,	onebyte_insn,	(0x0020AFUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+sscaq,	onebyte_insn,	(0x0040AFUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+sscaw,	onebyte_insn,	(0x0010AFUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+stc,	onebyte_insn,	(0x0000F9UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+std,	onebyte_insn,	(0x0000FDUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+stgi,	threebyte_insn,	(0x0F01DCUL<<8)|NELEMS(threebyte_insn),	CPU_SVM,	NONE
+sti,	onebyte_insn,	(0x0000FBUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+stmxcsr,	ldstmxcsr_insn,	(0x03UL<<8)|NELEMS(ldstmxcsr_insn),	CPU_SSE,	NONE
+stosb,	onebyte_insn,	(0x0000AAUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+stosl,	onebyte_insn,	(0x0020ABUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+stosq,	onebyte_insn,	(0x0040ABUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+stosw,	onebyte_insn,	(0x0010ABUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+str,	str_insn,	(0UL<<8)|NELEMS(str_insn),	CPU_286|CPU_Prot,	NONE
+strl,	str_insn,	(0UL<<8)|NELEMS(str_insn),	CPU_386|CPU_Prot,	SUF_L
+strq,	str_insn,	(0UL<<8)|NELEMS(str_insn),	CPU_286|CPU_64|CPU_Prot,	SUF_Q
+strw,	str_insn,	(0UL<<8)|NELEMS(str_insn),	CPU_286|CPU_Prot,	SUF_W
+sub,	arith_insn,	(0x0528UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+subb,	arith_insn,	(0x0528UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_B
+subl,	arith_insn,	(0x0528UL<<8)|NELEMS(arith_insn),	CPU_386,	SUF_L
+subq,	arith_insn,	(0x0528UL<<8)|NELEMS(arith_insn),	CPU_64,	SUF_Q
+subw,	arith_insn,	(0x0528UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_W
+subpd,	ssess_insn,	(0x665CUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+subps,	sseps_insn,	(0x5CUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+subsd,	ssess_insn,	(0xF25CUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+subss,	ssess_insn,	(0xF35CUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+svdc,	svdc_insn,	(0UL<<8)|NELEMS(svdc_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+svldt,	cyrixsmm_insn,	(0x7AUL<<8)|NELEMS(cyrixsmm_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+svts,	cyrixsmm_insn,	(0x7CUL<<8)|NELEMS(cyrixsmm_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+swapgs,	threebyte_insn,	(0x0F01F8UL<<8)|NELEMS(threebyte_insn),	CPU_64,	NONE
+syscall,	twobyte_insn,	(0x0F05UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_AMD,	NONE
+sysenter,	twobyte_insn,	(0x0F34UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_Not64,	NONE
+sysexit,	twobyte_insn,	(0x0F35UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_Not64|CPU_Priv,	NONE
+sysret,	twobyte_insn,	(0x0F07UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_AMD|CPU_Priv,	NONE
+sysretl,	twobyte_insn,	(0x0F07UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_AMD|CPU_Priv,	SUF_L
+sysretq,	twobyte_insn,	(0x0F07UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_AMD|CPU_Priv,	SUF_Q
+test,	test_insn,	(0UL<<8)|NELEMS(test_insn),	CPU_Any,	NONE
+testb,	test_insn,	(0UL<<8)|NELEMS(test_insn),	CPU_Any,	SUF_B
+testl,	test_insn,	(0UL<<8)|NELEMS(test_insn),	CPU_386,	SUF_L
+testq,	test_insn,	(0UL<<8)|NELEMS(test_insn),	CPU_64,	SUF_Q
+testw,	test_insn,	(0UL<<8)|NELEMS(test_insn),	CPU_Any,	SUF_W
+ucomisd,	ssess_insn,	(0x662EUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+ucomiss,	ssess_insn,	(0x002EUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+ud1,	twobyte_insn,	(0x0FB9UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_Undoc,	NONE
+ud2,	twobyte_insn,	(0x0F0BUL<<8)|NELEMS(twobyte_insn),	CPU_286,	NONE
+umov,	umov_insn,	(0UL<<8)|NELEMS(umov_insn),	CPU_386|CPU_Undoc,	NONE
+unpckhpd,	ssess_insn,	(0x6615UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+unpckhps,	sseps_insn,	(0x15UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+unpcklpd,	ssess_insn,	(0x6614UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+unpcklps,	sseps_insn,	(0x14UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+verr,	prot286_insn,	(0x0400UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Prot,	NONE
+verrw,	prot286_insn,	(0x0400UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Prot,	SUF_W
+verw,	prot286_insn,	(0x0500UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Prot,	NONE
+verww,	prot286_insn,	(0x0500UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Prot,	SUF_W
+vmcall,	threebyte_insn,	(0x0F01C1UL<<8)|NELEMS(threebyte_insn),	CPU_P4,	NONE
+vmclear,	vmxthreebytemem_insn,	(0x66UL<<8)|NELEMS(vmxthreebytemem_insn),	CPU_P4,	NONE
+vmlaunch,	threebyte_insn,	(0x0F01C2UL<<8)|NELEMS(threebyte_insn),	CPU_P4,	NONE
+vmload,	svm_rax_insn,	(0xDAUL<<8)|NELEMS(svm_rax_insn),	CPU_SVM,	NONE
+vmmcall,	threebyte_insn,	(0x0F01D9UL<<8)|NELEMS(threebyte_insn),	CPU_SVM,	NONE
+vmptrld,	vmxtwobytemem_insn,	(0x06UL<<8)|NELEMS(vmxtwobytemem_insn),	CPU_P4,	NONE
+vmptrst,	vmxtwobytemem_insn,	(0x07UL<<8)|NELEMS(vmxtwobytemem_insn),	CPU_P4,	NONE
+vmread,	vmxmemrd_insn,	(0UL<<8)|NELEMS(vmxmemrd_insn),	CPU_P4,	NONE
+vmreadl,	vmxmemrd_insn,	(0UL<<8)|NELEMS(vmxmemrd_insn),	CPU_Not64|CPU_P4,	SUF_L
+vmreadq,	vmxmemrd_insn,	(0UL<<8)|NELEMS(vmxmemrd_insn),	CPU_64|CPU_P4,	SUF_Q
+vmresume,	threebyte_insn,	(0x0F01C3UL<<8)|NELEMS(threebyte_insn),	CPU_P4,	NONE
+vmrun,	svm_rax_insn,	(0xD8UL<<8)|NELEMS(svm_rax_insn),	CPU_SVM,	NONE
+vmsave,	svm_rax_insn,	(0xDBUL<<8)|NELEMS(svm_rax_insn),	CPU_SVM,	NONE
+vmwrite,	vmxmemwr_insn,	(0UL<<8)|NELEMS(vmxmemwr_insn),	CPU_P4,	NONE
+vmwritel,	vmxmemwr_insn,	(0UL<<8)|NELEMS(vmxmemwr_insn),	CPU_Not64|CPU_P4,	SUF_L
+vmwriteq,	vmxmemwr_insn,	(0UL<<8)|NELEMS(vmxmemwr_insn),	CPU_64|CPU_P4,	SUF_Q
+vmxoff,	threebyte_insn,	(0x0F01C4UL<<8)|NELEMS(threebyte_insn),	CPU_P4,	NONE
+vmxon,	vmxthreebytemem_insn,	(0xF3UL<<8)|NELEMS(vmxthreebytemem_insn),	CPU_P4,	NONE
+wait,	onebyte_insn,	(0x00009BUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+wbinvd,	twobyte_insn,	(0x0F09UL<<8)|NELEMS(twobyte_insn),	CPU_486|CPU_Priv,	NONE
+word,	NULL,	X86_OPERSIZE,	0x10,	NONE
+wrmsr,	twobyte_insn,	(0x0F30UL<<8)|NELEMS(twobyte_insn),	CPU_586|CPU_Priv,	NONE
+wrshr,	rdwrshr_insn,	(0x01UL<<8)|NELEMS(rdwrshr_insn),	CPU_686|CPU_Cyrix|CPU_SMM,	NONE
+xadd,	cmpxchgxadd_insn,	(0xC0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	NONE
+xaddb,	cmpxchgxadd_insn,	(0xC0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	SUF_B
+xaddl,	cmpxchgxadd_insn,	(0xC0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	SUF_L
+xaddq,	cmpxchgxadd_insn,	(0xC0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486|CPU_64,	SUF_Q
+xaddw,	cmpxchgxadd_insn,	(0xC0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	SUF_W
+xbts,	xbts_insn,	(0UL<<8)|NELEMS(xbts_insn),	CPU_386|CPU_Obs|CPU_Undoc,	NONE
+xchg,	xchg_insn,	(0UL<<8)|NELEMS(xchg_insn),	CPU_Any,	NONE
+xchgb,	xchg_insn,	(0UL<<8)|NELEMS(xchg_insn),	CPU_Any,	SUF_B
+xchgl,	xchg_insn,	(0UL<<8)|NELEMS(xchg_insn),	CPU_Any,	SUF_L
+xchgq,	xchg_insn,	(0UL<<8)|NELEMS(xchg_insn),	CPU_64,	SUF_Q
+xchgw,	xchg_insn,	(0UL<<8)|NELEMS(xchg_insn),	CPU_Any,	SUF_W
+xcryptcbc,	padlock_insn,	(0xD0F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xcryptcfb,	padlock_insn,	(0xE0F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xcryptctr,	padlock_insn,	(0xD8F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xcryptecb,	padlock_insn,	(0xC8F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xcryptofb,	padlock_insn,	(0xE8F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xlatb,	onebyte_insn,	(0x0000D7UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+xor,	arith_insn,	(0x0630UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+xorb,	arith_insn,	(0x0630UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_B
+xorl,	arith_insn,	(0x0630UL<<8)|NELEMS(arith_insn),	CPU_386,	SUF_L
+xorq,	arith_insn,	(0x0630UL<<8)|NELEMS(arith_insn),	CPU_64,	SUF_Q
+xorw,	arith_insn,	(0x0630UL<<8)|NELEMS(arith_insn),	CPU_Any,	SUF_W
+xorpd,	ssess_insn,	(0x6657UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+xorps,	sseps_insn,	(0x57UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+xsha1,	padlock_insn,	(0xC8F3A6UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xsha256,	padlock_insn,	(0xD0F3A6UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xstore,	padlock_insn,	(0xC000A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xstorerng,	padlock_insn,	(0xC000A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
diff --git a/x86insn_nasm.gperf b/x86insn_nasm.gperf
new file mode 100644
index 00000000..6ee3d265
--- /dev/null
+++ b/x86insn_nasm.gperf
@@ -0,0 +1,768 @@
+%ignore-case
+%language=ANSI-C
+%compare-strncmp
+%readonly-tables
+%enum
+%struct-type
+%define hash-function-name insnprefix_nasm_hash
+%define lookup-function-name insnprefix_nasm_find
+struct insnprefix_parse_data;
+%%
+a16,	NULL,	X86_ADDRSIZE,	0x10,	NONE
+a32,	NULL,	X86_ADDRSIZE,	0x20,	NONE
+a64,	NULL,	X86_ADDRSIZE,	0x40,	NONE
+aaa,	onebyte_insn,	(0x000037UL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+aad,	aadm_insn,	(0x01UL<<8)|NELEMS(aadm_insn),	CPU_Not64,	NONE
+aam,	aadm_insn,	(0x00UL<<8)|NELEMS(aadm_insn),	CPU_Not64,	NONE
+aas,	onebyte_insn,	(0x00003FUL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+adc,	arith_insn,	(0x0210UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+add,	arith_insn,	(0x0000UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+addpd,	ssess_insn,	(0x6658UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+addps,	sseps_insn,	(0x58UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+addsd,	ssess_insn,	(0xF258UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+addss,	ssess_insn,	(0xF358UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+addsubpd,	ssess_insn,	(0x66D0UL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+addsubps,	ssess_insn,	(0xF2D0UL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+and,	arith_insn,	(0x0420UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+andnpd,	ssess_insn,	(0x6655UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+andnps,	sseps_insn,	(0x55UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+andpd,	ssess_insn,	(0x6654UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+andps,	sseps_insn,	(0x54UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+arpl,	arpl_insn,	(0UL<<8)|NELEMS(arpl_insn),	CPU_286|CPU_Not64|CPU_Prot,	NONE
+blendpd,	sse4imm_insn,	(0x0DUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+blendps,	sse4imm_insn,	(0x0CUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+blendvpd,	sse4xmm0_insn,	(0x15UL<<8)|NELEMS(sse4xmm0_insn),	CPU_SSE41,	NONE
+blendvps,	sse4xmm0_insn,	(0x14UL<<8)|NELEMS(sse4xmm0_insn),	CPU_SSE41,	NONE
+bound,	bound_insn,	(0UL<<8)|NELEMS(bound_insn),	CPU_186|CPU_Not64,	NONE
+bsf,	bsfr_insn,	(0xBCUL<<8)|NELEMS(bsfr_insn),	CPU_386,	NONE
+bsr,	bsfr_insn,	(0xBDUL<<8)|NELEMS(bsfr_insn),	CPU_386,	NONE
+bswap,	bswap_insn,	(0UL<<8)|NELEMS(bswap_insn),	CPU_486,	NONE
+bt,	bittest_insn,	(0x04A3UL<<8)|NELEMS(bittest_insn),	CPU_386,	NONE
+btc,	bittest_insn,	(0x07BBUL<<8)|NELEMS(bittest_insn),	CPU_386,	NONE
+btr,	bittest_insn,	(0x06B3UL<<8)|NELEMS(bittest_insn),	CPU_386,	NONE
+bts,	bittest_insn,	(0x05ABUL<<8)|NELEMS(bittest_insn),	CPU_386,	NONE
+call,	call_insn,	(0UL<<8)|NELEMS(call_insn),	CPU_Any,	NONE
+cbw,	onebyte_insn,	(0x001098UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cdq,	onebyte_insn,	(0x002099UL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+cdqe,	onebyte_insn,	(0x004098UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+clc,	onebyte_insn,	(0x0000F8UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cld,	onebyte_insn,	(0x0000FCUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+clflush,	clflush_insn,	(0UL<<8)|NELEMS(clflush_insn),	CPU_P3,	NONE
+clgi,	threebyte_insn,	(0x0F01DDUL<<8)|NELEMS(threebyte_insn),	CPU_SVM,	NONE
+cli,	onebyte_insn,	(0x0000FAUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+clts,	twobyte_insn,	(0x0F06UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_Priv,	NONE
+cmc,	onebyte_insn,	(0x0000F5UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cmova,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovae,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovb,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovbe,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovc,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmove,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovg,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovge,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovl,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovle,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovna,	cmovcc_insn,	(0x06UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnae,	cmovcc_insn,	(0x02UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnb,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnbe,	cmovcc_insn,	(0x07UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnc,	cmovcc_insn,	(0x03UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovne,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovng,	cmovcc_insn,	(0x0EUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnge,	cmovcc_insn,	(0x0CUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnl,	cmovcc_insn,	(0x0DUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnle,	cmovcc_insn,	(0x0FUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovno,	cmovcc_insn,	(0x01UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnp,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovns,	cmovcc_insn,	(0x09UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovnz,	cmovcc_insn,	(0x05UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovo,	cmovcc_insn,	(0x00UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovp,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovpe,	cmovcc_insn,	(0x0AUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovpo,	cmovcc_insn,	(0x0BUL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovs,	cmovcc_insn,	(0x08UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmovz,	cmovcc_insn,	(0x04UL<<8)|NELEMS(cmovcc_insn),	CPU_686,	NONE
+cmp,	arith_insn,	(0x0738UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+cmpeqpd,	ssecmpss_insn,	(0x0066UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpeqps,	ssecmpps_insn,	(0x00UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpeqsd,	ssecmpss_insn,	(0x00F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpeqss,	ssecmpss_insn,	(0x00F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmplepd,	ssecmpss_insn,	(0x0266UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpleps,	ssecmpps_insn,	(0x02UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmplesd,	ssecmpss_insn,	(0x02F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpless,	ssecmpss_insn,	(0x02F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpltpd,	ssecmpss_insn,	(0x0166UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpltps,	ssecmpps_insn,	(0x01UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpltsd,	ssecmpss_insn,	(0x01F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpltss,	ssecmpss_insn,	(0x01F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpneqpd,	ssecmpss_insn,	(0x0466UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpneqps,	ssecmpps_insn,	(0x04UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpneqsd,	ssecmpss_insn,	(0x04F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpneqss,	ssecmpss_insn,	(0x04F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpnlepd,	ssecmpss_insn,	(0x0666UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpnleps,	ssecmpps_insn,	(0x06UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpnlesd,	ssecmpss_insn,	(0x06F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpnless,	ssecmpss_insn,	(0x06F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpnltpd,	ssecmpss_insn,	(0x0566UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpnltps,	ssecmpps_insn,	(0x05UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpnltsd,	ssecmpss_insn,	(0x05F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpnltss,	ssecmpss_insn,	(0x05F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpordpd,	ssecmpss_insn,	(0x0766UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpordps,	ssecmpps_insn,	(0x07UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpordsd,	ssecmpss_insn,	(0x07F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpordss,	ssecmpss_insn,	(0x07F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmppd,	ssessimm_insn,	(0x66C2UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+cmpps,	ssepsimm_insn,	(0xC2UL<<8)|NELEMS(ssepsimm_insn),	CPU_SSE,	NONE
+cmpsb,	onebyte_insn,	(0x0000A6UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cmpsd,	cmpsd_insn,	(0UL<<8)|NELEMS(cmpsd_insn),	CPU_Any,	NONE
+cmpsq,	onebyte_insn,	(0x0040A7UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+cmpss,	ssessimm_insn,	(0xF3C2UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE,	NONE
+cmpsw,	onebyte_insn,	(0x0010A7UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cmpunordpd,	ssecmpss_insn,	(0x0366UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpunordps,	ssecmpps_insn,	(0x03UL<<8)|NELEMS(ssecmpps_insn),	CPU_SSE,	NONE
+cmpunordsd,	ssecmpss_insn,	(0x03F2UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE2,	NONE
+cmpunordss,	ssecmpss_insn,	(0x03F3UL<<8)|NELEMS(ssecmpss_insn),	CPU_SSE,	NONE
+cmpxchg,	cmpxchgxadd_insn,	(0xB0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	NONE
+cmpxchg16b,	cmpxchg16b_insn,	(0UL<<8)|NELEMS(cmpxchg16b_insn),	CPU_64,	NONE
+cmpxchg486,	cmpxchgxadd_insn,	(0xA6UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486|CPU_Undoc,	NONE
+cmpxchg8b,	cmpxchg8b_insn,	(0UL<<8)|NELEMS(cmpxchg8b_insn),	CPU_586,	NONE
+comisd,	ssess_insn,	(0x662FUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+comiss,	sseps_insn,	(0x2FUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+cpuid,	twobyte_insn,	(0x0FA2UL<<8)|NELEMS(twobyte_insn),	CPU_486,	NONE
+cqo,	onebyte_insn,	(0x004099UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+crc32,	crc32_insn,	(0UL<<8)|NELEMS(crc32_insn),	CPU_386|CPU_SSE42,	NONE
+cvtdq2pd,	cvt_xmm_xmm64_ss_insn,	(0xF3E6UL<<8)|NELEMS(cvt_xmm_xmm64_ss_insn),	CPU_SSE2,	NONE
+cvtdq2ps,	sseps_insn,	(0x5BUL<<8)|NELEMS(sseps_insn),	CPU_SSE2,	NONE
+cvtpd2dq,	ssess_insn,	(0xF2E6UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvtpd2pi,	cvt_mm_xmm_insn,	(0x662DUL<<8)|NELEMS(cvt_mm_xmm_insn),	CPU_SSE2,	NONE
+cvtpd2ps,	ssess_insn,	(0x665AUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvtpi2pd,	cvt_xmm_mm_ss_insn,	(0x662AUL<<8)|NELEMS(cvt_xmm_mm_ss_insn),	CPU_SSE2,	NONE
+cvtpi2ps,	cvt_xmm_mm_ps_insn,	(0x2AUL<<8)|NELEMS(cvt_xmm_mm_ps_insn),	CPU_SSE,	NONE
+cvtps2dq,	ssess_insn,	(0x665BUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvtps2pd,	cvt_xmm_xmm64_ps_insn,	(0x5AUL<<8)|NELEMS(cvt_xmm_xmm64_ps_insn),	CPU_SSE2,	NONE
+cvtps2pi,	cvt_mm_xmm64_insn,	(0x2DUL<<8)|NELEMS(cvt_mm_xmm64_insn),	CPU_SSE,	NONE
+cvtsd2si,	cvt_rx_xmm64_insn,	(0xF22DUL<<8)|NELEMS(cvt_rx_xmm64_insn),	CPU_386|CPU_SSE2,	NONE
+cvtsd2ss,	cvt_xmm_xmm64_ss_insn,	(0xF25AUL<<8)|NELEMS(cvt_xmm_xmm64_ss_insn),	CPU_SSE2,	NONE
+cvtsi2sd,	cvt_xmm_rmx_insn,	(0xF22AUL<<8)|NELEMS(cvt_xmm_rmx_insn),	CPU_SSE2,	NONE
+cvtsi2ss,	cvt_xmm_rmx_insn,	(0xF32AUL<<8)|NELEMS(cvt_xmm_rmx_insn),	CPU_386|CPU_SSE,	NONE
+cvtss2sd,	cvt_xmm_xmm32_insn,	(0xF35AUL<<8)|NELEMS(cvt_xmm_xmm32_insn),	CPU_SSE2,	NONE
+cvtss2si,	cvt_rx_xmm32_insn,	(0xF32DUL<<8)|NELEMS(cvt_rx_xmm32_insn),	CPU_386|CPU_SSE,	NONE
+cvttpd2dq,	ssess_insn,	(0x66E6UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvttpd2pi,	cvt_mm_xmm_insn,	(0x662CUL<<8)|NELEMS(cvt_mm_xmm_insn),	CPU_SSE2,	NONE
+cvttps2dq,	ssess_insn,	(0xF35BUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+cvttps2pi,	cvt_mm_xmm64_insn,	(0x2CUL<<8)|NELEMS(cvt_mm_xmm64_insn),	CPU_SSE,	NONE
+cvttsd2si,	cvt_rx_xmm64_insn,	(0xF22CUL<<8)|NELEMS(cvt_rx_xmm64_insn),	CPU_SSE2,	NONE
+cvttss2si,	cvt_rx_xmm32_insn,	(0xF32CUL<<8)|NELEMS(cvt_rx_xmm32_insn),	CPU_386|CPU_SSE,	NONE
+cwd,	onebyte_insn,	(0x001099UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+cwde,	onebyte_insn,	(0x002098UL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+daa,	onebyte_insn,	(0x000027UL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+das,	onebyte_insn,	(0x00002FUL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+dec,	incdec_insn,	(0x0148UL<<8)|NELEMS(incdec_insn),	CPU_Any,	NONE
+div,	div_insn,	(0x06UL<<8)|NELEMS(div_insn),	CPU_Any,	NONE
+divpd,	ssess_insn,	(0x665EUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+divps,	sseps_insn,	(0x5EUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+divsd,	ssess_insn,	(0xF25EUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+divss,	ssess_insn,	(0xF35EUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+dppd,	sse4imm_insn,	(0x41UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+dpps,	sse4imm_insn,	(0x40UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+emms,	twobyte_insn,	(0x0F77UL<<8)|NELEMS(twobyte_insn),	CPU_MMX,	NONE
+enter,	enter_insn,	(0UL<<8)|NELEMS(enter_insn),	CPU_186,	NONE
+extractps,	extractps_insn,	(0UL<<8)|NELEMS(extractps_insn),	CPU_386|CPU_SSE41,	NONE
+extrq,	extrq_insn,	(0UL<<8)|NELEMS(extrq_insn),	CPU_SSE41,	NONE
+f2xm1,	twobyte_insn,	(0xD9F0UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fabs,	twobyte_insn,	(0xD9E1UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fadd,	farith_insn,	(0x00C0C0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+faddp,	farithp_insn,	(0xC0UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+fbld,	fbldstp_insn,	(0x04UL<<8)|NELEMS(fbldstp_insn),	CPU_FPU,	NONE
+fbstp,	fbldstp_insn,	(0x06UL<<8)|NELEMS(fbldstp_insn),	CPU_FPU,	NONE
+fchs,	twobyte_insn,	(0xD9E0UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fclex,	threebyte_insn,	(0x9BDBE2UL<<8)|NELEMS(threebyte_insn),	CPU_FPU,	NONE
+fcmovb,	fcmovcc_insn,	(0xDAC0UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovbe,	fcmovcc_insn,	(0xDAD0UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmove,	fcmovcc_insn,	(0xDAC8UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovnb,	fcmovcc_insn,	(0xDBC0UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovnbe,	fcmovcc_insn,	(0xDBD0UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovne,	fcmovcc_insn,	(0xDBC8UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovnu,	fcmovcc_insn,	(0xDBD8UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcmovu,	fcmovcc_insn,	(0xDAD8UL<<8)|NELEMS(fcmovcc_insn),	CPU_686|CPU_FPU,	NONE
+fcom,	fcom_insn,	(0x02D0UL<<8)|NELEMS(fcom_insn),	CPU_FPU,	NONE
+fcomi,	fcom2_insn,	(0xDBF0UL<<8)|NELEMS(fcom2_insn),	CPU_686|CPU_FPU,	NONE
+fcomip,	fcom2_insn,	(0xDFF0UL<<8)|NELEMS(fcom2_insn),	CPU_686|CPU_FPU,	NONE
+fcomp,	fcom_insn,	(0x03D8UL<<8)|NELEMS(fcom_insn),	CPU_FPU,	NONE
+fcompp,	twobyte_insn,	(0xDED9UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fcos,	twobyte_insn,	(0xD9FFUL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fdecstp,	twobyte_insn,	(0xD9F6UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fdiv,	farith_insn,	(0x06F0F8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fdivp,	farithp_insn,	(0xF8UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+fdivr,	farith_insn,	(0x07F8F0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fdivrp,	farithp_insn,	(0xF0UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+femms,	twobyte_insn,	(0x0F0EUL<<8)|NELEMS(twobyte_insn),	CPU_3DNow,	NONE
+ffree,	ffree_insn,	(0xDDUL<<8)|NELEMS(ffree_insn),	CPU_FPU,	NONE
+ffreep,	ffree_insn,	(0xDFUL<<8)|NELEMS(ffree_insn),	CPU_686|CPU_FPU|CPU_Undoc,	NONE
+fiadd,	fiarith_insn,	(0x00DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+ficom,	fiarith_insn,	(0x02DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+ficomp,	fiarith_insn,	(0x03DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fidiv,	fiarith_insn,	(0x06DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fidivr,	fiarith_insn,	(0x07DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fild,	fildstp_insn,	(0x050200UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	NONE
+fimul,	fiarith_insn,	(0x01DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fincstp,	twobyte_insn,	(0xD9F7UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+finit,	threebyte_insn,	(0x9BDBE3UL<<8)|NELEMS(threebyte_insn),	CPU_FPU,	NONE
+fist,	fiarith_insn,	(0x02DBUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fistp,	fildstp_insn,	(0x070203UL<<8)|NELEMS(fildstp_insn),	CPU_FPU,	NONE
+fisttp,	fildstp_insn,	(0x010001UL<<8)|NELEMS(fildstp_insn),	CPU_SSE3,	NONE
+fisub,	fiarith_insn,	(0x04DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fisubr,	fiarith_insn,	(0x05DAUL<<8)|NELEMS(fiarith_insn),	CPU_FPU,	NONE
+fld,	fld_insn,	(0UL<<8)|NELEMS(fld_insn),	CPU_FPU,	NONE
+fld1,	twobyte_insn,	(0xD9E8UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldcw,	fldnstcw_insn,	(0x05UL<<8)|NELEMS(fldnstcw_insn),	CPU_FPU,	NONE
+fldenv,	onebytemem_insn,	(0x04D9UL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	NONE
+fldl2e,	twobyte_insn,	(0xD9EAUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldl2t,	twobyte_insn,	(0xD9E9UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldlg2,	twobyte_insn,	(0xD9ECUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldln2,	twobyte_insn,	(0xD9EDUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldpi,	twobyte_insn,	(0xD9EBUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fldz,	twobyte_insn,	(0xD9EEUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fmul,	farith_insn,	(0x01C8C8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fmulp,	farithp_insn,	(0xC8UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+fnclex,	twobyte_insn,	(0xDBE2UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fninit,	twobyte_insn,	(0xDBE3UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fnop,	twobyte_insn,	(0xD9D0UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fnsave,	onebytemem_insn,	(0x06DDUL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	NONE
+fnstcw,	fldnstcw_insn,	(0x07UL<<8)|NELEMS(fldnstcw_insn),	CPU_FPU,	NONE
+fnstenv,	onebytemem_insn,	(0x06D9UL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	NONE
+fnstsw,	fnstsw_insn,	(0UL<<8)|NELEMS(fnstsw_insn),	CPU_FPU,	NONE
+fpatan,	twobyte_insn,	(0xD9F3UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fprem,	twobyte_insn,	(0xD9F8UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fprem1,	twobyte_insn,	(0xD9F5UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fptan,	twobyte_insn,	(0xD9F2UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+frndint,	twobyte_insn,	(0xD9FCUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+frstor,	onebytemem_insn,	(0x04DDUL<<8)|NELEMS(onebytemem_insn),	CPU_FPU,	NONE
+fsave,	twobytemem_insn,	(0x069BDDUL<<8)|NELEMS(twobytemem_insn),	CPU_FPU,	NONE
+fscale,	twobyte_insn,	(0xD9FDUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fsetpm,	twobyte_insn,	(0xDBE4UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU|CPU_Obs,	NONE
+fsin,	twobyte_insn,	(0xD9FEUL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fsincos,	twobyte_insn,	(0xD9FBUL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fsqrt,	twobyte_insn,	(0xD9FAUL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fst,	fst_insn,	(0UL<<8)|NELEMS(fst_insn),	CPU_FPU,	NONE
+fstcw,	fstcw_insn,	(0UL<<8)|NELEMS(fstcw_insn),	CPU_FPU,	NONE
+fstenv,	twobytemem_insn,	(0x069BD9UL<<8)|NELEMS(twobytemem_insn),	CPU_FPU,	NONE
+fstp,	fstp_insn,	(0UL<<8)|NELEMS(fstp_insn),	CPU_FPU,	NONE
+fstsw,	fstsw_insn,	(0UL<<8)|NELEMS(fstsw_insn),	CPU_FPU,	NONE
+fsub,	farith_insn,	(0x04E0E8UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fsubp,	farithp_insn,	(0xE8UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+fsubr,	farith_insn,	(0x05E8E0UL<<8)|NELEMS(farith_insn),	CPU_FPU,	NONE
+fsubrp,	farithp_insn,	(0xE0UL<<8)|NELEMS(farithp_insn),	CPU_FPU,	NONE
+ftst,	twobyte_insn,	(0xD9E4UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fucom,	fcom2_insn,	(0xDDE0UL<<8)|NELEMS(fcom2_insn),	CPU_286|CPU_FPU,	NONE
+fucomi,	fcom2_insn,	(0xDBE8UL<<8)|NELEMS(fcom2_insn),	CPU_686|CPU_FPU,	NONE
+fucomip,	fcom2_insn,	(0xDFE8UL<<8)|NELEMS(fcom2_insn),	CPU_686|CPU_FPU,	NONE
+fucomp,	fcom2_insn,	(0xDDE8UL<<8)|NELEMS(fcom2_insn),	CPU_286|CPU_FPU,	NONE
+fucompp,	twobyte_insn,	(0xDAE9UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_FPU,	NONE
+fwait,	onebyte_insn,	(0x00009BUL<<8)|NELEMS(onebyte_insn),	CPU_FPU,	NONE
+fxam,	twobyte_insn,	(0xD9E5UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fxch,	fxch_insn,	(0UL<<8)|NELEMS(fxch_insn),	CPU_FPU,	NONE
+fxrstor,	twobytemem_insn,	(0x010FAEUL<<8)|NELEMS(twobytemem_insn),	CPU_686|CPU_FPU,	NONE
+fxsave,	twobytemem_insn,	(0x000FAEUL<<8)|NELEMS(twobytemem_insn),	CPU_686|CPU_FPU,	NONE
+fxtract,	twobyte_insn,	(0xD9F4UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fyl2x,	twobyte_insn,	(0xD9F1UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+fyl2xp1,	twobyte_insn,	(0xD9F9UL<<8)|NELEMS(twobyte_insn),	CPU_FPU,	NONE
+haddpd,	ssess_insn,	(0x667CUL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+haddps,	ssess_insn,	(0xF27CUL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+hlt,	onebyte_insn,	(0x0000F4UL<<8)|NELEMS(onebyte_insn),	CPU_Priv,	NONE
+hsubpd,	ssess_insn,	(0x667DUL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+hsubps,	ssess_insn,	(0xF27DUL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+ibts,	ibts_insn,	(0UL<<8)|NELEMS(ibts_insn),	CPU_386|CPU_Obs|CPU_Undoc,	NONE
+idiv,	div_insn,	(0x07UL<<8)|NELEMS(div_insn),	CPU_Any,	NONE
+imul,	imul_insn,	(0UL<<8)|NELEMS(imul_insn),	CPU_Any,	NONE
+in,	in_insn,	(0UL<<8)|NELEMS(in_insn),	CPU_Any,	NONE
+inc,	incdec_insn,	(0x0040UL<<8)|NELEMS(incdec_insn),	CPU_Any,	NONE
+insb,	onebyte_insn,	(0x00006CUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+insd,	onebyte_insn,	(0x00206DUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+insertps,	insertps_insn,	(0UL<<8)|NELEMS(insertps_insn),	CPU_SSE41,	NONE
+insertq,	insertq_insn,	(0UL<<8)|NELEMS(insertq_insn),	CPU_SSE41,	NONE
+insw,	onebyte_insn,	(0x00106DUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+int,	int_insn,	(0UL<<8)|NELEMS(int_insn),	CPU_Any,	NONE
+int03,	onebyte_insn,	(0x0000CCUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+int3,	onebyte_insn,	(0x0000CCUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+into,	onebyte_insn,	(0x0000CEUL<<8)|NELEMS(onebyte_insn),	CPU_Not64,	NONE
+invd,	twobyte_insn,	(0x0F08UL<<8)|NELEMS(twobyte_insn),	CPU_486|CPU_Priv,	NONE
+invlpg,	twobytemem_insn,	(0x070F01UL<<8)|NELEMS(twobytemem_insn),	CPU_486|CPU_Priv,	NONE
+invlpga,	invlpga_insn,	(0UL<<8)|NELEMS(invlpga_insn),	CPU_SVM,	NONE
+iret,	onebyte_insn,	(0x0000CFUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+iretd,	onebyte_insn,	(0x0020CFUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+iretq,	onebyte_insn,	(0x0040CFUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+iretw,	onebyte_insn,	(0x0010CFUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+ja,	jcc_insn,	(0x07UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jae,	jcc_insn,	(0x03UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jb,	jcc_insn,	(0x02UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jbe,	jcc_insn,	(0x06UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jc,	jcc_insn,	(0x02UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jcxz,	jcxz_insn,	(0x10UL<<8)|NELEMS(jcxz_insn),	CPU_Any,	NONE
+je,	jcc_insn,	(0x04UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jecxz,	jcxz_insn,	(0x20UL<<8)|NELEMS(jcxz_insn),	CPU_386,	NONE
+jg,	jcc_insn,	(0x0FUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jge,	jcc_insn,	(0x0DUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jl,	jcc_insn,	(0x0CUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jle,	jcc_insn,	(0x0EUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jmp,	jmp_insn,	(0UL<<8)|NELEMS(jmp_insn),	CPU_Any,	NONE
+jna,	jcc_insn,	(0x06UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnae,	jcc_insn,	(0x02UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnb,	jcc_insn,	(0x03UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnbe,	jcc_insn,	(0x07UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnc,	jcc_insn,	(0x03UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jne,	jcc_insn,	(0x05UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jng,	jcc_insn,	(0x0EUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnge,	jcc_insn,	(0x0CUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnl,	jcc_insn,	(0x0DUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnle,	jcc_insn,	(0x0FUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jno,	jcc_insn,	(0x01UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnp,	jcc_insn,	(0x0BUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jns,	jcc_insn,	(0x09UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jnz,	jcc_insn,	(0x05UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jo,	jcc_insn,	(0x00UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jp,	jcc_insn,	(0x0AUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jpe,	jcc_insn,	(0x0AUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jpo,	jcc_insn,	(0x0BUL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jrcxz,	jcxz_insn,	(0x40UL<<8)|NELEMS(jcxz_insn),	CPU_64,	NONE
+js,	jcc_insn,	(0x08UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+jz,	jcc_insn,	(0x04UL<<8)|NELEMS(jcc_insn),	CPU_Any,	NONE
+lahf,	onebyte_insn,	(0x00009FUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+lar,	bsfr_insn,	(0x02UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	NONE
+lddqu,	lddqu_insn,	(0UL<<8)|NELEMS(lddqu_insn),	CPU_SSE3,	NONE
+ldmxcsr,	ldstmxcsr_insn,	(0x02UL<<8)|NELEMS(ldstmxcsr_insn),	CPU_SSE,	NONE
+lds,	ldes_insn,	(0xC5UL<<8)|NELEMS(ldes_insn),	CPU_Not64,	NONE
+lea,	lea_insn,	(0UL<<8)|NELEMS(lea_insn),	CPU_Any,	NONE
+leave,	onebyte_insn,	(0x4000C9UL<<8)|NELEMS(onebyte_insn),	CPU_186,	NONE
+les,	ldes_insn,	(0xC4UL<<8)|NELEMS(ldes_insn),	CPU_Not64,	NONE
+lfence,	threebyte_insn,	(0x0FAEE8UL<<8)|NELEMS(threebyte_insn),	CPU_P3,	NONE
+lfs,	lfgss_insn,	(0xB4UL<<8)|NELEMS(lfgss_insn),	CPU_386,	NONE
+lgdt,	twobytemem_insn,	(0x020F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	NONE
+lgs,	lfgss_insn,	(0xB5UL<<8)|NELEMS(lfgss_insn),	CPU_386,	NONE
+lidt,	twobytemem_insn,	(0x030F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	NONE
+lldt,	prot286_insn,	(0x0200UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Priv|CPU_Prot,	NONE
+lmsw,	prot286_insn,	(0x0601UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Priv,	NONE
+loadall,	twobyte_insn,	(0x0F07UL<<8)|NELEMS(twobyte_insn),	CPU_386|CPU_Undoc,	NONE
+loadall286,	twobyte_insn,	(0x0F05UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_Undoc,	NONE
+lock,	NULL,	X86_LOCKREP,	0xF0,	NONE
+lodsb,	onebyte_insn,	(0x0000ACUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+lodsd,	onebyte_insn,	(0x0020ADUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+lodsq,	onebyte_insn,	(0x0040ADUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+lodsw,	onebyte_insn,	(0x0010ADUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+loop,	loop_insn,	(0x02UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+loope,	loop_insn,	(0x01UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+loopne,	loop_insn,	(0x00UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+loopnz,	loop_insn,	(0x00UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+loopz,	loop_insn,	(0x01UL<<8)|NELEMS(loop_insn),	CPU_Any,	NONE
+lsl,	bsfr_insn,	(0x03UL<<8)|NELEMS(bsfr_insn),	CPU_286|CPU_Prot,	NONE
+lss,	lfgss_insn,	(0xB2UL<<8)|NELEMS(lfgss_insn),	CPU_386,	NONE
+ltr,	prot286_insn,	(0x0300UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Priv|CPU_Prot,	NONE
+lzcnt,	cnt_insn,	(0xBDUL<<8)|NELEMS(cnt_insn),	CPU_686|CPU_AMD,	NONE
+maskmovdqu,	maskmovdqu_insn,	(0UL<<8)|NELEMS(maskmovdqu_insn),	CPU_SSE2,	NONE
+maskmovq,	maskmovq_insn,	(0UL<<8)|NELEMS(maskmovq_insn),	CPU_MMX|CPU_P3,	NONE
+maxpd,	ssess_insn,	(0x665FUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+maxps,	sseps_insn,	(0x5FUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+maxsd,	ssess_insn,	(0xF25FUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+maxss,	ssess_insn,	(0xF35FUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+mfence,	threebyte_insn,	(0x0FAEF0UL<<8)|NELEMS(threebyte_insn),	CPU_P3,	NONE
+minpd,	ssess_insn,	(0x665DUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+minps,	sseps_insn,	(0x5DUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+minsd,	ssess_insn,	(0xF25DUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+minss,	ssess_insn,	(0xF35DUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+monitor,	threebyte_insn,	(0x0F01C8UL<<8)|NELEMS(threebyte_insn),	CPU_SSE3,	NONE
+montmul,	padlock_insn,	(0xC0F3A6UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+mov,	mov_insn,	(0UL<<8)|NELEMS(mov_insn),	CPU_Any,	NONE
+movapd,	movaupd_insn,	(0x28UL<<8)|NELEMS(movaupd_insn),	CPU_SSE2,	NONE
+movaps,	movaups_insn,	(0x28UL<<8)|NELEMS(movaups_insn),	CPU_SSE,	NONE
+movd,	movd_insn,	(0UL<<8)|NELEMS(movd_insn),	CPU_386|CPU_MMX,	NONE
+movddup,	cvt_xmm_xmm64_ss_insn,	(0xF212UL<<8)|NELEMS(cvt_xmm_xmm64_ss_insn),	CPU_SSE3,	NONE
+movdq2q,	movdq2q_insn,	(0UL<<8)|NELEMS(movdq2q_insn),	CPU_SSE2,	NONE
+movdqa,	movdqau_insn,	(0x66UL<<8)|NELEMS(movdqau_insn),	CPU_SSE2,	NONE
+movdqu,	movdqau_insn,	(0xF3UL<<8)|NELEMS(movdqau_insn),	CPU_SSE2,	NONE
+movhlps,	movhllhps_insn,	(0x12UL<<8)|NELEMS(movhllhps_insn),	CPU_SSE,	NONE
+movhpd,	movhlpd_insn,	(0x16UL<<8)|NELEMS(movhlpd_insn),	CPU_SSE2,	NONE
+movhps,	movhlps_insn,	(0x16UL<<8)|NELEMS(movhlps_insn),	CPU_SSE,	NONE
+movlhps,	movhllhps_insn,	(0x16UL<<8)|NELEMS(movhllhps_insn),	CPU_SSE,	NONE
+movlpd,	movhlpd_insn,	(0x12UL<<8)|NELEMS(movhlpd_insn),	CPU_SSE2,	NONE
+movlps,	movhlps_insn,	(0x12UL<<8)|NELEMS(movhlps_insn),	CPU_SSE,	NONE
+movmskpd,	movmskpd_insn,	(0UL<<8)|NELEMS(movmskpd_insn),	CPU_386|CPU_SSE2,	NONE
+movmskps,	movmskps_insn,	(0UL<<8)|NELEMS(movmskps_insn),	CPU_386|CPU_SSE,	NONE
+movntdq,	movntpddq_insn,	(0xE7UL<<8)|NELEMS(movntpddq_insn),	CPU_SSE2,	NONE
+movntdqa,	movntdqa_insn,	(0UL<<8)|NELEMS(movntdqa_insn),	CPU_SSE41,	NONE
+movnti,	movnti_insn,	(0UL<<8)|NELEMS(movnti_insn),	CPU_P4,	NONE
+movntpd,	movntpddq_insn,	(0x2BUL<<8)|NELEMS(movntpddq_insn),	CPU_SSE2,	NONE
+movntps,	movntps_insn,	(0UL<<8)|NELEMS(movntps_insn),	CPU_SSE,	NONE
+movntq,	movntq_insn,	(0UL<<8)|NELEMS(movntq_insn),	CPU_SSE,	NONE
+movntsd,	movntsd_insn,	(0UL<<8)|NELEMS(movntsd_insn),	CPU_SSE41,	NONE
+movntss,	movntss_insn,	(0UL<<8)|NELEMS(movntss_insn),	CPU_SSE41,	NONE
+movq,	movq_insn,	(0UL<<8)|NELEMS(movq_insn),	CPU_MMX,	NONE
+movq2dq,	movq2dq_insn,	(0UL<<8)|NELEMS(movq2dq_insn),	CPU_SSE2,	NONE
+movsb,	onebyte_insn,	(0x0000A4UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+movsd,	movsd_insn,	(0UL<<8)|NELEMS(movsd_insn),	CPU_386,	NONE
+movshdup,	ssess_insn,	(0xF316UL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+movsldup,	ssess_insn,	(0xF312UL<<8)|NELEMS(ssess_insn),	CPU_SSE3,	NONE
+movsq,	onebyte_insn,	(0x0040A5UL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+movss,	movss_insn,	(0UL<<8)|NELEMS(movss_insn),	CPU_SSE,	NONE
+movsw,	onebyte_insn,	(0x0010A5UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+movsx,	movszx_insn,	(0xBEUL<<8)|NELEMS(movszx_insn),	CPU_386,	NONE
+movsxd,	movsxd_insn,	(0UL<<8)|NELEMS(movsxd_insn),	CPU_64,	NONE
+movupd,	movaupd_insn,	(0x10UL<<8)|NELEMS(movaupd_insn),	CPU_SSE2,	NONE
+movups,	movaups_insn,	(0x10UL<<8)|NELEMS(movaups_insn),	CPU_SSE,	NONE
+movzx,	movszx_insn,	(0xB6UL<<8)|NELEMS(movszx_insn),	CPU_386,	NONE
+mpsadbw,	sse4imm_insn,	(0x42UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+mul,	f6_insn,	(0x04UL<<8)|NELEMS(f6_insn),	CPU_Any,	NONE
+mulpd,	ssess_insn,	(0x6659UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+mulps,	sseps_insn,	(0x59UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+mulsd,	ssess_insn,	(0xF259UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+mulss,	ssess_insn,	(0xF359UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+mwait,	threebyte_insn,	(0x0F01C9UL<<8)|NELEMS(threebyte_insn),	CPU_SSE3,	NONE
+neg,	f6_insn,	(0x03UL<<8)|NELEMS(f6_insn),	CPU_Any,	NONE
+nop,	onebyte_insn,	(0x000090UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+not,	f6_insn,	(0x02UL<<8)|NELEMS(f6_insn),	CPU_Any,	NONE
+o16,	NULL,	X86_OPERSIZE,	0x10,	NONE
+o32,	NULL,	X86_OPERSIZE,	0x20,	NONE
+o64,	NULL,	X86_OPERSIZE,	0x40,	NONE
+or,	arith_insn,	(0x0108UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+orpd,	ssess_insn,	(0x6656UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+orps,	sseps_insn,	(0x56UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+out,	out_insn,	(0UL<<8)|NELEMS(out_insn),	CPU_Any,	NONE
+outsb,	onebyte_insn,	(0x00006EUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+outsd,	onebyte_insn,	(0x00206FUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+outsw,	onebyte_insn,	(0x00106FUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+pabsb,	ssse3_insn,	(0x1CUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pabsd,	ssse3_insn,	(0x1EUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pabsw,	ssse3_insn,	(0x1DUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+packssdw,	mmxsse2_insn,	(0x6BUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+packsswb,	mmxsse2_insn,	(0x63UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+packusdw,	sse4_insn,	(0x2BUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+packuswb,	mmxsse2_insn,	(0x67UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddb,	mmxsse2_insn,	(0xFCUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddd,	mmxsse2_insn,	(0xFEUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddq,	mmxsse2_insn,	(0xD4UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddsb,	mmxsse2_insn,	(0xECUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddsiw,	cyrixmmx_insn,	(0x51UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+paddsw,	mmxsse2_insn,	(0xEDUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddusb,	mmxsse2_insn,	(0xDCUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddusw,	mmxsse2_insn,	(0xDDUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+paddw,	mmxsse2_insn,	(0xFDUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+palignr,	ssse3imm_insn,	(0x0FUL<<8)|NELEMS(ssse3imm_insn),	CPU_SSSE3,	NONE
+pand,	mmxsse2_insn,	(0xDBUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pandn,	mmxsse2_insn,	(0xDFUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pause,	onebyte_prefix_insn,	(0xF390UL<<8)|NELEMS(onebyte_prefix_insn),	CPU_P4,	NONE
+paveb,	cyrixmmx_insn,	(0x50UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pavgb,	mmxsse2_insn,	(0xE0UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pavgusb,	now3d_insn,	(0xBFUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pavgw,	mmxsse2_insn,	(0xE3UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pblendvb,	sse4xmm0_insn,	(0x10UL<<8)|NELEMS(sse4xmm0_insn),	CPU_SSE41,	NONE
+pblendw,	sse4imm_insn,	(0x0EUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+pcmpeqb,	mmxsse2_insn,	(0x74UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpeqd,	mmxsse2_insn,	(0x76UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpeqq,	sse4_insn,	(0x29UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pcmpeqw,	mmxsse2_insn,	(0x75UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpestri,	sse4pcmpstr_insn,	(0x61UL<<8)|NELEMS(sse4pcmpstr_insn),	CPU_SSE42,	NONE
+pcmpestrm,	sse4pcmpstr_insn,	(0x60UL<<8)|NELEMS(sse4pcmpstr_insn),	CPU_SSE42,	NONE
+pcmpgtb,	mmxsse2_insn,	(0x64UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpgtd,	mmxsse2_insn,	(0x66UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpgtq,	sse4_insn,	(0x37UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pcmpgtw,	mmxsse2_insn,	(0x65UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pcmpistri,	sse4pcmpstr_insn,	(0x63UL<<8)|NELEMS(sse4pcmpstr_insn),	CPU_SSE42,	NONE
+pcmpistrm,	sse4pcmpstr_insn,	(0x62UL<<8)|NELEMS(sse4pcmpstr_insn),	CPU_SSE42,	NONE
+pdistib,	cyrixmmx_insn,	(0x54UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pextrb,	pextrb_insn,	(0UL<<8)|NELEMS(pextrb_insn),	CPU_SSE41,	NONE
+pextrd,	pextrd_insn,	(0UL<<8)|NELEMS(pextrd_insn),	CPU_386|CPU_SSE41,	NONE
+pextrq,	pextrq_insn,	(0UL<<8)|NELEMS(pextrq_insn),	CPU_64|CPU_SSE41,	NONE
+pextrw,	pextrw_insn,	(0UL<<8)|NELEMS(pextrw_insn),	CPU_MMX|CPU_P3,	NONE
+pf2id,	now3d_insn,	(0x1DUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pf2iw,	now3d_insn,	(0x1CUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+pfacc,	now3d_insn,	(0xAEUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfadd,	now3d_insn,	(0x9EUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfcmpeq,	now3d_insn,	(0xB0UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfcmpge,	now3d_insn,	(0x90UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfcmpgt,	now3d_insn,	(0xA0UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfmax,	now3d_insn,	(0xA4UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfmin,	now3d_insn,	(0x94UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfmul,	now3d_insn,	(0xB4UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfnacc,	now3d_insn,	(0x8AUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+pfpnacc,	now3d_insn,	(0x8EUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+pfrcp,	now3d_insn,	(0x96UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfrcpit1,	now3d_insn,	(0xA6UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfrcpit2,	now3d_insn,	(0xB6UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfrsqit1,	now3d_insn,	(0xA7UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfrsqrt,	now3d_insn,	(0x97UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfsub,	now3d_insn,	(0x9AUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pfsubr,	now3d_insn,	(0xAAUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+phaddd,	ssse3_insn,	(0x02UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phaddsw,	ssse3_insn,	(0x03UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phaddw,	ssse3_insn,	(0x01UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phminposuw,	sse4_insn,	(0x41UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+phsubd,	ssse3_insn,	(0x06UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phsubsw,	ssse3_insn,	(0x07UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+phsubw,	ssse3_insn,	(0x05UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pi2fd,	now3d_insn,	(0x0DUL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pi2fw,	now3d_insn,	(0x0CUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+pinsrb,	pinsrb_insn,	(0UL<<8)|NELEMS(pinsrb_insn),	CPU_SSE41,	NONE
+pinsrd,	pinsrd_insn,	(0UL<<8)|NELEMS(pinsrd_insn),	CPU_386|CPU_SSE41,	NONE
+pinsrq,	pinsrq_insn,	(0UL<<8)|NELEMS(pinsrq_insn),	CPU_64|CPU_SSE41,	NONE
+pinsrw,	pinsrw_insn,	(0UL<<8)|NELEMS(pinsrw_insn),	CPU_MMX|CPU_P3,	NONE
+pmachriw,	pmachriw_insn,	(0UL<<8)|NELEMS(pmachriw_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmaddubsw,	ssse3_insn,	(0x04UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pmaddwd,	mmxsse2_insn,	(0xF5UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pmagw,	cyrixmmx_insn,	(0x52UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmaxsb,	sse4_insn,	(0x3CUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmaxsd,	sse4_insn,	(0x3DUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmaxsw,	mmxsse2_insn,	(0xEEUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pmaxub,	mmxsse2_insn,	(0xDEUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pmaxud,	sse4_insn,	(0x3FUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmaxuw,	sse4_insn,	(0x3EUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pminsb,	sse4_insn,	(0x38UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pminsd,	sse4_insn,	(0x39UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pminsw,	mmxsse2_insn,	(0xEAUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pminub,	mmxsse2_insn,	(0xDAUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pminud,	sse4_insn,	(0x3BUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pminuw,	sse4_insn,	(0x3AUL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmovmskb,	pmovmskb_insn,	(0UL<<8)|NELEMS(pmovmskb_insn),	CPU_MMX|CPU_P3,	NONE
+pmovsxbd,	sse4m32_insn,	(0x21UL<<8)|NELEMS(sse4m32_insn),	CPU_SSE41,	NONE
+pmovsxbq,	sse4m16_insn,	(0x22UL<<8)|NELEMS(sse4m16_insn),	CPU_SSE41,	NONE
+pmovsxbw,	sse4m64_insn,	(0x20UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovsxdq,	sse4m64_insn,	(0x25UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovsxwd,	sse4m64_insn,	(0x23UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovsxwq,	sse4m32_insn,	(0x24UL<<8)|NELEMS(sse4m32_insn),	CPU_SSE41,	NONE
+pmovzxbd,	sse4m32_insn,	(0x31UL<<8)|NELEMS(sse4m32_insn),	CPU_SSE41,	NONE
+pmovzxbq,	sse4m16_insn,	(0x32UL<<8)|NELEMS(sse4m16_insn),	CPU_SSE41,	NONE
+pmovzxbw,	sse4m64_insn,	(0x30UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovzxdq,	sse4m64_insn,	(0x35UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovzxwd,	sse4m64_insn,	(0x33UL<<8)|NELEMS(sse4m64_insn),	CPU_SSE41,	NONE
+pmovzxwq,	sse4m32_insn,	(0x34UL<<8)|NELEMS(sse4m32_insn),	CPU_SSE41,	NONE
+pmuldq,	sse4_insn,	(0x28UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmulhriw,	cyrixmmx_insn,	(0x5DUL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmulhrsw,	ssse3_insn,	(0x0BUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pmulhrwa,	now3d_insn,	(0xB7UL<<8)|NELEMS(now3d_insn),	CPU_3DNow,	NONE
+pmulhrwc,	cyrixmmx_insn,	(0x59UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmulhuw,	mmxsse2_insn,	(0xE4UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pmulhw,	mmxsse2_insn,	(0xE5UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pmulld,	sse4_insn,	(0x40UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+pmullw,	mmxsse2_insn,	(0xD5UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pmuludq,	mmxsse2_insn,	(0xF4UL<<8)|NELEMS(mmxsse2_insn),	CPU_SSE2,	NONE
+pmvgezb,	cyrixmmx_insn,	(0x5CUL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmvlzb,	cyrixmmx_insn,	(0x5BUL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmvnzb,	cyrixmmx_insn,	(0x5AUL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pmvzb,	cyrixmmx_insn,	(0x58UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+pop,	pop_insn,	(0UL<<8)|NELEMS(pop_insn),	CPU_Any,	NONE
+popa,	onebyte_insn,	(0x000061UL<<8)|NELEMS(onebyte_insn),	CPU_186|CPU_Not64,	NONE
+popad,	onebyte_insn,	(0x002061UL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Not64,	NONE
+popaw,	onebyte_insn,	(0x001061UL<<8)|NELEMS(onebyte_insn),	CPU_186|CPU_Not64,	NONE
+popcnt,	cnt_insn,	(0xB8UL<<8)|NELEMS(cnt_insn),	CPU_SSE42,	NONE
+popf,	onebyte_insn,	(0x40009DUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+popfd,	onebyte_insn,	(0x00209DUL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Not64,	NONE
+popfq,	onebyte_insn,	(0x40409DUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+popfw,	onebyte_insn,	(0x40109DUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+por,	mmxsse2_insn,	(0xEBUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+prefetch,	twobytemem_insn,	(0x000F0DUL<<8)|NELEMS(twobytemem_insn),	CPU_3DNow,	NONE
+prefetchnta,	twobytemem_insn,	(0x000F18UL<<8)|NELEMS(twobytemem_insn),	CPU_P3,	NONE
+prefetcht0,	twobytemem_insn,	(0x010F18UL<<8)|NELEMS(twobytemem_insn),	CPU_P3,	NONE
+prefetcht1,	twobytemem_insn,	(0x020F18UL<<8)|NELEMS(twobytemem_insn),	CPU_P3,	NONE
+prefetcht2,	twobytemem_insn,	(0x030F18UL<<8)|NELEMS(twobytemem_insn),	CPU_P3,	NONE
+prefetchw,	twobytemem_insn,	(0x010F0DUL<<8)|NELEMS(twobytemem_insn),	CPU_3DNow,	NONE
+psadbw,	mmxsse2_insn,	(0xF6UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX|CPU_P3,	NONE
+pshufb,	ssse3_insn,	(0x00UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pshufd,	ssessimm_insn,	(0x6670UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+pshufhw,	ssessimm_insn,	(0xF370UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+pshuflw,	ssessimm_insn,	(0xF270UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+pshufw,	pshufw_insn,	(0UL<<8)|NELEMS(pshufw_insn),	CPU_MMX|CPU_P3,	NONE
+psignb,	ssse3_insn,	(0x08UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+psignd,	ssse3_insn,	(0x0AUL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+psignw,	ssse3_insn,	(0x09UL<<8)|NELEMS(ssse3_insn),	CPU_SSSE3,	NONE
+pslld,	pshift_insn,	(0x0672F2UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+pslldq,	pslrldq_insn,	(0x07UL<<8)|NELEMS(pslrldq_insn),	CPU_SSE2,	NONE
+psllq,	pshift_insn,	(0x0673F3UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psllw,	pshift_insn,	(0x0671F1UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psrad,	pshift_insn,	(0x0472E2UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psraw,	pshift_insn,	(0x0471E1UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psrld,	pshift_insn,	(0x0272D2UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psrldq,	pslrldq_insn,	(0x03UL<<8)|NELEMS(pslrldq_insn),	CPU_SSE2,	NONE
+psrlq,	pshift_insn,	(0x0273D3UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psrlw,	pshift_insn,	(0x0271D1UL<<8)|NELEMS(pshift_insn),	CPU_MMX,	NONE
+psubb,	mmxsse2_insn,	(0xF8UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubd,	mmxsse2_insn,	(0xFAUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubq,	mmxsse2_insn,	(0xFBUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubsb,	mmxsse2_insn,	(0xE8UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubsiw,	cyrixmmx_insn,	(0x55UL<<8)|NELEMS(cyrixmmx_insn),	CPU_Cyrix|CPU_MMX,	NONE
+psubsw,	mmxsse2_insn,	(0xE9UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubusb,	mmxsse2_insn,	(0xD8UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubusw,	mmxsse2_insn,	(0xD9UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+psubw,	mmxsse2_insn,	(0xF9UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+pswapd,	now3d_insn,	(0xBBUL<<8)|NELEMS(now3d_insn),	CPU_3DNow|CPU_Athlon,	NONE
+ptest,	sse4_insn,	(0x17UL<<8)|NELEMS(sse4_insn),	CPU_SSE41,	NONE
+punpckhbw,	mmxsse2_insn,	(0x68UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpckhdq,	mmxsse2_insn,	(0x6AUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpckhqdq,	ssess_insn,	(0x666DUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+punpckhwd,	mmxsse2_insn,	(0x69UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpcklbw,	mmxsse2_insn,	(0x60UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpckldq,	mmxsse2_insn,	(0x62UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+punpcklqdq,	ssess_insn,	(0x666CUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+punpcklwd,	mmxsse2_insn,	(0x61UL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+push,	push_insn,	(0UL<<8)|NELEMS(push_insn),	CPU_Any,	NONE
+pusha,	onebyte_insn,	(0x000060UL<<8)|NELEMS(onebyte_insn),	CPU_186|CPU_Not64,	NONE
+pushad,	onebyte_insn,	(0x002060UL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Not64,	NONE
+pushaw,	onebyte_insn,	(0x001060UL<<8)|NELEMS(onebyte_insn),	CPU_186|CPU_Not64,	NONE
+pushf,	onebyte_insn,	(0x40009CUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+pushfd,	onebyte_insn,	(0x00209CUL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Not64,	NONE
+pushfq,	onebyte_insn,	(0x40409CUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+pushfw,	onebyte_insn,	(0x40109CUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+pxor,	mmxsse2_insn,	(0xEFUL<<8)|NELEMS(mmxsse2_insn),	CPU_MMX,	NONE
+rcl,	shift_insn,	(0x02UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+rcpps,	sseps_insn,	(0x53UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+rcpss,	ssess_insn,	(0xF353UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+rcr,	shift_insn,	(0x03UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+rdmsr,	twobyte_insn,	(0x0F32UL<<8)|NELEMS(twobyte_insn),	CPU_586|CPU_Priv,	NONE
+rdpmc,	twobyte_insn,	(0x0F33UL<<8)|NELEMS(twobyte_insn),	CPU_686,	NONE
+rdshr,	rdwrshr_insn,	(0x00UL<<8)|NELEMS(rdwrshr_insn),	CPU_686|CPU_Cyrix|CPU_SMM,	NONE
+rdtsc,	twobyte_insn,	(0x0F31UL<<8)|NELEMS(twobyte_insn),	CPU_586,	NONE
+rdtscp,	threebyte_insn,	(0x0F01F9UL<<8)|NELEMS(threebyte_insn),	CPU_686|CPU_AMD|CPU_Priv,	NONE
+rep,	NULL,	X86_LOCKREP,	0xF3,	NONE
+repe,	NULL,	X86_LOCKREP,	0xF3,	NONE
+repne,	NULL,	X86_LOCKREP,	0xF2,	NONE
+repnz,	NULL,	X86_LOCKREP,	0xF2,	NONE
+repz,	NULL,	X86_LOCKREP,	0xF3,	NONE
+ret,	retnf_insn,	(0x00C2UL<<8)|NELEMS(retnf_insn),	CPU_Any,	NONE
+retf,	retnf_insn,	(0x40CAUL<<8)|NELEMS(retnf_insn),	CPU_Any,	NONE
+retn,	retnf_insn,	(0x00C2UL<<8)|NELEMS(retnf_insn),	CPU_Any,	NONE
+rol,	shift_insn,	(0x00UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+ror,	shift_insn,	(0x01UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+roundpd,	sse4imm_insn,	(0x09UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+roundps,	sse4imm_insn,	(0x08UL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+roundsd,	sse4imm_insn,	(0x0BUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+roundss,	sse4imm_insn,	(0x0AUL<<8)|NELEMS(sse4imm_insn),	CPU_SSE41,	NONE
+rsdc,	rsdc_insn,	(0UL<<8)|NELEMS(rsdc_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+rsldt,	cyrixsmm_insn,	(0x7BUL<<8)|NELEMS(cyrixsmm_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+rsm,	twobyte_insn,	(0x0FAAUL<<8)|NELEMS(twobyte_insn),	CPU_586|CPU_SMM,	NONE
+rsqrtps,	sseps_insn,	(0x52UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+rsqrtss,	ssess_insn,	(0xF352UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+rsts,	cyrixsmm_insn,	(0x7DUL<<8)|NELEMS(cyrixsmm_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+sahf,	onebyte_insn,	(0x00009EUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+sal,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+salc,	onebyte_insn,	(0x0000D6UL<<8)|NELEMS(onebyte_insn),	CPU_Not64|CPU_Undoc,	NONE
+sar,	shift_insn,	(0x07UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+sbb,	arith_insn,	(0x0318UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+scasb,	onebyte_insn,	(0x0000AEUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+scasd,	onebyte_insn,	(0x0020AFUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+scasq,	onebyte_insn,	(0x0040AFUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+scasw,	onebyte_insn,	(0x0010AFUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+seta,	setcc_insn,	(0x07UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setae,	setcc_insn,	(0x03UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setb,	setcc_insn,	(0x02UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setbe,	setcc_insn,	(0x06UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setc,	setcc_insn,	(0x02UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+sete,	setcc_insn,	(0x04UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setg,	setcc_insn,	(0x0FUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setge,	setcc_insn,	(0x0DUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setl,	setcc_insn,	(0x0CUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setle,	setcc_insn,	(0x0EUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setna,	setcc_insn,	(0x06UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnae,	setcc_insn,	(0x02UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnb,	setcc_insn,	(0x03UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnbe,	setcc_insn,	(0x07UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnc,	setcc_insn,	(0x03UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setne,	setcc_insn,	(0x05UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setng,	setcc_insn,	(0x0EUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnge,	setcc_insn,	(0x0CUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnl,	setcc_insn,	(0x0DUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnle,	setcc_insn,	(0x0FUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setno,	setcc_insn,	(0x01UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnp,	setcc_insn,	(0x0BUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setns,	setcc_insn,	(0x09UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setnz,	setcc_insn,	(0x05UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+seto,	setcc_insn,	(0x00UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setp,	setcc_insn,	(0x0AUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setpe,	setcc_insn,	(0x0AUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setpo,	setcc_insn,	(0x0BUL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+sets,	setcc_insn,	(0x08UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+setz,	setcc_insn,	(0x04UL<<8)|NELEMS(setcc_insn),	CPU_386,	NONE
+sfence,	threebyte_insn,	(0x0FAEF8UL<<8)|NELEMS(threebyte_insn),	CPU_P3,	NONE
+sgdt,	twobytemem_insn,	(0x000F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	NONE
+shl,	shift_insn,	(0x04UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+shld,	shlrd_insn,	(0xA4UL<<8)|NELEMS(shlrd_insn),	CPU_386,	NONE
+shr,	shift_insn,	(0x05UL<<8)|NELEMS(shift_insn),	CPU_Any,	NONE
+shrd,	shlrd_insn,	(0xACUL<<8)|NELEMS(shlrd_insn),	CPU_386,	NONE
+shufpd,	ssessimm_insn,	(0x66C6UL<<8)|NELEMS(ssessimm_insn),	CPU_SSE2,	NONE
+shufps,	ssepsimm_insn,	(0xC6UL<<8)|NELEMS(ssepsimm_insn),	CPU_SSE,	NONE
+sidt,	twobytemem_insn,	(0x010F01UL<<8)|NELEMS(twobytemem_insn),	CPU_286|CPU_Priv,	NONE
+skinit,	skinit_insn,	(0UL<<8)|NELEMS(skinit_insn),	CPU_SVM,	NONE
+sldt,	sldtmsw_insn,	(0x0000UL<<8)|NELEMS(sldtmsw_insn),	CPU_286,	NONE
+smi,	onebyte_insn,	(0x0000F1UL<<8)|NELEMS(onebyte_insn),	CPU_386|CPU_Undoc,	NONE
+smint,	twobyte_insn,	(0x0F38UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_Cyrix,	NONE
+smintold,	twobyte_insn,	(0x0F7EUL<<8)|NELEMS(twobyte_insn),	CPU_486|CPU_Cyrix|CPU_Obs,	NONE
+smsw,	sldtmsw_insn,	(0x0401UL<<8)|NELEMS(sldtmsw_insn),	CPU_286,	NONE
+sqrtpd,	ssess_insn,	(0x6651UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+sqrtps,	sseps_insn,	(0x51UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+sqrtsd,	ssess_insn,	(0xF251UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+sqrtss,	ssess_insn,	(0xF351UL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+stc,	onebyte_insn,	(0x0000F9UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+std,	onebyte_insn,	(0x0000FDUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+stgi,	threebyte_insn,	(0x0F01DCUL<<8)|NELEMS(threebyte_insn),	CPU_SVM,	NONE
+sti,	onebyte_insn,	(0x0000FBUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+stmxcsr,	ldstmxcsr_insn,	(0x03UL<<8)|NELEMS(ldstmxcsr_insn),	CPU_SSE,	NONE
+stosb,	onebyte_insn,	(0x0000AAUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+stosd,	onebyte_insn,	(0x0020ABUL<<8)|NELEMS(onebyte_insn),	CPU_386,	NONE
+stosq,	onebyte_insn,	(0x0040ABUL<<8)|NELEMS(onebyte_insn),	CPU_64,	NONE
+stosw,	onebyte_insn,	(0x0010ABUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+str,	str_insn,	(0UL<<8)|NELEMS(str_insn),	CPU_286|CPU_Prot,	NONE
+sub,	arith_insn,	(0x0528UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+subpd,	ssess_insn,	(0x665CUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+subps,	sseps_insn,	(0x5CUL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+subsd,	ssess_insn,	(0xF25CUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+subss,	ssess_insn,	(0xF35CUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+svdc,	svdc_insn,	(0UL<<8)|NELEMS(svdc_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+svldt,	cyrixsmm_insn,	(0x7AUL<<8)|NELEMS(cyrixsmm_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+svts,	cyrixsmm_insn,	(0x7CUL<<8)|NELEMS(cyrixsmm_insn),	CPU_486|CPU_Cyrix|CPU_SMM,	NONE
+swapgs,	threebyte_insn,	(0x0F01F8UL<<8)|NELEMS(threebyte_insn),	CPU_64,	NONE
+syscall,	twobyte_insn,	(0x0F05UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_AMD,	NONE
+sysenter,	twobyte_insn,	(0x0F34UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_Not64,	NONE
+sysexit,	twobyte_insn,	(0x0F35UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_Not64|CPU_Priv,	NONE
+sysret,	twobyte_insn,	(0x0F07UL<<8)|NELEMS(twobyte_insn),	CPU_686|CPU_AMD|CPU_Priv,	NONE
+test,	test_insn,	(0UL<<8)|NELEMS(test_insn),	CPU_Any,	NONE
+ucomisd,	ssess_insn,	(0x662EUL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+ucomiss,	ssess_insn,	(0x002EUL<<8)|NELEMS(ssess_insn),	CPU_SSE,	NONE
+ud1,	twobyte_insn,	(0x0FB9UL<<8)|NELEMS(twobyte_insn),	CPU_286|CPU_Undoc,	NONE
+ud2,	twobyte_insn,	(0x0F0BUL<<8)|NELEMS(twobyte_insn),	CPU_286,	NONE
+umov,	umov_insn,	(0UL<<8)|NELEMS(umov_insn),	CPU_386|CPU_Undoc,	NONE
+unpckhpd,	ssess_insn,	(0x6615UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+unpckhps,	sseps_insn,	(0x15UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+unpcklpd,	ssess_insn,	(0x6614UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+unpcklps,	sseps_insn,	(0x14UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+verr,	prot286_insn,	(0x0400UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Prot,	NONE
+verw,	prot286_insn,	(0x0500UL<<8)|NELEMS(prot286_insn),	CPU_286|CPU_Prot,	NONE
+vmcall,	threebyte_insn,	(0x0F01C1UL<<8)|NELEMS(threebyte_insn),	CPU_P4,	NONE
+vmclear,	vmxthreebytemem_insn,	(0x66UL<<8)|NELEMS(vmxthreebytemem_insn),	CPU_P4,	NONE
+vmlaunch,	threebyte_insn,	(0x0F01C2UL<<8)|NELEMS(threebyte_insn),	CPU_P4,	NONE
+vmload,	svm_rax_insn,	(0xDAUL<<8)|NELEMS(svm_rax_insn),	CPU_SVM,	NONE
+vmmcall,	threebyte_insn,	(0x0F01D9UL<<8)|NELEMS(threebyte_insn),	CPU_SVM,	NONE
+vmptrld,	vmxtwobytemem_insn,	(0x06UL<<8)|NELEMS(vmxtwobytemem_insn),	CPU_P4,	NONE
+vmptrst,	vmxtwobytemem_insn,	(0x07UL<<8)|NELEMS(vmxtwobytemem_insn),	CPU_P4,	NONE
+vmread,	vmxmemrd_insn,	(0UL<<8)|NELEMS(vmxmemrd_insn),	CPU_P4,	NONE
+vmresume,	threebyte_insn,	(0x0F01C3UL<<8)|NELEMS(threebyte_insn),	CPU_P4,	NONE
+vmrun,	svm_rax_insn,	(0xD8UL<<8)|NELEMS(svm_rax_insn),	CPU_SVM,	NONE
+vmsave,	svm_rax_insn,	(0xDBUL<<8)|NELEMS(svm_rax_insn),	CPU_SVM,	NONE
+vmwrite,	vmxmemwr_insn,	(0UL<<8)|NELEMS(vmxmemwr_insn),	CPU_P4,	NONE
+vmxoff,	threebyte_insn,	(0x0F01C4UL<<8)|NELEMS(threebyte_insn),	CPU_P4,	NONE
+vmxon,	vmxthreebytemem_insn,	(0xF3UL<<8)|NELEMS(vmxthreebytemem_insn),	CPU_P4,	NONE
+wait,	onebyte_insn,	(0x00009BUL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+wbinvd,	twobyte_insn,	(0x0F09UL<<8)|NELEMS(twobyte_insn),	CPU_486|CPU_Priv,	NONE
+wrmsr,	twobyte_insn,	(0x0F30UL<<8)|NELEMS(twobyte_insn),	CPU_586|CPU_Priv,	NONE
+wrshr,	rdwrshr_insn,	(0x01UL<<8)|NELEMS(rdwrshr_insn),	CPU_686|CPU_Cyrix|CPU_SMM,	NONE
+xadd,	cmpxchgxadd_insn,	(0xC0UL<<8)|NELEMS(cmpxchgxadd_insn),	CPU_486,	NONE
+xbts,	xbts_insn,	(0UL<<8)|NELEMS(xbts_insn),	CPU_386|CPU_Obs|CPU_Undoc,	NONE
+xchg,	xchg_insn,	(0UL<<8)|NELEMS(xchg_insn),	CPU_Any,	NONE
+xcryptcbc,	padlock_insn,	(0xD0F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xcryptcfb,	padlock_insn,	(0xE0F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xcryptctr,	padlock_insn,	(0xD8F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xcryptecb,	padlock_insn,	(0xC8F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xcryptofb,	padlock_insn,	(0xE8F3A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xlatb,	onebyte_insn,	(0x0000D7UL<<8)|NELEMS(onebyte_insn),	CPU_Any,	NONE
+xor,	arith_insn,	(0x0630UL<<8)|NELEMS(arith_insn),	CPU_Any,	NONE
+xorpd,	ssess_insn,	(0x6657UL<<8)|NELEMS(ssess_insn),	CPU_SSE2,	NONE
+xorps,	sseps_insn,	(0x57UL<<8)|NELEMS(sseps_insn),	CPU_SSE,	NONE
+xsha1,	padlock_insn,	(0xC8F3A6UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xsha256,	padlock_insn,	(0xD0F3A6UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xstore,	padlock_insn,	(0xC000A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
+xstorerng,	padlock_insn,	(0xC000A7UL<<8)|NELEMS(padlock_insn),	CPU_PadLock,	NONE
diff --git a/x86insns.c b/x86insns.c
new file mode 100644
index 00000000..240e4a0e
--- /dev/null
+++ b/x86insns.c
@@ -0,0 +1,1104 @@
+static const x86_insn_info onebyte_insn[] = {
+    { CPU_Any, MOD_Op0Add|MOD_OpSizeR|MOD_DOpS64R, 0, 0, 0, 1, {0x00, 0, 0}, 0, 0, {0, 0, 0} }
+};
+
+static const x86_insn_info onebyte_prefix_insn[] = {
+    { CPU_Any, MOD_Op0Add|MOD_PreAdd, 0, 0, 0x00, 1, {0x00, 0, 0}, 0, 0, {0, 0, 0} }
+};
+
+static const x86_insn_info twobyte_insn[] = {
+    { CPU_Any, MOD_Op1Add|MOD_Op0Add|MOD_GasSufL|MOD_GasSufQ, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 0, {0, 0, 0} }
+};
+
+static const x86_insn_info threebyte_insn[] = {
+    { CPU_Any, MOD_Op2Add|MOD_Op1Add|MOD_Op0Add, 0, 0, 0, 3, {0x00, 0x00, 0x00}, 0, 0, {0, 0, 0} }
+};
+
+static const x86_insn_info onebytemem_insn[] = {
+    { CPU_Any, MOD_Op0Add|MOD_SpAdd|MOD_GasSufL|MOD_GasSufQ|MOD_GasSufS, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_Mem|OPS_Any|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info twobytemem_insn[] = {
+    { CPU_Any, MOD_Op1Add|MOD_Op0Add|MOD_SpAdd|MOD_GasSufL|MOD_GasSufQ|MOD_GasSufS|MOD_GasSufW, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, {OPT_Mem|OPS_Any|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info mov_insn[] = {
+    { CPU_Not64, MOD_GasSufB, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, {OPT_Areg|OPS_8|OPA_None, OPT_MemOffs|OPS_8|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_Not64, MOD_GasSufW, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, {OPT_Areg|OPS_16|OPA_None, OPT_MemOffs|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_None, OPT_MemOffs|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_Not64, MOD_GasSufB, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, {OPT_MemOffs|OPS_8|OPS_Relaxed|OPA_EA, OPT_Areg|OPS_8|OPA_None, 0} },
+    { CPU_Not64, MOD_GasSufW, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, {OPT_MemOffs|OPS_16|OPS_Relaxed|OPA_EA, OPT_Areg|OPS_16|OPA_None, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, {OPT_MemOffs|OPS_32|OPS_Relaxed|OPA_EA, OPT_Areg|OPS_32|OPA_None, 0} },
+    { CPU_64, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, {OPT_Areg|OPS_8|OPA_None, OPT_MemOffs|OPS_8|OPS_Relaxed|OPEAS_64|OPA_EA, 0} },
+    { CPU_64, 0, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, {OPT_Areg|OPS_16|OPA_None, OPT_MemOffs|OPS_16|OPS_Relaxed|OPEAS_64|OPA_EA, 0} },
+    { CPU_64, 0, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_None, OPT_MemOffs|OPS_32|OPS_Relaxed|OPEAS_64|OPA_EA, 0} },
+    { CPU_64, 0, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, {OPT_Areg|OPS_64|OPA_None, OPT_MemOffs|OPS_64|OPS_Relaxed|OPEAS_64|OPA_EA, 0} },
+    { CPU_64, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, {OPT_MemOffs|OPS_8|OPS_Relaxed|OPEAS_64|OPA_EA, OPT_Areg|OPS_8|OPA_None, 0} },
+    { CPU_64, 0, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, {OPT_MemOffs|OPS_16|OPS_Relaxed|OPEAS_64|OPA_EA, OPT_Areg|OPS_16|OPA_None, 0} },
+    { CPU_64, 0, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, {OPT_MemOffs|OPS_32|OPS_Relaxed|OPEAS_64|OPA_EA, OPT_Areg|OPS_32|OPA_None, 0} },
+    { CPU_64, 0, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, {OPT_MemOffs|OPS_64|OPS_Relaxed|OPEAS_64|OPA_EA, OPT_Areg|OPS_64|OPA_None, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA|OPAP_ShortMov, OPT_Areg|OPS_8|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA|OPAP_ShortMov, OPT_Areg|OPS_16|OPA_Spare, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA|OPAP_ShortMov, OPT_Areg|OPS_32|OPA_Spare, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA|OPAP_ShortMov, OPT_Areg|OPS_64|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_8|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x89, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x89, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x89, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, {OPT_Areg|OPS_8|OPA_Spare, OPT_RM|OPS_8|OPS_Relaxed|OPA_EA|OPAP_ShortMov, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, {OPT_Areg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA|OPAP_ShortMov, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA|OPAP_ShortMov, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, {OPT_Areg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA|OPAP_ShortMov, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, {OPT_Reg|OPS_8|OPA_Spare, OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x8B, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x8B, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x8B, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_Any, MOD_GasSufW, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, {OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x8C, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_EA, OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x8C, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_EA, OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x8C, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_EA, OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufW, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, {OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386, MOD_GasSufL, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, {OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, OPT_Reg|OPS_32|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufQ, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, {OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, OPT_Reg|OPS_64|OPA_EA, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, {OPT_Reg|OPS_8|OPA_Op0Add, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xB8, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Op0Add, OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xB8, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Op0Add, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_64, MOD_GasIllegal, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Op0Add, OPT_Imm|OPS_64|OPA_Imm, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Op0Add, OPT_Imm|OPS_64|OPS_Relaxed|OPA_Imm|OPAP_SImm32Avail, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_16|OPA_Imm, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_32|OPA_Imm, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_32|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPA_EA, OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPA_EA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPA_EA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_586|CPU_Not64|CPU_Priv, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, {OPT_CR4|OPS_32|OPA_Spare, OPT_Reg|OPS_32|OPA_EA, 0} },
+    { CPU_386|CPU_Not64|CPU_Priv, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, {OPT_CRReg|OPS_32|OPA_Spare, OPT_Reg|OPS_32|OPA_EA, 0} },
+    { CPU_64|CPU_Priv, MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, {OPT_CRReg|OPS_32|OPA_Spare, OPT_Reg|OPS_64|OPA_EA, 0} },
+    { CPU_586|CPU_Not64|CPU_Priv, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_EA, OPT_CR4|OPS_32|OPA_Spare, 0} },
+    { CPU_386|CPU_Not64|CPU_Priv, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_EA, OPT_CRReg|OPS_32|OPA_Spare, 0} },
+    { CPU_64|CPU_Priv, MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_EA, OPT_CRReg|OPS_32|OPA_Spare, 0} },
+    { CPU_386|CPU_Not64|CPU_Priv, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, {OPT_DRReg|OPS_32|OPA_Spare, OPT_Reg|OPS_32|OPA_EA, 0} },
+    { CPU_64|CPU_Priv, MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, {OPT_DRReg|OPS_32|OPA_Spare, OPT_Reg|OPS_64|OPA_EA, 0} },
+    { CPU_386|CPU_Not64|CPU_Priv, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_EA, OPT_DRReg|OPS_32|OPA_Spare, 0} },
+    { CPU_64|CPU_Priv, MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_EA, OPT_DRReg|OPS_32|OPA_Spare, 0} },
+    { CPU_MMX, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_MMX, MOD_GasOnly|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_MMX, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, {OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} },
+    { CPU_64|CPU_MMX, MOD_GasOnly|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} },
+    { CPU_SSE2, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_SSE2, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_SSE2, MOD_GasOnly|MOD_GasSufQ, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE2, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, {OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} },
+    { CPU_64|CPU_SSE2, MOD_GasOnly|MOD_GasSufQ, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movabs_insn[] = {
+    { CPU_64, MOD_GasSufB, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, {OPT_Areg|OPS_8|OPA_None, OPT_MemOffs|OPS_8|OPS_Relaxed|OPEAS_64|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufW, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, {OPT_Areg|OPS_16|OPA_None, OPT_MemOffs|OPS_16|OPS_Relaxed|OPEAS_64|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufL, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_None, OPT_MemOffs|OPS_32|OPS_Relaxed|OPEAS_64|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, {OPT_Areg|OPS_64|OPA_None, OPT_MemOffs|OPS_64|OPS_Relaxed|OPEAS_64|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufB, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, {OPT_MemOffs|OPS_8|OPS_Relaxed|OPEAS_64|OPA_EA, OPT_Areg|OPS_8|OPA_None, 0} },
+    { CPU_64, MOD_GasSufW, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, {OPT_MemOffs|OPS_16|OPS_Relaxed|OPEAS_64|OPA_EA, OPT_Areg|OPS_16|OPA_None, 0} },
+    { CPU_64, MOD_GasSufL, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, {OPT_MemOffs|OPS_32|OPS_Relaxed|OPEAS_64|OPA_EA, OPT_Areg|OPS_32|OPA_None, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, {OPT_MemOffs|OPS_64|OPS_Relaxed|OPEAS_64|OPA_EA, OPT_Areg|OPS_64|OPA_None, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Op0Add, OPT_Imm|OPS_64|OPS_Relaxed|OPA_Imm, 0} }
+};
+
+static const x86_insn_info movszx_insn[] = {
+    { CPU_386, MOD_Op1Add|MOD_GasSufB, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386, MOD_Op1Add|MOD_GasSufB, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_8|OPA_EA, 0} },
+    { CPU_64, MOD_Op1Add|MOD_GasSufB, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_8|OPA_EA, 0} },
+    { CPU_386, MOD_Op1Add|MOD_GasSufW, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_16|OPA_EA, 0} },
+    { CPU_64, MOD_Op1Add|MOD_GasSufW, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_16|OPA_EA, 0} }
+};
+
+static const x86_insn_info movsxd_insn[] = {
+    { CPU_64, MOD_GasSufL, 64, 0, 0, 1, {0x63, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_32|OPA_EA, 0} }
+};
+
+static const x86_insn_info push_insn[] = {
+    { CPU_Any, MOD_GasSufW, 16, 64, 0, 1, {0x50, 0, 0}, 0, 1, {OPT_Reg|OPS_16|OPA_Op0Add, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0x50, 0, 0}, 0, 1, {OPT_Reg|OPS_32|OPA_Op0Add, 0, 0} },
+    { CPU_64, MOD_GasSufQ, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, {OPT_Reg|OPS_64|OPA_Op0Add, 0, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 64, 0, 1, {0xFF, 0, 0}, 6, 1, {OPT_RM|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0xFF, 0, 0}, 6, 1, {OPT_RM|OPS_32|OPA_EA, 0, 0} },
+    { CPU_64, MOD_GasSufQ, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, {OPT_RM|OPS_64|OPA_EA, 0, 0} },
+    { CPU_186, MOD_GasIllegal, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPA_SImm, 0, 0} },
+    { CPU_186, MOD_GasOnly, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_SImm, 0, 0} },
+    { CPU_186, MOD_GasOnly|MOD_GasSufW, 16, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm|OPAP_SImm8, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasOnly|MOD_GasSufL, 32, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, {OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm|OPAP_SImm8, 0, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, {OPT_Imm|OPS_32|OPS_Relaxed|OPA_SImm|OPAP_SImm8, 0, 0} },
+    { CPU_186|CPU_Not64, MOD_GasIllegal, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, {OPT_Imm|OPS_BITS|OPS_Relaxed|OPA_Imm|OPAP_SImm8, 0, 0} },
+    { CPU_186, MOD_GasIllegal, 16, 64, 0, 1, {0x68, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPA_Imm, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasIllegal, 32, 0, 0, 1, {0x68, 0, 0}, 0, 1, {OPT_Imm|OPS_32|OPA_Imm, 0, 0} },
+    { CPU_64, MOD_GasIllegal, 64, 64, 0, 1, {0x68, 0, 0}, 0, 1, {OPT_Imm|OPS_32|OPA_SImm, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, {OPT_CS|OPS_Any|OPA_None, 0, 0} },
+    { CPU_Not64, MOD_GasSufW, 16, 0, 0, 1, {0x0E, 0, 0}, 0, 1, {OPT_CS|OPS_16|OPA_None, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0x0E, 0, 0}, 0, 1, {OPT_CS|OPS_32|OPA_None, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, {OPT_SS|OPS_Any|OPA_None, 0, 0} },
+    { CPU_Not64, MOD_GasSufW, 16, 0, 0, 1, {0x16, 0, 0}, 0, 1, {OPT_SS|OPS_16|OPA_None, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0x16, 0, 0}, 0, 1, {OPT_SS|OPS_32|OPA_None, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, {OPT_DS|OPS_Any|OPA_None, 0, 0} },
+    { CPU_Not64, MOD_GasSufW, 16, 0, 0, 1, {0x1E, 0, 0}, 0, 1, {OPT_DS|OPS_16|OPA_None, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0x1E, 0, 0}, 0, 1, {OPT_DS|OPS_32|OPA_None, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, {OPT_ES|OPS_Any|OPA_None, 0, 0} },
+    { CPU_Not64, MOD_GasSufW, 16, 0, 0, 1, {0x06, 0, 0}, 0, 1, {OPT_ES|OPS_16|OPA_None, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0x06, 0, 0}, 0, 1, {OPT_ES|OPS_32|OPA_None, 0, 0} },
+    { CPU_386, 0, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, {OPT_FS|OPS_Any|OPA_None, 0, 0} },
+    { CPU_386, MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, {OPT_FS|OPS_16|OPA_None, 0, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, {OPT_FS|OPS_32|OPA_None, 0, 0} },
+    { CPU_386, 0, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, {OPT_GS|OPS_Any|OPA_None, 0, 0} },
+    { CPU_386, MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, {OPT_GS|OPS_16|OPA_None, 0, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, {OPT_GS|OPS_32|OPA_None, 0, 0} }
+};
+
+static const x86_insn_info pop_insn[] = {
+    { CPU_Any, MOD_GasSufW, 16, 64, 0, 1, {0x58, 0, 0}, 0, 1, {OPT_Reg|OPS_16|OPA_Op0Add, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0x58, 0, 0}, 0, 1, {OPT_Reg|OPS_32|OPA_Op0Add, 0, 0} },
+    { CPU_64, MOD_GasSufQ, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, {OPT_Reg|OPS_64|OPA_Op0Add, 0, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 64, 0, 1, {0x8F, 0, 0}, 0, 1, {OPT_RM|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0x8F, 0, 0}, 0, 1, {OPT_RM|OPS_32|OPA_EA, 0, 0} },
+    { CPU_64, MOD_GasSufQ, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, {OPT_RM|OPS_64|OPA_EA, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, {OPT_SS|OPS_Any|OPA_None, 0, 0} },
+    { CPU_Not64, 0, 16, 0, 0, 1, {0x17, 0, 0}, 0, 1, {OPT_SS|OPS_16|OPA_None, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0x17, 0, 0}, 0, 1, {OPT_SS|OPS_32|OPA_None, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, {OPT_DS|OPS_Any|OPA_None, 0, 0} },
+    { CPU_Not64, 0, 16, 0, 0, 1, {0x1F, 0, 0}, 0, 1, {OPT_DS|OPS_16|OPA_None, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0x1F, 0, 0}, 0, 1, {OPT_DS|OPS_32|OPA_None, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, {OPT_ES|OPS_Any|OPA_None, 0, 0} },
+    { CPU_Not64, 0, 16, 0, 0, 1, {0x07, 0, 0}, 0, 1, {OPT_ES|OPS_16|OPA_None, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0x07, 0, 0}, 0, 1, {OPT_ES|OPS_32|OPA_None, 0, 0} },
+    { CPU_386, 0, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, {OPT_FS|OPS_Any|OPA_None, 0, 0} },
+    { CPU_386, 0, 16, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, {OPT_FS|OPS_16|OPA_None, 0, 0} },
+    { CPU_386, 0, 32, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, {OPT_FS|OPS_32|OPA_None, 0, 0} },
+    { CPU_386, 0, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, {OPT_GS|OPS_Any|OPA_None, 0, 0} },
+    { CPU_386, 0, 16, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, {OPT_GS|OPS_16|OPA_None, 0, 0} },
+    { CPU_386, 0, 32, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, {OPT_GS|OPS_32|OPA_None, 0, 0} }
+};
+
+static const x86_insn_info xchg_insn[] = {
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_8|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, {OPT_Reg|OPS_8|OPA_Spare, OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, {OPT_Areg|OPS_16|OPA_None, OPT_Reg|OPS_16|OPA_Op0Add, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Op0Add, OPT_Areg|OPS_16|OPA_None, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufL, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_EA, OPT_Areg|OPS_32|OPA_Spare, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_None, OPT_Reg|OPS_32|OPA_Op0Add, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Op0Add, OPT_Areg|OPS_32|OPA_None, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufQ, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, {OPT_Areg|OPS_64|OPA_None, OPT_Areg|OPS_64|OPA_Op0Add, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, {OPT_Areg|OPS_64|OPA_None, OPT_Reg|OPS_64|OPA_Op0Add, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Op0Add, OPT_Areg|OPS_64|OPA_None, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info in_insn[] = {
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, {OPT_Areg|OPS_8|OPA_None, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 2, {OPT_Areg|OPS_16|OPA_None, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_None, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, {OPT_Areg|OPS_8|OPA_None, OPT_Dreg|OPS_16|OPA_None, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xED, 0, 0}, 0, 2, {OPT_Areg|OPS_16|OPA_None, OPT_Dreg|OPS_16|OPA_None, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xED, 0, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_None, OPT_Dreg|OPS_16|OPA_None, 0} },
+    { CPU_Any, MOD_GasOnly|MOD_GasSufB, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0, 0} },
+    { CPU_Any, MOD_GasOnly|MOD_GasSufW, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0, 0} },
+    { CPU_386, MOD_GasOnly|MOD_GasSufL, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0, 0} },
+    { CPU_Any, MOD_GasOnly|MOD_GasSufB, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, {OPT_Dreg|OPS_16|OPA_None, 0, 0} },
+    { CPU_Any, MOD_GasOnly|MOD_GasSufW, 16, 0, 0, 1, {0xED, 0, 0}, 0, 1, {OPT_Dreg|OPS_16|OPA_None, 0, 0} },
+    { CPU_386, MOD_GasOnly|MOD_GasSufL, 32, 0, 0, 1, {0xED, 0, 0}, 0, 1, {OPT_Dreg|OPS_16|OPA_None, 0, 0} }
+};
+
+static const x86_insn_info out_insn[] = {
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, OPT_Areg|OPS_8|OPA_None, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 2, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, OPT_Areg|OPS_16|OPA_None, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 2, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, OPT_Areg|OPS_32|OPA_None, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, {OPT_Dreg|OPS_16|OPA_None, OPT_Areg|OPS_8|OPA_None, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 2, {OPT_Dreg|OPS_16|OPA_None, OPT_Areg|OPS_16|OPA_None, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 2, {OPT_Dreg|OPS_16|OPA_None, OPT_Areg|OPS_32|OPA_None, 0} },
+    { CPU_Any, MOD_GasOnly|MOD_GasSufB, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0, 0} },
+    { CPU_Any, MOD_GasOnly|MOD_GasSufW, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0, 0} },
+    { CPU_386, MOD_GasOnly|MOD_GasSufL, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0, 0} },
+    { CPU_Any, MOD_GasOnly|MOD_GasSufB, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, {OPT_Dreg|OPS_16|OPA_None, 0, 0} },
+    { CPU_Any, MOD_GasOnly|MOD_GasSufW, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 1, {OPT_Dreg|OPS_16|OPA_None, 0, 0} },
+    { CPU_386, MOD_GasOnly|MOD_GasSufL, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 1, {OPT_Dreg|OPS_16|OPA_None, 0, 0} }
+};
+
+static const x86_insn_info lea_insn[] = {
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x8D, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x8D, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x8D, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info ldes_insn[] = {
+    { CPU_Not64, MOD_Op0Add|MOD_GasSufW, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_Mem|OPS_Any|OPA_EA, 0} },
+    { CPU_386|CPU_Not64, MOD_Op0Add|MOD_GasSufL, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_Mem|OPS_Any|OPA_EA, 0} }
+};
+
+static const x86_insn_info lfgss_insn[] = {
+    { CPU_386, MOD_Op1Add|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_Mem|OPS_Any|OPA_EA, 0} },
+    { CPU_386, MOD_Op1Add|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_Mem|OPS_Any|OPA_EA, 0} }
+};
+
+static const x86_insn_info arith_insn[] = {
+    { CPU_Any, MOD_Op0Add|MOD_GasSufB, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, {OPT_Areg|OPS_8|OPA_None, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_Op2Add|MOD_Op1AddSp|MOD_GasSufW, 16, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, {OPT_Areg|OPS_16|OPA_None, OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm|OPAP_SImm8, 0} },
+    { CPU_386, MOD_Op2Add|MOD_Op1AddSp|MOD_GasSufL, 32, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, {OPT_Areg|OPS_32|OPA_None, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm|OPAP_SImm8, 0} },
+    { CPU_64, MOD_Op2Add|MOD_Op1AddSp|MOD_GasSufQ, 64, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, {OPT_Areg|OPS_64|OPA_None, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm|OPAP_SImm8, 0} },
+    { CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPA_Imm, 0} },
+    { CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0x83, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPA_EA, OPT_Imm|OPS_8|OPA_SImm, 0} },
+    { CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasIllegal, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_16|OPA_Imm|OPAP_SImm8, 0} },
+    { CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, {OPT_RM|OPS_16|OPA_EA, OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm|OPAP_SImm8, 0} },
+    { CPU_386, MOD_Gap0|MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0x83, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPA_EA, OPT_Imm|OPS_8|OPA_SImm, 0} },
+    { CPU_386|CPU_Not64, MOD_Gap0|MOD_SpAdd|MOD_GasIllegal, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_32|OPA_Imm|OPAP_SImm8, 0} },
+    { CPU_386, MOD_Gap0|MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, {OPT_RM|OPS_32|OPA_EA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm|OPAP_SImm8, 0} },
+    { CPU_64, MOD_Gap0|MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1, {0x83, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPA_EA, OPT_Imm|OPS_8|OPA_SImm, 0} },
+    { CPU_64, MOD_Gap0|MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, {OPT_RM|OPS_64|OPA_EA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm|OPAP_SImm8, 0} },
+    { CPU_Any, MOD_Op0Add|MOD_GasSufB, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_8|OPA_Spare, 0} },
+    { CPU_Any, MOD_Op0Add|MOD_GasSufW, 16, 0, 0, 1, {0x01, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} },
+    { CPU_386, MOD_Op0Add|MOD_GasSufL, 32, 0, 0, 1, {0x01, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_64, MOD_Op0Add|MOD_GasSufQ, 64, 0, 0, 1, {0x01, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, 0} },
+    { CPU_Any, MOD_Op0Add|MOD_GasSufB, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, {OPT_Reg|OPS_8|OPA_Spare, OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_Any, MOD_Op0Add|MOD_GasSufW, 16, 0, 0, 1, {0x03, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386, MOD_Op0Add|MOD_GasSufL, 32, 0, 0, 1, {0x03, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64, MOD_Op0Add|MOD_GasSufQ, 64, 0, 0, 1, {0x03, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info incdec_insn[] = {
+    { CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, {OPT_RM|OPS_8|OPA_EA, 0, 0} },
+    { CPU_Not64, MOD_Op0Add|MOD_GasSufW, 16, 0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_Reg|OPS_16|OPA_Op0Add, 0, 0} },
+    { CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, {OPT_RM|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_Op0Add|MOD_GasSufL, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_Reg|OPS_32|OPA_Op0Add, 0, 0} },
+    { CPU_386, MOD_Gap0|MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, {OPT_RM|OPS_32|OPA_EA, 0, 0} },
+    { CPU_64, MOD_Gap0|MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, {OPT_RM|OPS_64|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info f6_insn[] = {
+    { CPU_Any, MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, {OPT_RM|OPS_8|OPA_EA, 0, 0} },
+    { CPU_Any, MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, {OPT_RM|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386, MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, {OPT_RM|OPS_32|OPA_EA, 0, 0} },
+    { CPU_64, MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, {OPT_RM|OPS_64|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info div_insn[] = {
+    { CPU_Any, MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, {OPT_RM|OPS_8|OPA_EA, 0, 0} },
+    { CPU_Any, MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, {OPT_RM|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386, MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, {OPT_RM|OPS_32|OPA_EA, 0, 0} },
+    { CPU_64, MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, {OPT_RM|OPS_64|OPA_EA, 0, 0} },
+    { CPU_Any, MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, {OPT_Areg|OPS_8|OPA_None, OPT_RM|OPS_8|OPA_EA, 0} },
+    { CPU_Any, MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, {OPT_Areg|OPS_16|OPA_None, OPT_RM|OPS_16|OPA_EA, 0} },
+    { CPU_386, MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_None, OPT_RM|OPS_32|OPA_EA, 0} },
+    { CPU_64, MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, {OPT_Areg|OPS_64|OPA_None, OPT_RM|OPS_64|OPA_EA, 0} }
+};
+
+static const x86_insn_info test_insn[] = {
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, {OPT_Areg|OPS_8|OPA_None, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xA9, 0, 0}, 0, 2, {OPT_Areg|OPS_16|OPA_None, OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xA9, 0, 0}, 0, 2, {OPT_Areg|OPS_32|OPA_None, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xA9, 0, 0}, 0, 2, {OPT_Areg|OPS_64|OPA_None, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPA_EA, OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_16|OPA_Imm, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPA_EA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_32|OPA_Imm, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPA_EA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_32|OPA_Imm, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_8|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, 0} },
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, {OPT_Reg|OPS_8|OPA_Spare, OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info aadm_insn[] = {
+    { CPU_Any, MOD_Op0Add, 0, 0, 0, 2, {0xD4, 0x0A, 0}, 0, 0, {0, 0, 0} },
+    { CPU_Any, MOD_Op0Add, 0, 0, 0, 1, {0xD4, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0, 0} }
+};
+
+static const x86_insn_info imul_insn[] = {
+    { CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, {OPT_RM|OPS_8|OPA_EA, 0, 0} },
+    { CPU_Any, MOD_GasSufW, 16, 0, 0, 1, {0xF7, 0, 0}, 5, 1, {OPT_RM|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xF7, 0, 0}, 5, 1, {OPT_RM|OPS_32|OPA_EA, 0, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xF7, 0, 0}, 5, 1, {OPT_RM|OPS_64|OPA_EA, 0, 0} },
+    { CPU_386, MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386|CPU_64, MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_186, MOD_GasSufW, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 3, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPA_SImm} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 3, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPA_SImm} },
+    { CPU_186|CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 3, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPA_SImm} },
+    { CPU_186, MOD_GasSufW, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_SpareEA, OPT_Imm|OPS_8|OPA_SImm, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_SpareEA, OPT_Imm|OPS_8|OPA_SImm, 0} },
+    { CPU_186|CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_SpareEA, OPT_Imm|OPS_8|OPA_SImm, 0} },
+    { CPU_186, MOD_GasSufW, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_16|OPS_Relaxed|OPA_SImm|OPAP_SImm8} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_SImm|OPAP_SImm8} },
+    { CPU_186|CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_SImm|OPAP_SImm8} },
+    { CPU_186, MOD_GasSufW, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_SpareEA, OPT_Imm|OPS_16|OPS_Relaxed|OPA_SImm|OPAP_SImm8, 0} },
+    { CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_SpareEA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_SImm|OPAP_SImm8, 0} },
+    { CPU_186|CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_SpareEA, OPT_Imm|OPS_32|OPS_Relaxed|OPA_SImm|OPAP_SImm8, 0} }
+};
+
+static const x86_insn_info shift_insn[] = {
+    { CPU_Any, MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPA_EA, OPT_Creg|OPS_8|OPA_None, 0} },
+    { CPU_Any, MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPA_EA, OPT_Imm1|OPS_8|OPS_Relaxed|OPA_None, 0} },
+    { CPU_186, MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0xC0, 0, 0}, 0, 2, {OPT_RM|OPS_8|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0xD3, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPA_EA, OPT_Creg|OPS_8|OPA_None, 0} },
+    { CPU_Any, MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPA_EA, OPT_Imm1|OPS_8|OPS_Relaxed|OPA_None, 0} },
+    { CPU_186, MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0xC1, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_386, MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0xD3, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPA_EA, OPT_Creg|OPS_8|OPA_None, 0} },
+    { CPU_386, MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPA_EA, OPT_Imm1|OPS_8|OPS_Relaxed|OPA_None, 0} },
+    { CPU_386, MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0xC1, 0, 0}, 0, 2, {OPT_RM|OPS_32|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_64, MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1, {0xD3, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPA_EA, OPT_Creg|OPS_8|OPA_None, 0} },
+    { CPU_64, MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPA_EA, OPT_Imm1|OPS_8|OPS_Relaxed|OPA_None, 0} },
+    { CPU_186|CPU_64, MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1, {0xC1, 0, 0}, 0, 2, {OPT_RM|OPS_64|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_Any, MOD_SpAdd|MOD_GasOnly|MOD_GasSufB, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 1, {OPT_RM|OPS_8|OPA_EA, 0, 0} },
+    { CPU_Any, MOD_SpAdd|MOD_GasOnly|MOD_GasSufW, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 1, {OPT_RM|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386, MOD_SpAdd|MOD_GasOnly|MOD_GasSufL, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 1, {OPT_RM|OPS_32|OPA_EA, 0, 0} },
+    { CPU_64, MOD_SpAdd|MOD_GasOnly|MOD_GasSufQ, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 1, {OPT_RM|OPS_64|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info shlrd_insn[] = {
+    { CPU_386, MOD_Op1Add|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_386, MOD_Op1Add|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, OPT_Creg|OPS_8|OPA_None} },
+    { CPU_386, MOD_Op1Add|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_386, MOD_Op1Add|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, OPT_Creg|OPS_8|OPA_None} },
+    { CPU_386|CPU_64, MOD_Op1Add|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_386|CPU_64, MOD_Op1Add|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, OPT_Creg|OPS_8|OPA_None} },
+    { CPU_386, MOD_Op1Add|MOD_GasOnly|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} },
+    { CPU_386, MOD_Op1Add|MOD_GasOnly|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_386|CPU_64, MOD_Op1Add|MOD_GasOnly|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, 0} }
+};
+
+static const x86_insn_info call_insn[] = {
+    { CPU_Any, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_ImmNotSegOff|OPS_Any|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 16, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_ImmNotSegOff|OPS_16|OPA_JmpRel, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_ImmNotSegOff|OPS_32|OPA_JmpRel, 0, 0} },
+    { CPU_64, 0, 64, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_ImmNotSegOff|OPS_32|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 16, 64, 0, 1, {0xE8, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0xE8, 0, 0}, 0, 1, {OPT_Imm|OPS_32|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_64, 0, 64, 64, 0, 1, {0xE8, 0, 0}, 0, 1, {OPT_Imm|OPS_32|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 0, 64, 0, 1, {0xE8, 0, 0}, 0, 1, {OPT_Imm|OPS_Any|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 16, 0, 0, 1, {0xFF, 0, 0}, 2, 1, {OPT_RM|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, {OPT_RM|OPS_32|OPA_EA, 0, 0} },
+    { CPU_64, 0, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, {OPT_RM|OPS_64|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, {OPT_Mem|OPS_Any|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 16, 64, 0, 1, {0xFF, 0, 0}, 2, 1, {OPT_RM|OPS_16|OPTM_Near|OPA_EA, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, {OPT_RM|OPS_32|OPTM_Near|OPA_EA, 0, 0} },
+    { CPU_64, 0, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, {OPT_RM|OPS_64|OPTM_Near|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, {OPT_Mem|OPS_Any|OPTM_Near|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 16, 0, 0, 1, {0xFF, 0, 0}, 3, 1, {OPT_Mem|OPS_16|OPTM_Far|OPA_EA, 0, 0} },
+    { CPU_386, 0, 32, 0, 0, 1, {0xFF, 0, 0}, 3, 1, {OPT_Mem|OPS_32|OPTM_Far|OPA_EA, 0, 0} },
+    { CPU_64, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 3, 1, {OPT_Mem|OPS_64|OPTM_Far|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, {OPT_Mem|OPS_Any|OPTM_Far|OPA_EA, 0, 0} },
+    { CPU_Not64, 0, 16, 0, 0, 1, {0x9A, 0, 0}, 3, 1, {OPT_Imm|OPS_16|OPTM_Far|OPA_JmpFar, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0x9A, 0, 0}, 3, 1, {OPT_Imm|OPS_32|OPTM_Far|OPA_JmpFar, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, {OPT_Imm|OPS_Any|OPTM_Far|OPA_JmpFar, 0, 0} },
+    { CPU_Not64, 0, 16, 0, 0, 1, {0x9A, 0, 0}, 3, 1, {OPT_Imm|OPS_16|OPA_JmpFar, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0x9A, 0, 0}, 3, 1, {OPT_Imm|OPS_32|OPA_JmpFar, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, {OPT_Imm|OPS_Any|OPA_JmpFar, 0, 0} }
+};
+
+static const x86_insn_info jmp_insn[] = {
+    { CPU_Any, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_ImmNotSegOff|OPS_Any|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 16, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_ImmNotSegOff|OPS_16|OPA_JmpRel, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_ImmNotSegOff|OPS_32|OPA_JmpRel, 0, 0} },
+    { CPU_64, 0, 64, 0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_ImmNotSegOff|OPS_32|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 0, 64, 0, 1, {0xEB, 0, 0}, 0, 1, {OPT_Imm|OPS_Any|OPTM_Short|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 16, 64, 0, 1, {0xE9, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0xE9, 0, 0}, 0, 1, {OPT_Imm|OPS_32|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_64, 0, 64, 64, 0, 1, {0xE9, 0, 0}, 0, 1, {OPT_Imm|OPS_32|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 0, 64, 0, 1, {0xE9, 0, 0}, 0, 1, {OPT_Imm|OPS_Any|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, {OPT_RM|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, {OPT_RM|OPS_32|OPA_EA, 0, 0} },
+    { CPU_64, 0, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, {OPT_RM|OPS_64|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, {OPT_Mem|OPS_Any|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, {OPT_RM|OPS_16|OPTM_Near|OPA_EA, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, {OPT_RM|OPS_32|OPTM_Near|OPA_EA, 0, 0} },
+    { CPU_64, 0, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, {OPT_RM|OPS_64|OPTM_Near|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, {OPT_Mem|OPS_Any|OPTM_Near|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 16, 0, 0, 1, {0xFF, 0, 0}, 5, 1, {OPT_Mem|OPS_16|OPTM_Far|OPA_EA, 0, 0} },
+    { CPU_386, 0, 32, 0, 0, 1, {0xFF, 0, 0}, 5, 1, {OPT_Mem|OPS_32|OPTM_Far|OPA_EA, 0, 0} },
+    { CPU_64, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 5, 1, {OPT_Mem|OPS_64|OPTM_Far|OPA_EA, 0, 0} },
+    { CPU_Any, 0, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, {OPT_Mem|OPS_Any|OPTM_Far|OPA_EA, 0, 0} },
+    { CPU_Not64, 0, 16, 0, 0, 1, {0xEA, 0, 0}, 3, 1, {OPT_Imm|OPS_16|OPTM_Far|OPA_JmpFar, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0xEA, 0, 0}, 3, 1, {OPT_Imm|OPS_32|OPTM_Far|OPA_JmpFar, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, {OPT_Imm|OPS_Any|OPTM_Far|OPA_JmpFar, 0, 0} },
+    { CPU_Not64, 0, 16, 0, 0, 1, {0xEA, 0, 0}, 3, 1, {OPT_Imm|OPS_16|OPA_JmpFar, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 1, {0xEA, 0, 0}, 3, 1, {OPT_Imm|OPS_32|OPA_JmpFar, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, {OPT_Imm|OPS_Any|OPA_JmpFar, 0, 0} }
+};
+
+static const x86_insn_info retnf_insn[] = {
+    { CPU_Not64, MOD_Op0Add, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, {0, 0, 0} },
+    { CPU_Not64, MOD_Op0Add, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0, 0} },
+    { CPU_64, MOD_Op0Add|MOD_OpSizeR, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, {0, 0, 0} },
+    { CPU_64, MOD_Op0Add|MOD_OpSizeR, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0, 0} },
+    { CPU_Any, MOD_Op0Add|MOD_OpSizeR|MOD_GasSufL|MOD_GasSufQ|MOD_GasSufW, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, {0, 0, 0} },
+    { CPU_Any, MOD_Op0Add|MOD_OpSizeR|MOD_GasSufL|MOD_GasSufQ|MOD_GasSufW, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0, 0} }
+};
+
+static const x86_insn_info enter_insn[] = {
+    { CPU_186|CPU_Not64, MOD_GasNoRev|MOD_GasSufL, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_EA|OPAP_A16, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_186|CPU_64, MOD_GasNoRev|MOD_GasSufQ, 64, 64, 0, 1, {0xC8, 0, 0}, 0, 2, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_EA|OPAP_A16, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_186, MOD_GasOnly|MOD_GasNoRev|MOD_GasSufW, 16, 0, 0, 1, {0xC8, 0, 0}, 0, 2, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_EA|OPAP_A16, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} }
+};
+
+static const x86_insn_info jcc_insn[] = {
+    { CPU_Any, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_Imm|OPS_Any|OPA_JmpRel, 0, 0} },
+    { CPU_Any, 0, 16, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPA_JmpRel, 0, 0} },
+    { CPU_386|CPU_Not64, 0, 32, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_Imm|OPS_32|OPA_JmpRel, 0, 0} },
+    { CPU_64, 0, 64, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_Imm|OPS_32|OPA_JmpRel, 0, 0} },
+    { CPU_Any, MOD_Op0Add, 0, 64, 0, 1, {0x70, 0, 0}, 0, 1, {OPT_Imm|OPS_Any|OPTM_Short|OPA_JmpRel, 0, 0} },
+    { CPU_186, MOD_Op1Add, 16, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, {OPT_Imm|OPS_16|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_386|CPU_Not64, MOD_Op1Add, 32, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, {OPT_Imm|OPS_32|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_64, MOD_Op1Add, 64, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, {OPT_Imm|OPS_32|OPTM_Near|OPA_JmpRel, 0, 0} },
+    { CPU_186, MOD_Op1Add, 0, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, {OPT_Imm|OPS_Any|OPTM_Near|OPA_JmpRel, 0, 0} }
+};
+
+static const x86_insn_info jcxz_insn[] = {
+    { CPU_Any, MOD_AdSizeR, 0, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_Imm|OPS_Any|OPA_JmpRel, 0, 0} },
+    { CPU_Any, MOD_AdSizeR, 0, 64, 0, 1, {0xE3, 0, 0}, 0, 1, {OPT_Imm|OPS_Any|OPTM_Short|OPA_JmpRel, 0, 0} }
+};
+
+static const x86_insn_info loop_insn[] = {
+    { CPU_Any, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, {OPT_Imm|OPS_Any|OPA_JmpRel, 0, 0} },
+    { CPU_Not64, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 2, {OPT_Imm|OPS_Any|OPA_JmpRel, OPT_Creg|OPS_16|OPA_AdSizeR, 0} },
+    { CPU_386, 0, 0, 64, 0, 0, {0, 0, 0}, 0, 2, {OPT_Imm|OPS_Any|OPA_JmpRel, OPT_Creg|OPS_32|OPA_AdSizeR, 0} },
+    { CPU_64, 0, 0, 64, 0, 0, {0, 0, 0}, 0, 2, {OPT_Imm|OPS_Any|OPA_JmpRel, OPT_Creg|OPS_64|OPA_AdSizeR, 0} },
+    { CPU_Not64, MOD_Op0Add, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1, {OPT_Imm|OPS_Any|OPTM_Short|OPA_JmpRel, 0, 0} },
+    { CPU_Any, MOD_Op0Add, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, {OPT_Imm|OPS_Any|OPTM_Short|OPA_JmpRel, OPT_Creg|OPS_16|OPA_AdSizeR, 0} },
+    { CPU_386, MOD_Op0Add, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, {OPT_Imm|OPS_Any|OPTM_Short|OPA_JmpRel, OPT_Creg|OPS_32|OPA_AdSizeR, 0} },
+    { CPU_64, MOD_Op0Add, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, {OPT_Imm|OPS_Any|OPTM_Short|OPA_JmpRel, OPT_Creg|OPS_64|OPA_AdSizeR, 0} }
+};
+
+static const x86_insn_info setcc_insn[] = {
+    { CPU_386, MOD_Op1Add|MOD_GasSufB, 0, 0, 0, 2, {0x0F, 0x90, 0}, 2, 1, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info cmpsd_insn[] = {
+    { CPU_386, MOD_GasIllegal, 32, 0, 0, 1, {0xA7, 0, 0}, 0, 0, {0, 0, 0} },
+    { CPU_SSE2, 0, 0, 0, 0xF2, 2, {0x0F, 0xC2, 0}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info movsd_insn[] = {
+    { CPU_386, MOD_GasIllegal, 32, 0, 0, 1, {0xA5, 0, 0}, 0, 0, {0, 0, 0} },
+    { CPU_SSE2, 0, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_SSE2, 0, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE2, 0, 0, 0, 0xF2, 2, {0x0F, 0x11, 0}, 0, 2, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info bittest_insn[] = {
+    { CPU_386, MOD_Op1Add|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} },
+    { CPU_386, MOD_Op1Add|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_386|CPU_64, MOD_Op1Add|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, 0} },
+    { CPU_386, MOD_Gap0|MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, {OPT_RM|OPS_16|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_386, MOD_Gap0|MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, {OPT_RM|OPS_32|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_386|CPU_64, MOD_Gap0|MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, {OPT_RM|OPS_64|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} }
+};
+
+static const x86_insn_info bsfr_insn[] = {
+    { CPU_386, MOD_Op1Add|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386, MOD_Op1Add|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386|CPU_64, MOD_Op1Add|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info int_insn[] = {
+    { CPU_Any, 0, 0, 0, 0, 1, {0xCD, 0, 0}, 0, 1, {OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0, 0} }
+};
+
+static const x86_insn_info bound_insn[] = {
+    { CPU_186|CPU_Not64, MOD_GasSufW, 16, 0, 0, 1, {0x62, 0, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386|CPU_Not64, MOD_GasSufL, 32, 0, 0, 1, {0x62, 0, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info arpl_insn[] = {
+    { CPU_286|CPU_Not64|CPU_Prot, MOD_GasSufW, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} }
+};
+
+static const x86_insn_info str_insn[] = {
+    { CPU_286|CPU_Prot, MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, {OPT_Reg|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386|CPU_Prot, MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, {OPT_Reg|OPS_32|OPA_EA, 0, 0} },
+    { CPU_286|CPU_64|CPU_Prot, MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, {OPT_Reg|OPS_64|OPA_EA, 0, 0} },
+    { CPU_286|CPU_Prot, MOD_GasSufL|MOD_GasSufW, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info prot286_insn[] = {
+    { CPU_286, MOD_Op1Add|MOD_SpAdd|MOD_GasSufW, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info sldtmsw_insn[] = {
+    { CPU_286, MOD_Op1Add|MOD_SpAdd|MOD_GasSufW, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, {OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, 0, 0} },
+    { CPU_386, MOD_Op1Add|MOD_SpAdd|MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, {OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0, 0} },
+    { CPU_286|CPU_64, MOD_Op1Add|MOD_SpAdd|MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0, 0} },
+    { CPU_286, MOD_Op1Add|MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, {OPT_Reg|OPS_16|OPA_EA, 0, 0} },
+    { CPU_386, MOD_Op1Add|MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, {OPT_Reg|OPS_32|OPA_EA, 0, 0} },
+    { CPU_286|CPU_64, MOD_Op1Add|MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, {OPT_Reg|OPS_64|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info fld_insn[] = {
+    { CPU_FPU, MOD_GasSufS, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, {OPT_Mem|OPS_32|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_GasSufL, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, {OPT_Mem|OPS_64|OPA_EA, 0, 0} },
+    { CPU_FPU, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, {OPT_Mem|OPS_80|OPA_EA, 0, 0} },
+    { CPU_FPU, 0, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} }
+};
+
+static const x86_insn_info fstp_insn[] = {
+    { CPU_FPU, MOD_GasSufS, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, {OPT_Mem|OPS_32|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_GasSufL, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, {OPT_Mem|OPS_64|OPA_EA, 0, 0} },
+    { CPU_FPU, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, {OPT_Mem|OPS_80|OPA_EA, 0, 0} },
+    { CPU_FPU, 0, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} }
+};
+
+static const x86_insn_info fldstpt_insn[] = {
+    { CPU_FPU, MOD_SpAdd, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, {OPT_Mem|OPS_80|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info fildstp_insn[] = {
+    { CPU_FPU, MOD_SpAdd|MOD_GasSufS, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, {OPT_Mem|OPS_16|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_SpAdd|MOD_GasSufL, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, {OPT_Mem|OPS_32|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_Gap0|MOD_Op0Add|MOD_SpAdd|MOD_GasSufQ, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, {OPT_Mem|OPS_64|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info fbldstp_insn[] = {
+    { CPU_FPU, MOD_SpAdd, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, {OPT_Mem|OPS_80|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info fst_insn[] = {
+    { CPU_FPU, MOD_GasSufS, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, {OPT_Mem|OPS_32|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_GasSufL, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, {OPT_Mem|OPS_64|OPA_EA, 0, 0} },
+    { CPU_FPU, 0, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} }
+};
+
+static const x86_insn_info fxch_insn[] = {
+    { CPU_FPU, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} },
+    { CPU_FPU, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, {OPT_ST0|OPS_80|OPA_None, OPT_Reg|OPS_80|OPA_Op1Add, 0} },
+    { CPU_FPU, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, {OPT_Reg|OPS_80|OPA_Op1Add, OPT_ST0|OPS_80|OPA_None, 0} },
+    { CPU_FPU, 0, 0, 0, 0, 2, {0xD9, 0xC9, 0}, 0, 0, {0, 0, 0} }
+};
+
+static const x86_insn_info fcom_insn[] = {
+    { CPU_FPU, MOD_Gap0|MOD_SpAdd|MOD_GasSufS, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, {OPT_Mem|OPS_32|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_Gap0|MOD_SpAdd|MOD_GasSufL, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, {OPT_Mem|OPS_64|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_Op1Add, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} },
+    { CPU_FPU, MOD_Op1Add|MOD_GasOnly, 0, 0, 0, 2, {0xD8, 0x01, 0}, 0, 0, {0, 0, 0} },
+    { CPU_FPU, MOD_Op1Add|MOD_GasIllegal, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, {OPT_ST0|OPS_80|OPA_None, OPT_Reg|OPS_80|OPA_Op1Add, 0} }
+};
+
+static const x86_insn_info fcom2_insn[] = {
+    { CPU_286|CPU_FPU, MOD_Op1Add|MOD_Op0Add, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} },
+    { CPU_286|CPU_FPU, MOD_Op1Add|MOD_Op0Add, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, {OPT_ST0|OPS_80|OPA_None, OPT_Reg|OPS_80|OPA_Op1Add, 0} }
+};
+
+static const x86_insn_info farith_insn[] = {
+    { CPU_FPU, MOD_Gap0|MOD_Gap1|MOD_SpAdd|MOD_GasSufS, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, {OPT_Mem|OPS_32|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_Gap0|MOD_Gap1|MOD_SpAdd|MOD_GasSufL, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, {OPT_Mem|OPS_64|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_Gap0|MOD_Op1Add, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} },
+    { CPU_FPU, MOD_Gap0|MOD_Op1Add, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, {OPT_ST0|OPS_80|OPA_None, OPT_Reg|OPS_80|OPA_Op1Add, 0} },
+    { CPU_FPU, MOD_Op1Add, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 1, {OPT_Reg|OPS_80|OPTM_To|OPA_Op1Add, 0, 0} },
+    { CPU_FPU, MOD_Op1Add|MOD_GasIllegal, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, {OPT_Reg|OPS_80|OPA_Op1Add, OPT_ST0|OPS_80|OPA_None, 0} },
+    { CPU_FPU, MOD_Gap0|MOD_Op1Add|MOD_GasOnly, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, {OPT_Reg|OPS_80|OPA_Op1Add, OPT_ST0|OPS_80|OPA_None, 0} }
+};
+
+static const x86_insn_info farithp_insn[] = {
+    { CPU_FPU, MOD_Op1Add, 0, 0, 0, 2, {0xDE, 0x01, 0}, 0, 0, {0, 0, 0} },
+    { CPU_FPU, MOD_Op1Add, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} },
+    { CPU_FPU, MOD_Op1Add, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 2, {OPT_Reg|OPS_80|OPA_Op1Add, OPT_ST0|OPS_80|OPA_None, 0} }
+};
+
+static const x86_insn_info fiarith_insn[] = {
+    { CPU_FPU, MOD_Op0Add|MOD_SpAdd|MOD_GasSufS, 0, 0, 0, 1, {0x04, 0, 0}, 0, 1, {OPT_Mem|OPS_16|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_Op0Add|MOD_SpAdd|MOD_GasSufL, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_Mem|OPS_32|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info fldnstcw_insn[] = {
+    { CPU_FPU, MOD_SpAdd|MOD_GasSufW, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, {OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info fstcw_insn[] = {
+    { CPU_FPU, MOD_GasSufW, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1, {OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info fnstsw_insn[] = {
+    { CPU_FPU, MOD_GasSufW, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, {OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_GasSufW, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, {OPT_Areg|OPS_16|OPA_None, 0, 0} }
+};
+
+static const x86_insn_info fstsw_insn[] = {
+    { CPU_FPU, MOD_GasSufW, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1, {OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, 0, 0} },
+    { CPU_FPU, MOD_GasSufW, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, {OPT_Areg|OPS_16|OPA_None, 0, 0} }
+};
+
+static const x86_insn_info ffree_insn[] = {
+    { CPU_FPU, MOD_Op0Add, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} }
+};
+
+static const x86_insn_info bswap_insn[] = {
+    { CPU_486, MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, {OPT_Reg|OPS_32|OPA_Op1Add, 0, 0} },
+    { CPU_64, MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, {OPT_Reg|OPS_64|OPA_Op1Add, 0, 0} }
+};
+
+static const x86_insn_info cmpxchgxadd_insn[] = {
+    { CPU_486, MOD_Op1Add|MOD_GasSufB, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_8|OPA_Spare, 0} },
+    { CPU_486, MOD_Op1Add|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} },
+    { CPU_486, MOD_Op1Add|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_486|CPU_64, MOD_Op1Add|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, 0} }
+};
+
+static const x86_insn_info cmpxchg8b_insn[] = {
+    { CPU_586, MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info cmovcc_insn[] = {
+    { CPU_686, MOD_Op1Add|MOD_GasSufW, 16, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_686, MOD_Op1Add|MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_686, MOD_Op1Add|MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info fcmovcc_insn[] = {
+    { CPU_686|CPU_FPU, MOD_Op1Add|MOD_Op0Add, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, {OPT_ST0|OPS_80|OPA_None, OPT_Reg|OPS_80|OPA_Op1Add, 0} }
+};
+
+static const x86_insn_info movnti_insn[] = {
+    { CPU_P4, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, {OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_64|CPU_P4, MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, 0} }
+};
+
+static const x86_insn_info clflush_insn[] = {
+    { CPU_P3, 0, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, {OPT_Mem|OPS_8|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info movd_insn[] = {
+    { CPU_386|CPU_MMX, 0, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_MMX, 0, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386|CPU_MMX, 0, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} },
+    { CPU_64|CPU_MMX, 0, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} },
+    { CPU_386|CPU_SSE2, 0, 0, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_SSE2, 0, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386|CPU_SSE2, 0, 0, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} },
+    { CPU_64|CPU_SSE2, 0, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movq_insn[] = {
+    { CPU_MMX, MOD_GasIllegal, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_MMX, MOD_GasIllegal, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_MMX, MOD_GasIllegal, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, {OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} },
+    { CPU_64|CPU_MMX, MOD_GasIllegal, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} },
+    { CPU_SSE2, MOD_GasIllegal, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_SSE2, MOD_GasIllegal, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_SSE2, MOD_GasIllegal, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE2, MOD_GasIllegal, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, {OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} },
+    { CPU_64|CPU_SSE2, MOD_GasIllegal, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info mmxsse2_insn[] = {
+    { CPU_MMX, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE2, MOD_Op1Add, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info pshift_insn[] = {
+    { CPU_MMX, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_MMX, MOD_Gap0|MOD_Op1Add|MOD_SpAdd, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
+    { CPU_SSE2, MOD_Op1Add, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE2, MOD_Gap0|MOD_Op1Add|MOD_SpAdd, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} }
+};
+
+static const x86_insn_info sseps_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cvt_rx_xmm32_insn[] = {
+    { CPU_386|CPU_SSE, MOD_Op1Add|MOD_PreAdd|MOD_GasSufL, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_386|CPU_SSE, MOD_Op1Add|MOD_PreAdd|MOD_GasSufL, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_SSE, MOD_Op1Add|MOD_PreAdd|MOD_GasSufQ, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_64|CPU_SSE, MOD_Op1Add|MOD_PreAdd|MOD_GasSufQ, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cvt_mm_xmm64_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cvt_xmm_mm_ps_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cvt_xmm_rmx_insn[] = {
+    { CPU_386|CPU_SSE, MOD_Op1Add|MOD_PreAdd|MOD_GasSufL, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_SSE, MOD_Op1Add|MOD_PreAdd|MOD_GasSufQ, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info ssess_insn[] = {
+    { CPU_SSE, MOD_Op1Add|MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info ssecmpps_insn[] = {
+    { CPU_SSE, MOD_Imm8, 0, 0, 0, 2, {0x0F, 0xC2, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info ssecmpss_insn[] = {
+    { CPU_SSE, MOD_PreAdd|MOD_Imm8, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info ssepsimm_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info ssessimm_insn[] = {
+    { CPU_SSE, MOD_Op1Add|MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info ldstmxcsr_insn[] = {
+    { CPU_SSE, MOD_SpAdd, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 0, 1, {OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info maskmovq_insn[] = {
+    { CPU_MMX|CPU_P3, 0, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_64|OPA_EA, 0} }
+};
+
+static const x86_insn_info movaups_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movhllhps_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info movhlps_insn[] = {
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movmskps_insn[] = {
+    { CPU_386|CPU_SSE, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0x50, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_64|CPU_SSE, MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0x50, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info movntps_insn[] = {
+    { CPU_SSE, 0, 0, 0, 0, 2, {0x0F, 0x2B, 0}, 0, 2, {OPT_Mem|OPS_128|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movntq_insn[] = {
+    { CPU_SSE, 0, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movss_insn[] = {
+    { CPU_SSE, 0, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_SSE, 0, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE, 0, 0, 0, 0xF3, 2, {0x0F, 0x11, 0}, 0, 2, {OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info pextrw_insn[] = {
+    { CPU_MMX|CPU_P3, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_64|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_386|CPU_SSE2, MOD_GasSufL, 0, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_64|CPU_MMX|CPU_P3, MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, {OPT_Reg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_64|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_64|CPU_SSE2, MOD_GasSufQ, 64, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, {OPT_Reg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_SSE41, 0, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, {OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_386|CPU_SSE41, 0, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, {OPT_Reg|OPS_32|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_64|CPU_SSE41, 0, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, {OPT_Reg|OPS_64|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info pinsrw_insn[] = {
+    { CPU_MMX|CPU_P3, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_Reg|OPS_32|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_64|CPU_MMX|CPU_P3, MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_Reg|OPS_64|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_MMX|CPU_P3, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_386|CPU_SSE2, MOD_GasSufL, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Reg|OPS_32|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_64|CPU_SSE2, MOD_GasSufQ, 64, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Reg|OPS_64|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_SSE2, MOD_GasSufL, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info pmovmskb_insn[] = {
+    { CPU_MMX|CPU_P3, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_64|OPA_EA, 0} },
+    { CPU_386|CPU_SSE2, MOD_GasSufL, 0, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_64|CPU_MMX|CPU_P3, MOD_GasSufQ, 64, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_64|OPA_EA, 0} },
+    { CPU_64|CPU_SSE2, MOD_GasSufQ, 64, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info pshufw_insn[] = {
+    { CPU_MMX|CPU_P3, 0, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info cvt_xmm_xmm64_ss_insn[] = {
+    { CPU_SSE2, MOD_Op1Add|MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_SSE2, MOD_Op1Add|MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cvt_xmm_xmm64_ps_insn[] = {
+    { CPU_SSE2, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_SSE2, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cvt_rx_xmm64_insn[] = {
+    { CPU_386|CPU_SSE2, MOD_Op1Add|MOD_PreAdd|MOD_GasSufL, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_386|CPU_SSE2, MOD_Op1Add|MOD_PreAdd|MOD_GasSufL, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_SSE2, MOD_Op1Add|MOD_PreAdd|MOD_GasSufQ, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_64|CPU_SSE2, MOD_Op1Add|MOD_PreAdd|MOD_GasSufQ, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cvt_mm_xmm_insn[] = {
+    { CPU_SSE2, MOD_Op1Add|MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cvt_xmm_mm_ss_insn[] = {
+    { CPU_SSE, MOD_Op1Add|MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info movaupd_insn[] = {
+    { CPU_SSE2, MOD_Op1Add, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE2, MOD_Op1Add, 0, 0, 0x66, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movhlpd_insn[] = {
+    { CPU_SSE2, MOD_Op1Add, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE2, MOD_Op1Add, 0, 0, 0x66, 2, {0x0F, 0x01, 0}, 0, 2, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movmskpd_insn[] = {
+    { CPU_386|CPU_SSE2, MOD_GasSufL, 0, 0, 0x66, 2, {0x0F, 0x50, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_64|CPU_SSE2, MOD_GasSufQ, 0, 0, 0x66, 2, {0x0F, 0x50, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info movntpddq_insn[] = {
+    { CPU_SSE2, MOD_Op1Add, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Mem|OPS_128|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info vmxmemrd_insn[] = {
+    { CPU_Not64|CPU_P4, MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_64|CPU_P4, MOD_GasSufQ, 64, 64, 0, 2, {0x0F, 0x78, 0}, 0, 2, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_64|OPA_Spare, 0} }
+};
+
+static const x86_insn_info vmxmemwr_insn[] = {
+    { CPU_Not64|CPU_P4, MOD_GasSufL, 32, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_P4, MOD_GasSufQ, 64, 64, 0, 2, {0x0F, 0x79, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info vmxtwobytemem_insn[] = {
+    { CPU_P4, MOD_SpAdd, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 0, 1, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info vmxthreebytemem_insn[] = {
+    { CPU_P4, MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0xC7, 0}, 6, 1, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info cvt_xmm_xmm32_insn[] = {
+    { CPU_SSE2, MOD_Op1Add|MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_SSE2, MOD_Op1Add|MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info maskmovdqu_insn[] = {
+    { CPU_SSE2, 0, 0, 0, 0x66, 2, {0x0F, 0xF7, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info movdqau_insn[] = {
+    { CPU_SSE2, MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x6F, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE2, MOD_PreAdd, 0, 0, 0x00, 2, {0x0F, 0x7F, 0}, 0, 2, {OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movdq2q_insn[] = {
+    { CPU_SSE2, 0, 0, 0, 0xF2, 2, {0x0F, 0xD6, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info movq2dq_insn[] = {
+    { CPU_SSE2, 0, 0, 0, 0xF3, 2, {0x0F, 0xD6, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_64|OPA_EA, 0} }
+};
+
+static const x86_insn_info pslrldq_insn[] = {
+    { CPU_SSE2, MOD_SpAdd, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} }
+};
+
+static const x86_insn_info lddqu_insn[] = {
+    { CPU_SSE3, 0, 0, 0, 0xF2, 2, {0x0F, 0xF0, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_Any|OPA_EA, 0} }
+};
+
+static const x86_insn_info ssse3_insn[] = {
+    { CPU_SSSE3, MOD_Op2Add, 0, 0, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSSE3, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info ssse3imm_insn[] = {
+    { CPU_SSSE3, MOD_Op2Add, 0, 0, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_SSSE3, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info sse4_insn[] = {
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info sse4imm_insn[] = {
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info sse4xmm0_insn[] = {
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_XMM0|OPS_128|OPA_None} }
+};
+
+static const x86_insn_info crc32_insn[] = {
+    { CPU_386|CPU_SSE42, MOD_GasSufB, 0, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_8|OPA_EA, 0} },
+    { CPU_386|CPU_SSE42, MOD_GasSufW, 16, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_16|OPA_EA, 0} },
+    { CPU_386|CPU_SSE42, MOD_GasSufL, 32, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64|CPU_SSE42, MOD_GasSufB, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_8|OPA_EA, 0} },
+    { CPU_64|CPU_SSE42, MOD_GasSufQ, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info extractps_insn[] = {
+    { CPU_386|CPU_SSE41, 0, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_64|CPU_SSE41, 0, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, {OPT_Reg|OPS_64|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info insertps_insn[] = {
+    { CPU_SSE41, 0, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_SSE41, 0, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info movntdqa_insn[] = {
+    { CPU_SSE41, 0, 0, 0, 0x66, 3, {0x0F, 0x38, 0x2A}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_128|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info sse4pcmpstr_insn[] = {
+    { CPU_SSE42, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_128|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info pextrb_insn[] = {
+    { CPU_SSE41, 0, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, {OPT_Mem|OPS_8|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_386|CPU_SSE41, 0, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, {OPT_Reg|OPS_32|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_64|CPU_SSE41, 0, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, {OPT_Reg|OPS_64|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info pextrd_insn[] = {
+    { CPU_386|CPU_SSE41, 0, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info pextrq_insn[] = {
+    { CPU_64|CPU_SSE41, 0, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info pinsrb_insn[] = {
+    { CPU_SSE41, 0, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_8|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_386|CPU_SSE41, 0, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Reg|OPS_32|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info pinsrd_insn[] = {
+    { CPU_386|CPU_SSE41, 0, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info pinsrq_insn[] = {
+    { CPU_64|CPU_SSE41, 0, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} }
+};
+
+static const x86_insn_info sse4m64_insn[] = {
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info sse4m32_insn[] = {
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info sse4m16_insn[] = {
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE41, MOD_Op2Add, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info cnt_insn[] = {
+    { CPU_Any, MOD_Op1Add|MOD_GasSufW, 16, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386, MOD_Op1Add|MOD_GasSufL, 32, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_64, MOD_Op1Add|MOD_GasSufQ, 64, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_Reg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info extrq_insn[] = {
+    { CPU_SSE41, 0, 0, 0, 0x66, 2, {0x0F, 0x78, 0}, 0, 3, {OPT_SIMDReg|OPS_128|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm} },
+    { CPU_SSE41, 0, 0, 0, 0x66, 2, {0x0F, 0x79, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info insertq_insn[] = {
+    { CPU_SSE41, 0, 0, 0, 0xF2, 2, {0x0F, 0x78, 0}, 0, 4, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_EA} },
+    { CPU_SSE41, 0, 0, 0, 0xF2, 2, {0x0F, 0x79, 0}, 0, 2, {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} }
+};
+
+static const x86_insn_info movntsd_insn[] = {
+    { CPU_SSE41, 0, 0, 0, 0xF2, 2, {0x0F, 0x2B, 0}, 0, 2, {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info movntss_insn[] = {
+    { CPU_SSE41, 0, 0, 0, 0xF3, 2, {0x0F, 0x2B, 0}, 0, 2, {OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+};
+
+static const x86_insn_info now3d_insn[] = {
+    { CPU_3DNow, MOD_Imm8, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cmpxchg16b_insn[] = {
+    { CPU_64, 0, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, {OPT_Mem|OPS_128|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info invlpga_insn[] = {
+    { CPU_SVM, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 0, {0, 0, 0} },
+    { CPU_386|CPU_SVM, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 2, {OPT_MemrAX|OPS_Any|OPA_AdSizeEA, OPT_Creg|OPS_32|OPA_None, 0} }
+};
+
+static const x86_insn_info skinit_insn[] = {
+    { CPU_SVM, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 0, {0, 0, 0} },
+    { CPU_SVM, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, {OPT_MemEAX|OPS_Any|OPA_None, 0, 0} }
+};
+
+static const x86_insn_info svm_rax_insn[] = {
+    { CPU_SVM, MOD_Op2Add, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 0, {0, 0, 0} },
+    { CPU_SVM, MOD_Op2Add, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 1, {OPT_MemrAX|OPS_Any|OPA_AdSizeEA, 0, 0} }
+};
+
+static const x86_insn_info padlock_insn[] = {
+    { CPU_PadLock, MOD_Op1Add|MOD_PreAdd|MOD_Imm8, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 0, {0, 0, 0} }
+};
+
+static const x86_insn_info cyrixmmx_insn[] = {
+    { CPU_Cyrix|CPU_MMX, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info pmachriw_insn[] = {
+    { CPU_Cyrix|CPU_MMX, 0, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info rdwrshr_insn[] = {
+    { CPU_686|CPU_Cyrix|CPU_SMM, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x36, 0}, 0, 1, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info rsdc_insn[] = {
+    { CPU_486|CPU_Cyrix|CPU_SMM, 0, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, {OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, OPT_Mem|OPS_80|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info cyrixsmm_insn[] = {
+    { CPU_486|CPU_Cyrix|CPU_SMM, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, {OPT_Mem|OPS_80|OPS_Relaxed|OPA_EA, 0, 0} }
+};
+
+static const x86_insn_info svdc_insn[] = {
+    { CPU_486|CPU_Cyrix|CPU_SMM, 0, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, {OPT_Mem|OPS_80|OPS_Relaxed|OPA_EA, OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} }
+};
+
+static const x86_insn_info ibts_insn[] = {
+    { CPU_386|CPU_Obs|CPU_Undoc, 0, 16, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} },
+    { CPU_386|CPU_Obs|CPU_Undoc, 0, 32, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} }
+};
+
+static const x86_insn_info umov_insn[] = {
+    { CPU_386|CPU_Undoc, 0, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, {OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_8|OPA_Spare, 0} },
+    { CPU_386|CPU_Undoc, 0, 16, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_16|OPA_Spare, 0} },
+    { CPU_386|CPU_Undoc, 0, 32, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_32|OPA_Spare, 0} },
+    { CPU_386|CPU_Undoc, 0, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0, 2, {OPT_Reg|OPS_8|OPA_Spare, OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386|CPU_Undoc, 0, 16, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386|CPU_Undoc, 0, 32, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} }
+};
+
+static const x86_insn_info xbts_insn[] = {
+    { CPU_386|CPU_Obs|CPU_Undoc, 0, 16, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, {OPT_Reg|OPS_16|OPA_Spare, OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_386|CPU_Obs|CPU_Undoc, 0, 32, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, {OPT_Reg|OPS_32|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0} }
+};
+