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| author | Peter Johnson <peter@tortall.net> | 2008-02-02 19:23:17 +0000 |
|---|---|---|
| committer | Peter Johnson <peter@tortall.net> | 2008-02-02 19:23:17 +0000 |
| commit | 2fe53b2c299bf8292b7780105742ac357bcf8224 (patch) | |
| tree | c17c0915e58fce2ef1127d329a60dd67d022d6f8 /modules/arch/x86/gen_x86_insn.py | |
| parent | e03b37ca5d4e684cee984cb7044ff5c14e5e3351 (diff) | |
| download | yasm-2fe53b2c299bf8292b7780105742ac357bcf8224.tar.gz | |
Revert r2029. According to both AMD64 and Intel 64 instruction set
references, REX + 90h opcode is not NOP, but a valid XCHG:
"The x86 architecture commonly uses the XCHG EAX, EAX instruction (opcode
90h) as a one-byte NOP. In 64-bit mode, the processor treats opcode 90h as
a true NOP only if it would exchange rAX with itself. Without this special
handling, the instruction would zero-extend the upper 32 bits of RAX, and
thus it would not be a true nooperation. Opcode 90h can still be used to
exchange rAX and r8 if the appropriate REX prefix is used."
Noticed by: nasm64developer@users.sf.net
svn path=/trunk/yasm/; revision=2031
Diffstat (limited to 'modules/arch/x86/gen_x86_insn.py')
| -rwxr-xr-x | modules/arch/x86/gen_x86_insn.py | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py index bb1ec5fe..fd923d4f 100755 --- a/modules/arch/x86/gen_x86_insn.py +++ b/modules/arch/x86/gen_x86_insn.py @@ -1357,12 +1357,12 @@ add_group("xchg", opersize=16, opcode=[0x90], operands=[Operand(type="Areg", size=16, dest=None), - Operand(type="RegNotR8", size=16, dest="Op0Add")]) + Operand(type="Reg", size=16, dest="Op0Add")]) add_group("xchg", suffix="w", opersize=16, opcode=[0x90], - operands=[Operand(type="RegNotR8", size=16, dest="Op0Add"), + operands=[Operand(type="Reg", size=16, dest="Op0Add"), Operand(type="Areg", size=16, dest=None)]) add_group("xchg", suffix="w", @@ -1396,12 +1396,12 @@ add_group("xchg", opersize=32, opcode=[0x90], operands=[Operand(type="Areg", size=32, dest=None), - Operand(type="RegNotR8", size=32, dest="Op0Add")]) + Operand(type="Reg", size=32, dest="Op0Add")]) add_group("xchg", suffix="l", opersize=32, opcode=[0x90], - operands=[Operand(type="RegNotR8", size=32, dest="Op0Add"), + operands=[Operand(type="Reg", size=32, dest="Op0Add"), Operand(type="Areg", size=32, dest=None)]) add_group("xchg", suffix="l", @@ -1428,12 +1428,12 @@ add_group("xchg", opersize=64, opcode=[0x90], operands=[Operand(type="Areg", size=64, dest=None), - Operand(type="RegNotR8", size=64, dest="Op0Add")]) + Operand(type="Reg", size=64, dest="Op0Add")]) add_group("xchg", suffix="q", opersize=64, opcode=[0x90], - operands=[Operand(type="RegNotR8", size=64, dest="Op0Add"), + operands=[Operand(type="Reg", size=64, dest="Op0Add"), Operand(type="Areg", size=64, dest=None)]) add_group("xchg", suffix="q", |