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path: root/modules/arch/x86/gen_x86_insn.py
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* Default memory size to "s" for no-suffix FP conversions in GAS syntax.Peter Johnson2009-03-291-0/+16
* Add support for VEX-encoded pclmul*qdq instructions per the latest AVX spec.Peter Johnson2009-02-021-6/+35
* Update AVX and FMA to latest Intel specification (Dec 2008).Peter Johnson2009-01-141-175/+73
* gen_x86_insn.py: Handle invalid rcstag.Peter Johnson2008-12-051-2/+6
* Add movbe instruction and CPU feature.Peter Johnson2008-10-161-0/+18
* Add core TASM syntax support.Peter Johnson2008-10-071-4/+4
* Optimize non-strict push with 66 override to byte size if possible in NASMPeter Johnson2008-10-051-16/+14
* VPBLENDVB doesn't have a 256-bit form.Peter Johnson2008-10-021-1/+14
* gen_x86_insn.py: Warn if any groups are unused (due to a typo, for example).Peter Johnson2008-10-021-0/+7
* Mark gen_x86_insn.py outputs as generated, to discourage hand-editing.Peter Johnson2008-09-101-1/+7
* Add support for newly specified AVX/AES instructions:Peter Johnson2008-08-131-2/+38
* Fix #137: LAR and LSL should only need 286+Prot CPU flags, not 386.Peter Johnson2008-04-291-3/+2
* Fix two instances of VERMIL2PS/PD incorrectly setting VEX.L=1.Peter Johnson2008-04-251-2/+2
* Fix register fields on FMA instructions.Peter Johnson2008-04-221-11/+11
* Fix a number of AVX instructions where VEX.vvvv was incorrectly being setPeter Johnson2008-04-211-12/+68
* Fix AVX instruction misnaming of new vptest variants:Peter Johnson2008-04-211-2/+2
* Add complete Intel Advanced Vector Extensions (AVX) support.Peter Johnson2008-04-111-170/+1677
* Move BITS==64 condition out of the CPU field (where it really doesn't belong)Peter Johnson2008-04-111-36/+59
* PCOMUcc should have been PCOMccU.Peter Johnson2008-04-041-35/+45
* Add mnenomic condition codes for SSE5 comparison opcodes.Peter Johnson2008-04-031-0/+49
* Add support for Nehalem XSAVE instructions and CPU feature.Peter Johnson2008-02-221-0/+12
* Revert r2029. According to both AMD64 and Intel 64 instruction setPeter Johnson2008-02-021-6/+6
* Don't generate 0x90 opcode for xchg rax, r8 and varieties thereof.Peter Johnson2008-01-281-6/+6
* Fix #129: Support no-operand form of movsd in GAS syntax.Peter Johnson2008-01-031-1/+1
* Fix #119. Quite a few SSE/SSE2 instructions assumed 128-bit memory sizesPeter Johnson2007-11-281-154/+174
* Add SSE5 (new AMD SSE) instructions support.Peter Johnson2007-09-161-47/+380
* Switch x86 operand storage from manual bitfields to C structure bitfields.Peter Johnson2007-09-131-22/+9
* Change modifiers from a prioritized shifted sequence into an ordered array.Peter Johnson2007-09-131-55/+23
* Add Id tag.Peter Johnson2007-09-121-1/+1
* Now that we have more cpu feature bits, properly document SSE4a as such.Peter Johnson2007-09-121-8/+8
* Restructure x86 CPU handling to allow for more than 30 CPU feature flags.Peter Johnson2007-09-121-8/+41
* Shrink the size of the x86_insn_info structure, particularly on 64-bitPeter Johnson2007-09-111-8/+40
* Change x86 instruction tables to be automatically generated.Peter Johnson2007-09-101-0/+5284