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baserock/danielsilverstone/vagrant-support
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x86
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gen_x86_insn.py
Commit message (
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Author
Age
Files
Lines
*
Default memory size to "s" for no-suffix FP conversions in GAS syntax.
Peter Johnson
2009-03-29
1
-0
/
+16
*
Add support for VEX-encoded pclmul*qdq instructions per the latest AVX spec.
Peter Johnson
2009-02-02
1
-6
/
+35
*
Update AVX and FMA to latest Intel specification (Dec 2008).
Peter Johnson
2009-01-14
1
-175
/
+73
*
gen_x86_insn.py: Handle invalid rcstag.
Peter Johnson
2008-12-05
1
-2
/
+6
*
Add movbe instruction and CPU feature.
Peter Johnson
2008-10-16
1
-0
/
+18
*
Add core TASM syntax support.
Peter Johnson
2008-10-07
1
-4
/
+4
*
Optimize non-strict push with 66 override to byte size if possible in NASM
Peter Johnson
2008-10-05
1
-16
/
+14
*
VPBLENDVB doesn't have a 256-bit form.
Peter Johnson
2008-10-02
1
-1
/
+14
*
gen_x86_insn.py: Warn if any groups are unused (due to a typo, for example).
Peter Johnson
2008-10-02
1
-0
/
+7
*
Mark gen_x86_insn.py outputs as generated, to discourage hand-editing.
Peter Johnson
2008-09-10
1
-1
/
+7
*
Add support for newly specified AVX/AES instructions:
Peter Johnson
2008-08-13
1
-2
/
+38
*
Fix #137: LAR and LSL should only need 286+Prot CPU flags, not 386.
Peter Johnson
2008-04-29
1
-3
/
+2
*
Fix two instances of VERMIL2PS/PD incorrectly setting VEX.L=1.
Peter Johnson
2008-04-25
1
-2
/
+2
*
Fix register fields on FMA instructions.
Peter Johnson
2008-04-22
1
-11
/
+11
*
Fix a number of AVX instructions where VEX.vvvv was incorrectly being set
Peter Johnson
2008-04-21
1
-12
/
+68
*
Fix AVX instruction misnaming of new vptest variants:
Peter Johnson
2008-04-21
1
-2
/
+2
*
Add complete Intel Advanced Vector Extensions (AVX) support.
Peter Johnson
2008-04-11
1
-170
/
+1677
*
Move BITS==64 condition out of the CPU field (where it really doesn't belong)
Peter Johnson
2008-04-11
1
-36
/
+59
*
PCOMUcc should have been PCOMccU.
Peter Johnson
2008-04-04
1
-35
/
+45
*
Add mnenomic condition codes for SSE5 comparison opcodes.
Peter Johnson
2008-04-03
1
-0
/
+49
*
Add support for Nehalem XSAVE instructions and CPU feature.
Peter Johnson
2008-02-22
1
-0
/
+12
*
Revert r2029. According to both AMD64 and Intel 64 instruction set
Peter Johnson
2008-02-02
1
-6
/
+6
*
Don't generate 0x90 opcode for xchg rax, r8 and varieties thereof.
Peter Johnson
2008-01-28
1
-6
/
+6
*
Fix #129: Support no-operand form of movsd in GAS syntax.
Peter Johnson
2008-01-03
1
-1
/
+1
*
Fix #119. Quite a few SSE/SSE2 instructions assumed 128-bit memory sizes
Peter Johnson
2007-11-28
1
-154
/
+174
*
Add SSE5 (new AMD SSE) instructions support.
Peter Johnson
2007-09-16
1
-47
/
+380
*
Switch x86 operand storage from manual bitfields to C structure bitfields.
Peter Johnson
2007-09-13
1
-22
/
+9
*
Change modifiers from a prioritized shifted sequence into an ordered array.
Peter Johnson
2007-09-13
1
-55
/
+23
*
Add Id tag.
Peter Johnson
2007-09-12
1
-1
/
+1
*
Now that we have more cpu feature bits, properly document SSE4a as such.
Peter Johnson
2007-09-12
1
-8
/
+8
*
Restructure x86 CPU handling to allow for more than 30 CPU feature flags.
Peter Johnson
2007-09-12
1
-8
/
+41
*
Shrink the size of the x86_insn_info structure, particularly on 64-bit
Peter Johnson
2007-09-11
1
-8
/
+40
*
Change x86 instruction tables to be automatically generated.
Peter Johnson
2007-09-10
1
-0
/
+5284