diff options
| author | Peter Johnson <peter@tortall.net> | 2008-04-22 05:41:11 +0000 |
|---|---|---|
| committer | Peter Johnson <peter@tortall.net> | 2008-04-22 05:41:11 +0000 |
| commit | bf5716cbd7d9558eb298a3f07a1aa2ec7a4bc1db (patch) | |
| tree | b21f10cf1ce66e44fd1c5640f16e1ae1e1c0f149 /modules/arch/x86/gen_x86_insn.py | |
| parent | 3d2fb09a5f33774c3a6c0bd2cff12aacf0c14923 (diff) | |
| download | yasm-bf5716cbd7d9558eb298a3f07a1aa2ec7a4bc1db.tar.gz | |
Fix register fields on FMA instructions.
The FMA instructions swap VEX.vvvv and imm8[7:4] as compared to other AVX
instructions.
Reported by: nasm64developer@users.sf.net
svn path=/trunk/yasm/; revision=2071
Diffstat (limited to 'modules/arch/x86/gen_x86_insn.py')
| -rwxr-xr-x | modules/arch/x86/gen_x86_insn.py | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py index ef19a408..e52ca641 100755 --- a/modules/arch/x86/gen_x86_insn.py +++ b/modules/arch/x86/gen_x86_insn.py @@ -6374,9 +6374,9 @@ add_group("fma_128_256", prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), + Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"), - Operand(type="SIMDReg", size=128, dest="VEXImmSrc")]) + Operand(type="SIMDReg", size=128, dest="VEX")]) add_group("fma_128_256", cpu=["FMA"], modifiers=["Op2Add"], @@ -6385,8 +6385,8 @@ add_group("fma_128_256", prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), + Operand(type="SIMDReg", size=128, dest="VEX"), Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")]) add_group("fma_128_256", cpu=["FMA"], @@ -6396,9 +6396,9 @@ add_group("fma_128_256", prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=256, dest="Spare"), - Operand(type="SIMDReg", size=256, dest="VEX"), + Operand(type="SIMDReg", size=256, dest="VEXImmSrc"), Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"), - Operand(type="SIMDReg", size=256, dest="VEXImmSrc")]) + Operand(type="SIMDReg", size=256, dest="VEX")]) add_group("fma_128_256", cpu=["FMA"], modifiers=["Op2Add"], @@ -6407,8 +6407,8 @@ add_group("fma_128_256", prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=256, dest="Spare"), - Operand(type="SIMDReg", size=256, dest="VEX"), Operand(type="SIMDReg", size=256, dest="VEXImmSrc"), + Operand(type="SIMDReg", size=256, dest="VEX"), Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")]) add_insn("vfmaddpd", "fma_128_256", modifiers=[0x69]) @@ -6433,9 +6433,9 @@ for sz in [32, 64]: prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), + Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), Operand(type="SIMDReg", size=128, dest="EA"), - Operand(type="SIMDReg", size=128, dest="VEXImmSrc")]) + Operand(type="SIMDReg", size=128, dest="VEX")]) add_group("fma_128_m%d" % sz, cpu=["FMA"], modifiers=["Op2Add"], @@ -6444,9 +6444,9 @@ for sz in [32, 64]: prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), + Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), Operand(type="Mem", size=sz, relaxed=True, dest="EA"), - Operand(type="SIMDReg", size=128, dest="VEXImmSrc")]) + Operand(type="SIMDReg", size=128, dest="VEX")]) add_group("fma_128_m%d" % sz, cpu=["FMA"], modifiers=["Op2Add"], @@ -6455,8 +6455,8 @@ for sz in [32, 64]: prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), + Operand(type="SIMDReg", size=128, dest="VEX"), Operand(type="Mem", size=sz, relaxed=True, dest="EA")]) add_insn("vfmaddsd", "fma_128_m64", modifiers=[0x6B]) |