Add mnenomic condition codes for SSE5 comparison opcodes.

There are 16 condition codes for COM and 8 condition codes for PCOM/PCOMU.

Noticed by: nasm64developer@users.sf.net

svn path=/trunk/yasm/; revision=2048

4 files changed, 280 insertions, 0 deletions

diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index d850feed..da0f3012 100755
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -5019,11 +5019,48 @@ for sz in [32, 64]:
                   Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
                   Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
+# Condition code versions
+add_group("sse5comcc",
+    cpu=["SSE5"],
+    modifiers=["Op2Add", "Imm8"],
+    opcode=[0x0F, 0x25, 0x00],
+    drex_oc0=0,
+    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
+              Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+
+for sz in [32, 64]:
+    add_group("sse5comcc%d" % sz,
+        cpu=["SSE5"],
+        modifiers=["Op2Add", "Imm8"],
+        opcode=[0x0F, 0x25, 0x00],
+        drex_oc0=0,
+        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
+                  Operand(type="SIMDReg", size=128, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, dest="EA")])
+    add_group("sse5comcc%d" % sz,
+        cpu=["SSE5"],
+        modifiers=["Op2Add", "Imm8"],
+        opcode=[0x0F, 0x25, 0x00],
+        drex_oc0=0,
+        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
+                  Operand(type="SIMDReg", size=128, dest="Spare"),
+                  Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
+
 add_insn("comps", "sse5com", modifiers=[0x2C])
 add_insn("compd", "sse5com", modifiers=[0x2D])
 add_insn("comss", "sse5com32", modifiers=[0x2E])
 add_insn("comsd", "sse5com64", modifiers=[0x2F])
 
+for ib, cc in enumerate([  "eq",   "lt",   "le", "unord",
+                         "uneq", "unlt", "unle",   "ord",
+                          "ueq",  "ult",  "ule", "false",
+                          "neq",  "nlt",  "nle",  "true"]):
+    add_insn("com"+cc+"ps", "sse5comcc", modifiers=[0x2C, ib])
+    add_insn("com"+cc+"pd", "sse5comcc", modifiers=[0x2D, ib])
+    add_insn("com"+cc+"ss", "sse5comcc32", modifiers=[0x2E, ib])
+    add_insn("com"+cc+"sd", "sse5comcc64", modifiers=[0x2F, ib])
+
 add_insn("pcomb", "sse5com", modifiers=[0x4C])
 add_insn("pcomw", "sse5com", modifiers=[0x4D])
 add_insn("pcomd", "sse5com", modifiers=[0x4E])
@@ -5034,6 +5071,18 @@ add_insn("pcomuw", "sse5com", modifiers=[0x6D])
 add_insn("pcomud", "sse5com", modifiers=[0x6E])
 add_insn("pcomuq", "sse5com", modifiers=[0x6F])
 
+for ib, cc in enumerate(["lt", "le", "gt", "ge",
+                         "eq", "neq", "false", "true"]):
+    add_insn("pcom"+cc+"b", "sse5comcc", modifiers=[0x4C, ib])
+    add_insn("pcom"+cc+"w", "sse5comcc", modifiers=[0x4D, ib])
+    add_insn("pcom"+cc+"d", "sse5comcc", modifiers=[0x4E, ib])
+    add_insn("pcom"+cc+"q", "sse5comcc", modifiers=[0x4F, ib])
+
+    add_insn("pcomu"+cc+"b", "sse5comcc", modifiers=[0x6C, ib])
+    add_insn("pcomu"+cc+"w", "sse5comcc", modifiers=[0x6D, ib])
+    add_insn("pcomu"+cc+"d", "sse5comcc", modifiers=[0x6E, ib])
+    add_insn("pcomu"+cc+"q", "sse5comcc", modifiers=[0x6F, ib])
+
 add_group("cvtph2ps",
     cpu=["SSE5"],
     opcode=[0x0F, 0x7A, 0x30],
diff --git a/modules/arch/x86/tests/Makefile.inc b/modules/arch/x86/tests/Makefile.inc
index b500f419..09256a7d 100644
--- a/modules/arch/x86/tests/Makefile.inc
+++ b/modules/arch/x86/tests/Makefile.inc
@@ -170,6 +170,8 @@ EXTRA_DIST += modules/arch/x86/tests/sse5-all.asm
 EXTRA_DIST += modules/arch/x86/tests/sse5-all.hex
 EXTRA_DIST += modules/arch/x86/tests/sse5-basic.asm
 EXTRA_DIST += modules/arch/x86/tests/sse5-basic.hex
+EXTRA_DIST += modules/arch/x86/tests/sse5-cc.asm
+EXTRA_DIST += modules/arch/x86/tests/sse5-cc.hex
 EXTRA_DIST += modules/arch/x86/tests/sse5-err.asm
 EXTRA_DIST += modules/arch/x86/tests/sse5-err.errwarn
 EXTRA_DIST += modules/arch/x86/tests/ssewidth.asm
diff --git a/modules/arch/x86/tests/sse5-cc.asm b/modules/arch/x86/tests/sse5-cc.asm
new file mode 100644
index 00000000..6d778a6b
--- /dev/null
+++ b/modules/arch/x86/tests/sse5-cc.asm
@@ -0,0 +1,37 @@
+[bits 16]
+comeqpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 00
+comltpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 01
+comlepd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 02
+comunordpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 03
+comuneqpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 04
+comunltpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 05
+comunlepd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 06
+comordpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 07
+comueqpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 08
+comultpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 09
+comulepd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 0A
+comfalsepd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 0B
+comneqpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 0C
+comnltpd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 0D
+comnlepd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 0E
+comtruepd xmm1, xmm2, xmm3	; 0F 25 2D 323 10 0F
+
+pcomltb xmm1, xmm2, xmm3	; 0F 25 4C 323 10 00
+pcomleb xmm1, xmm2, xmm3	; 0F 25 4C 323 10 01
+pcomgtb xmm1, xmm2, xmm3	; 0F 25 4C 323 10 02
+pcomgeb xmm1, xmm2, xmm3	; 0F 25 4C 323 10 03
+pcomeqb xmm1, xmm2, xmm3	; 0F 25 4C 323 10 04
+pcomneqb xmm1, xmm2, xmm3	; 0F 25 4C 323 10 05
+pcomfalseb xmm1, xmm2, xmm3	; 0F 25 4C 323 10 06
+pcomtrueb xmm1, xmm2, xmm3	; 0F 25 4C 323 10 07
+
+pcomultb xmm1, xmm2, xmm3	; 0F 25 6C 323 10 00
+pcomuleb xmm1, xmm2, xmm3	; 0F 25 6C 323 10 01
+pcomugtb xmm1, xmm2, xmm3	; 0F 25 6C 323 10 02
+pcomugeb xmm1, xmm2, xmm3	; 0F 25 6C 323 10 03
+pcomueqb xmm1, xmm2, xmm3	; 0F 25 6C 323 10 04
+pcomuneqb xmm1, xmm2, xmm3	; 0F 25 6C 323 10 05
+pcomufalseb xmm1, xmm2, xmm3	; 0F 25 6C 323 10 06
+pcomutrueb xmm1, xmm2, xmm3	; 0F 25 6C 323 10 07
+
+
diff --git a/modules/arch/x86/tests/sse5-cc.hex b/modules/arch/x86/tests/sse5-cc.hex
new file mode 100644
index 00000000..f565535e
--- /dev/null
+++ b/modules/arch/x86/tests/sse5-cc.hex
@@ -0,0 +1,192 @@
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