diff options
| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2023-04-18 11:30:39 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-04-21 08:29:45 +0200 |
| commit | 3a3cd967288055777a692fabba7c94cf9259e500 (patch) | |
| tree | fa05223ae5cd3d32b95ba71f6fecd07c8da7f18f /include | |
| parent | cf0f1454dae5d9fbebc0e212cdf0a2090f2e64a5 (diff) | |
| download | barebox-3a3cd967288055777a692fabba7c94cf9259e500.tar.gz | |
mci: add eMMC DDR52 support
The maximum card frequency that can be configured by barebox currently
is 50MHz for SD and 52MHz for eMMC. Higher speed modes require runtime
voltage switching or tuning sequences, which are not yet implemented.
Only exception is eMMC's DDR52: This mode was first introduced with
MMC 4.4 and can be used even at 3.3V.
This commit adds DDR52 support to the core. This introduces no functional
change, because host controllers must opt-in by setting the appropriate
host capabilities. In cases where it's enabled, bus width determination
happens as usual and then if possible, the resulting bus width will be
attempted with DDR. If that fails, we revert back to SDR.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20230418093040.1865982-4-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/mci.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/mci.h b/include/mci.h index a3f6d619b3..3e93f378e4 100644 --- a/include/mci.h +++ b/include/mci.h @@ -51,6 +51,11 @@ #define MMC_CAP_SD_HIGHSPEED (1 << 3) #define MMC_CAP_MMC_HIGHSPEED (1 << 4) #define MMC_CAP_MMC_HIGHSPEED_52MHZ (1 << 5) +#define MMC_CAP_MMC_3_3V_DDR (1 << 7) /* Host supports eMMC DDR 3.3V */ +#define MMC_CAP_MMC_1_8V_DDR (1 << 8) /* Host supports eMMC DDR 1.8V */ +#define MMC_CAP_MMC_1_2V_DDR (1 << 9) /* Host supports eMMC DDR 1.2V */ +#define MMC_CAP_DDR (MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | \ + MMC_CAP_1_2V_DDR) /* Mask of all caps for bus width */ #define MMC_CAP_BIT_DATA_MASK (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA) @@ -308,6 +313,7 @@ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ +#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */ #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_STATUS(x) (x & 0xFFF9A000) @@ -410,6 +416,19 @@ enum mci_timing { MMC_TIMING_MMC_HS400 = 8, }; +static inline bool mci_timing_is_ddr(enum mci_timing timing) +{ + switch (timing) { + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_HS200: + case MMC_TIMING_MMC_DDR52: + case MMC_TIMING_MMC_HS400: + return true; + default: + return false; + } +} + enum mci_bus_width { MMC_BUS_WIDTH_1 = 0, MMC_BUS_WIDTH_4 = 2, |