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| author | Alan Modra <amodra@gmail.com> | 2004-03-16 00:59:35 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2004-03-16 00:59:35 +0000 |
| commit | 974a217561b92209b973f8f06ac35b3cf6502a86 (patch) | |
| tree | 47b64ba7f50ef41611dc62324400aaca2a08ab16 /ld/testsuite/ld-powerpc/tlsexe32.d | |
| parent | 443600310d5b32102bfaa0495b4ee6a227933bb7 (diff) | |
| download | binutils-gdb-974a217561b92209b973f8f06ac35b3cf6502a86.tar.gz | |
opcodes/
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
Diffstat (limited to 'ld/testsuite/ld-powerpc/tlsexe32.d')
| -rw-r--r-- | ld/testsuite/ld-powerpc/tlsexe32.d | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/ld/testsuite/ld-powerpc/tlsexe32.d b/ld/testsuite/ld-powerpc/tlsexe32.d index 9bd8221f22a..4aea8f061c2 100644 --- a/ld/testsuite/ld-powerpc/tlsexe32.d +++ b/ld/testsuite/ld-powerpc/tlsexe32.d @@ -9,34 +9,34 @@ Disassembly of section \.text: 0180028c <_start>: - 180028c: 80 7f 00 0c lwz r3,12\(r31\) - 1800290: 7c 63 12 14 add r3,r3,r2 - 1800294: 38 7f 00 10 addi r3,r31,16 - 1800298: 48 01 01 85 bl 181041c .* - 180029c: 3c 62 00 00 addis r3,r2,0 - 18002a0: 38 63 90 1c addi r3,r3,-28644 - 18002a4: 3c 62 00 00 addis r3,r2,0 - 18002a8: 38 63 10 00 addi r3,r3,4096 - 18002ac: 39 23 80 20 addi r9,r3,-32736 - 18002b0: 3d 23 00 00 addis r9,r3,0 - 18002b4: 81 49 80 24 lwz r10,-32732\(r9\) - 18002b8: 3d 22 00 00 addis r9,r2,0 - 18002bc: a1 49 90 2c lhz r10,-28628\(r9\) - 18002c0: 89 42 90 30 lbz r10,-28624\(r2\) - 18002c4: 3d 22 00 00 addis r9,r2,0 - 18002c8: 99 49 90 34 stb r10,-28620\(r9\) - 18002cc: 3c 62 00 00 addis r3,r2,0 - 18002d0: 38 63 90 00 addi r3,r3,-28672 - 18002d4: 3c 62 00 00 addis r3,r2,0 - 18002d8: 38 63 10 00 addi r3,r3,4096 - 18002dc: 91 43 80 04 stw r10,-32764\(r3\) - 18002e0: 3d 23 00 00 addis r9,r3,0 - 18002e4: 91 49 80 08 stw r10,-32760\(r9\) - 18002e8: 3d 22 00 00 addis r9,r2,0 - 18002ec: b1 49 90 2c sth r10,-28628\(r9\) - 18002f0: a1 42 90 14 lhz r10,-28652\(r2\) - 18002f4: 3d 22 00 00 addis r9,r2,0 - 18002f8: a9 49 90 18 lha r10,-28648\(r9\) + 180028c: 80 7f 00 0c lwz r3,12\(r31\) + 1800290: 7c 63 12 14 add r3,r3,r2 + 1800294: 38 7f 00 10 addi r3,r31,16 + 1800298: 48 01 01 85 bl 181041c .* + 180029c: 3c 62 00 00 addis r3,r2,0 + 18002a0: 38 63 90 1c addi r3,r3,-28644 + 18002a4: 3c 62 00 00 addis r3,r2,0 + 18002a8: 38 63 10 00 addi r3,r3,4096 + 18002ac: 39 23 80 20 addi r9,r3,-32736 + 18002b0: 3d 23 00 00 addis r9,r3,0 + 18002b4: 81 49 80 24 lwz r10,-32732\(r9\) + 18002b8: 3d 22 00 00 addis r9,r2,0 + 18002bc: a1 49 90 2c lhz r10,-28628\(r9\) + 18002c0: 89 42 90 30 lbz r10,-28624\(r2\) + 18002c4: 3d 22 00 00 addis r9,r2,0 + 18002c8: 99 49 90 34 stb r10,-28620\(r9\) + 18002cc: 3c 62 00 00 addis r3,r2,0 + 18002d0: 38 63 90 00 addi r3,r3,-28672 + 18002d4: 3c 62 00 00 addis r3,r2,0 + 18002d8: 38 63 10 00 addi r3,r3,4096 + 18002dc: 91 43 80 04 stw r10,-32764\(r3\) + 18002e0: 3d 23 00 00 addis r9,r3,0 + 18002e4: 91 49 80 08 stw r10,-32760\(r9\) + 18002e8: 3d 22 00 00 addis r9,r2,0 + 18002ec: b1 49 90 2c sth r10,-28628\(r9\) + 18002f0: a1 42 90 14 lhz r10,-28652\(r2\) + 18002f4: 3d 22 00 00 addis r9,r2,0 + 18002f8: a9 49 90 18 lha r10,-28648\(r9\) Disassembly of section \.got: 018103b8 <\.got>: |