diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 03:11:32 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-15 01:49:23 -0500 |
| commit | 29fd199ed8eb33df997a8ce74a8c9b623d811006 (patch) | |
| tree | 1365cc73947682282333966ccd73d515c31d1d99 /sim/testsuite/sim | |
| parent | 137d6efd8aaee18ebb4d23a13fcaa4ef0688f1ab (diff) | |
| download | binutils-gdb-29fd199ed8eb33df997a8ce74a8c9b623d811006.tar.gz | |
sim: d10v: relocate tests & clean up test harness
This is the only target using a dir directly under testsuite/. All
others use sim/<arch>/ instead. Relocate it so all targets look the
same, and so we can leverage the common test harness.
We drop loop.s in the process because it was never referenced and
was just 2 lines of code.
All other test files are moved & have directives added to the top so
that the test harness can invoke them correctly.
Diffstat (limited to 'sim/testsuite/sim')
50 files changed, 1810 insertions, 0 deletions
diff --git a/sim/testsuite/sim/d10v/ChangeLog b/sim/testsuite/sim/d10v/ChangeLog new file mode 100644 index 00000000000..5ca891021e6 --- /dev/null +++ b/sim/testsuite/sim/d10v/ChangeLog @@ -0,0 +1,144 @@ +2021-01-15 Mike Frysinger <vapier@gentoo.org> + + * allinsn.exp: New file. + * configure, configure.ac, loop.s, Makefile.in: Deleted. + +2020-10-06 Andrew Burgess <andrew.burgess@embecosm.com> + + * configure: Regnerate. + * configure.ac (AC_CONFIG_AUX_DIR): Update. + +2015-03-30 Mike Frysinger <vapier@gentoo.org> + + * Makefile.in (RUNFLAGS_FOR_TARGET): Set to --environment operating. + +2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> + + * configure: Regenerate. + +2005-01-07 Andrew Cagney <cagney@gnu.org> + + * configure.ac: Rename configure.in, require autoconf 2.59. + * configure: Re-generate. + +Tue Apr 18 16:32:07 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * t-rie-xx.s (test_rie_xx): New test. + * Makefile.in (TESTS): Update. + +Tue Feb 22 17:36:34 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * Makefile.in: Force d10v into operating mode. + +Mon Jan 3 00:17:28 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * t-ae-ld-d.s, t-ae-ld-i.s, t-ae-ld-id.s, t-ae-ld-im.s , + t-ae-ld-ip.s, t-ae-ld2w-d.s, t-ae-ld2w-i.s, t-ae-ld2w-id.s , + t-ae-ld2w-im.s, t-ae-ld2w-ip.s, t-ae-st-d.s, t-ae-st-i.s , + t-ae-st-id.s, t-ae-st-im.s, t-ae-st-ip.s, t-ae-st-is.s , + t-ae-st2w-d.s, t-ae-st2w-i.s, t-ae-st2w-id.s, t-ae-st2w-im.s , + t-ae-st2w-ip.s, t-ae-st2w-is.s: New tests. Check that an address + exception occures when a word/two-word load/store is not word + aligned. + * Makefile.in (TESTS): Update. + +Fri Oct 29 18:36:34 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * t-mvtc.s: Check that the user can not modify the DM bit in the + BPSW or DPSW. + +Thu Oct 28 01:47:26 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * t-mvtc.s: Update. Check that user can not modify DM bit. + +Wed Sep 8 19:34:55 MDT 1999 Diego Novillo <dnovillo@cygnus.com> + + * t-ld-st.s: New file. + * t-sac.s: New file. + * t-sachi.s: New file. + * t-slae.s: New file. + +1999-01-13 Jason Molenda (jsm@bugshack.cygnus.com) + + * t-sadd.s: New file. + * Makefile.in (TESTS): Add t-sadd. + +Mon Feb 16 09:20:57 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * t-macros.i (VEC_*): Define. + (DMAP_REG, DMAP_BASE, DMAP_MASK): Define. + (IMAP[01]_REG): Define. + + * t-rdt.s (test_tdt): New file. + + * t-dbt.s (test_dbt): New file. + + * Makefile.in (TESTS): Add t-rdt and t-dbt. + + +Fri Feb 13 16:21:13 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * t-sp.s: New test. + * Makefile.in (TESTS): Update. + +Wed Feb 11 17:58:50 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * t-macros.i: Update trap calls, func in r4, args in + r0... + (start): Force r0 to zero. + + * t-sub2w.s: Ditto. + +Tue Dec 9 10:41:44 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-rte.s (success): New file. + * Makefile.in: Update. + + * t-rep.s: Check rep repeats correct number of times. + +Fri Dec 5 10:11:18 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S. + + * t-trap.s: New file. + * Makefile.in (TESTS): Update. + +Thu Dec 4 16:56:55 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-macros.i: Add definitions for PSW bits. + + * t-mvtc.s: New file. + * Makefile.in (TESTS): Update. + +Wed Dec 3 16:35:24 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-rac.s: New files. + + * t-macros.i: Add macros for checking psw and 2w quantities. + + * Makefile.in (TESTS): Update. + +Tue Dec 2 11:01:36 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New + files. + + * Makefile.in: Update. + +Mon Nov 17 20:14:48 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-subi.s (test_subi): New file. + * Makefile.in: Update. + +Fri Nov 14 14:06:06 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-rep.s: New file. Test case of branch to RPT_E address. + +Mon Nov 10 19:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * t-macros.i (_start): New file. + * t-rachi.s: New file. + + * Makefile.in (RUN_FOR_TARGET): Look for simulator in d10v + directory. + diff --git a/sim/testsuite/sim/d10v/allinsn.exp b/sim/testsuite/sim/d10v/allinsn.exp new file mode 100644 index 00000000000..123509a3b99 --- /dev/null +++ b/sim/testsuite/sim/d10v/allinsn.exp @@ -0,0 +1,17 @@ +# d10v simulator testsuite. + +if [istarget d10v*-*] { + # load support procs (none yet) + # load_lib cgen.exp + # all machines + set all_machs "d10v" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/d10v/exit47.s b/sim/testsuite/sim/d10v/exit47.s new file mode 100644 index 00000000000..8f2a6ee8003 --- /dev/null +++ b/sim/testsuite/sim/d10v/exit47.s @@ -0,0 +1,8 @@ +# mach: all +# status: 47 +# output: + +.include "t-macros.i" + + start + exit47 diff --git a/sim/testsuite/sim/d10v/hello.s b/sim/testsuite/sim/d10v/hello.s new file mode 100644 index 00000000000..3e3557d7eb8 --- /dev/null +++ b/sim/testsuite/sim/d10v/hello.s @@ -0,0 +1,8 @@ +# mach: all +# output: Hello World!\n + + .include "t-macros.i" + + start + hello + exit0 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-d.s b/sim/testsuite/sim/d10v/t-ae-ld-d.s new file mode 100644 index 00000000000..511fbb072cf --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld-d.s @@ -0,0 +1,17 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ld r8,@0x4000 +test_ld: + ld r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-i.s b/sim/testsuite/sim/d10v/t-ae-ld-i.s new file mode 100644 index 00000000000..b9d10d16140 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld-i.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4000 + ld r8, @r10 + + ldi r10, #0x4001 +test_ld: + ld r8,@r10 + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-id.s b/sim/testsuite/sim/d10v/t-ae-ld-id.s new file mode 100644 index 00000000000..ed86525d213 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld-id.s @@ -0,0 +1,19 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4001 + ld r8, @(1,r10) + +test_ld: + ld r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-im.s b/sim/testsuite/sim/d10v/t-ae-ld-im.s new file mode 100644 index 00000000000..42f87161876 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld-im.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4000 + ld r8, @r10- + + ldi r10, #0x4001 +test_ld: + ld r8,@r10- + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld-ip.s b/sim/testsuite/sim/d10v/t-ae-ld-ip.s new file mode 100644 index 00000000000..c163912ce5b --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld-ip.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4000 + ld r8, @r10+ + + ldi r10, #0x4001 +test_ld: + ld r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-d.s b/sim/testsuite/sim/d10v/t-ae-ld2w-d.s new file mode 100644 index 00000000000..1c81594f7ab --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld2w-d.s @@ -0,0 +1,17 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ld2w r8,@0x4000 +test_ld2w: + ld2w r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-i.s b/sim/testsuite/sim/d10v/t-ae-ld2w-i.s new file mode 100644 index 00000000000..9547870fa43 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld2w-i.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4000 + ld2w r8, @r10 + + ldi r10, #0x4001 +test_ld2w: + ld2w r8,@r10 + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-id.s b/sim/testsuite/sim/d10v/t-ae-ld2w-id.s new file mode 100644 index 00000000000..2766388f188 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld2w-id.s @@ -0,0 +1,18 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4001 + ld2w r8,@(1,r10) +test_ld2w: + ld2w r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-im.s b/sim/testsuite/sim/d10v/t-ae-ld2w-im.s new file mode 100644 index 00000000000..c6946f3a998 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld2w-im.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4000 + ld2w r8, @r10- + + ldi r10, #0x4001 +test_ld2w: + ld2w r8,@r10- + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-ld2w-ip.s b/sim/testsuite/sim/d10v/t-ae-ld2w-ip.s new file mode 100644 index 00000000000..6214853d7d5 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-ld2w-ip.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4000 + ld2w r8, @r10+ + + ldi r10, #0x4001 +test_ld2w: + ld2w r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-d.s b/sim/testsuite/sim/d10v/t-ae-st-d.s new file mode 100644 index 00000000000..99bd724b5d1 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st-d.s @@ -0,0 +1,17 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + st r8,@0x4000 +test_st: + st r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-i.s b/sim/testsuite/sim/d10v/t-ae-st-i.s new file mode 100644 index 00000000000..5f0f9b44c41 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st-i.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4000 + st r8, @r10 + + ldi r10,#0x4001 +test_st: + st r8,@r10 + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-id.s b/sim/testsuite/sim/d10v/t-ae-st-id.s new file mode 100644 index 00000000000..9620fce1a0b --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st-id.s @@ -0,0 +1,18 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4001 + st r8, @(1,r10) +test_st: + st r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-im.s b/sim/testsuite/sim/d10v/t-ae-st-im.s new file mode 100644 index 00000000000..0318243a8d4 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st-im.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4000 + st r8, @r10- + + ldi r10,#0x4001 +test_st: + st r8,@r10- + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-ip.s b/sim/testsuite/sim/d10v/t-ae-st-ip.s new file mode 100644 index 00000000000..78d9a1d7994 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st-ip.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4000 + st r8, @r10+ + + ldi r10,#0x4001 +test_st: + st r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st-is.s b/sim/testsuite/sim/d10v/t-ae-st-is.s new file mode 100644 index 00000000000..08e1d7e5f3d --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st-is.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi sp,#0x4000 + st r8, @-SP + + ldi sp,#0x4001 +test_st: + st r8,@-SP + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-d.s b/sim/testsuite/sim/d10v/t-ae-st2w-d.s new file mode 100644 index 00000000000..6f07a997581 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st2w-d.s @@ -0,0 +1,17 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + st2w r8,@0x4000 +test_st2w: + st2w r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-i.s b/sim/testsuite/sim/d10v/t-ae-st2w-i.s new file mode 100644 index 00000000000..a629b759715 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st2w-i.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4000 + st2w r8, @r10 + + ldi r10, #0x4001 +test_st2w: + st2w r8,@r10 + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-id.s b/sim/testsuite/sim/d10v/t-ae-st2w-id.s new file mode 100644 index 00000000000..91f231978d0 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st2w-id.s @@ -0,0 +1,18 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4001 + st2w r8, @(1,r10) +test_st2w: + st2w r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-im.s b/sim/testsuite/sim/d10v/t-ae-st2w-im.s new file mode 100644 index 00000000000..f8cc7fb45fb --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st2w-im.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4000 + st2w r8, @r10- + + ldi r10, #0x4001 +test_st2w: + st2w r8,@r10- + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-ip.s b/sim/testsuite/sim/d10v/t-ae-st2w-ip.s new file mode 100644 index 00000000000..63c5abd5bd0 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st2w-ip.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4000 + st2w r8, @r10+ + + ldi r10, #0x4001 +test_st2w: + st2w r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-ae-st2w-is.s b/sim/testsuite/sim/d10v/t-ae-st2w-is.s new file mode 100644 index 00000000000..190ab4223a0 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ae-st2w-is.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi sp, #0x4004 + st2w r8, @-SP + + ldi sp, #0x4005 +test_st2w: + st2w r8,@-SP + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-dbt.s b/sim/testsuite/sim/d10v/t-dbt.s new file mode 100644 index 00000000000..9b405b09c83 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-dbt.s @@ -0,0 +1,38 @@ +# mach: all +# output: +# sim: --environment operating +# as: -W + +.include "t-macros.i" + + start + + PSW_BITS = PSW_DM + +;;; Blat our DMAP registers so that they point at on-chip imem + + ldi r2, MAP_INSN | 0xf + st r2, @(DMAP_REG,r0) + ldi r2, MAP_INSN + st r2, @(IMAP1_REG,r0) + +;;; Patch the interrupt vector's dbt entry with a jmp to success + + ldi r4, #trap + ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE + ld2w r2, @(0,r4) + st2w r2, @(0,r5) + ld2w r2, @(4,r4) + st2w r2, @(4,r5) + +test_dbt: + dbt -> nop + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 + + .data +trap: ldi r1, success@word + jmp r1 diff --git a/sim/testsuite/sim/d10v/t-ld-st.s b/sim/testsuite/sim/d10v/t-ld-st.s new file mode 100644 index 00000000000..4ae4f852e56 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-ld-st.s @@ -0,0 +1,36 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ; Test ld and st + ld r4, @foo + check 1 r4 0xdead + + ldi r4, #0x2152 + st r4, @foo + ld r4, @foo + check 2 r4 0x2152 + + ; Test ld2w and st2w + ldi r4, #0xdead + st r4, @foo + ld2w r4, @foo + check2w2 3 r4 0xdead 0xf000 + + ldi r4, #0x2112 + ldi r5, #0x1984 + st2w r4, @foo + ld2w r4, @foo + check2w2 4 r4 0x2112 0x1984 + + .data + .align 2 +foo: .short 0xdead +bar: .short 0xf000 + .text + + exit0 diff --git a/sim/testsuite/sim/d10v/t-mac.s b/sim/testsuite/sim/d10v/t-mac.s new file mode 100644 index 00000000000..1b6e660c536 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-mac.s @@ -0,0 +1,75 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ;; clear FX + loadpsw2 0x8005 + loadacc2 a1 0x7f 0xffff 0xffff + load r8 0xffff + load r9 0x8001 +test_macu1: + MACU a1, r9, r8 + checkacc2 1 a1 0x80 0x8000 0x7FFE + + ;; set FX + loadpsw2 0x8085 + loadacc2 a1 0x7f 0xffff 0xffff + load r8 0xffff + load r9 0x8001 +test_macu2: + MACU a1, r9, r8 + checkacc2 2 a1 0x81 0x0000 0xfffd + + + + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, #0xffff + ldi r9, #0x7FFF +test_macsu1: + MACSU a1, r9, r8 + checkacc2 3 a1 0x80 0x7FFE 0x8000 + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, #0xffff + ldi r9, #0x7FFF +test_macsu2: + MACSU a1, r9, r8 + checkacc2 4 a1 0x80 0xfffd 0x0001 + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_macsu3: + MACSU a1, r9, r8 + checkacc2 5 a1 0x7F 0x8001 0x7FFE + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, #0xffff + ldi r9, #0x8001 +test_macsu4: + MACSU a1, r9, r8 + checkacc2 6 a1 0x7f 0x0002 0xFFFD + + exit0 + diff --git a/sim/testsuite/sim/d10v/t-macros.i b/sim/testsuite/sim/d10v/t-macros.i new file mode 100644 index 00000000000..d6e155ce232 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-macros.i @@ -0,0 +1,235 @@ +# mach: d10v +# output: +# sim: --environment operating + + .macro start + .text + .align 2 + .globl _start +_start: + ldi r0, 0 + .endm + + + .macro exit47 + ldi r4, 1 + ldi r0, 47 + trap 15 + .endm + + + .macro exit0 + ldi r4, 1 + ldi r0, 0 + trap 15 + .endm + + + .macro exit1 + ldi r4, 1 + ldi r0, 1 + trap 15 + .endm + + + .macro exit2 + ldi r4, 1 + ldi r0, 2 + trap 15 + .endm + + + .macro load reg val + ldi \reg, #\val + .endm + + + .macro load2w reg hi lo + ld2w \reg, @(1f,r0) + .data + .align 2 +1: .short \hi + .short \lo + .text + .endm + + + .macro check exit reg val + cmpeqi \reg, #\val + brf0t 1f +0: ldi r4, 1 + ldi r0, \exit + trap 15 +1: + .endm + + + .macro check2w2 exit reg hi lo + st2w \reg, @(1f,r0) + ld r2, @(1f, r0) + cmpeqi r2, #\hi + brf0f 0f + ld r2, @(1f + 2, r0) + cmpeqi r2, #\lo + brf0f 0f + bra 2f +0: ldi r4, 1 + ldi r0, \exit + trap 15 + .data + .align 2 +1: .long 0 + .text +2: + .endm + + + .macro loadacc2 acc guard hi lo + ldi r2, #\lo + mvtaclo r2, \acc + ldi r2, #\hi + mvtachi r2, \acc + ldi r2, #\guard + mvtacg r2, \acc + .endm + + + .macro checkacc2 exit acc guard hi lo + ldi r2, #\guard + mvfacg r3, \acc + cmpeq r2, r3 + brf0f 0f + ldi r2, #\hi + mvfachi r3, \acc + cmpeq r2, r3 + brf0f 0f + ldi r2, #\lo + mvfaclo r3, \acc + cmpeq r2, r3 + brf0f 0f + bra 4f +0: ldi r4, 1 + ldi r0, \exit + trap 15 +4: + .endm + + + .macro loadpsw2 val + ldi r2, #\val + mvtc r2, cr0 + .endm + + + .macro checkpsw2 exit val + mvfc r2, cr0 + cmpeqi r2, #\val + brf0t 1f + ldi r4, 1 + ldi r0, \exit + trap 15 +1: + .endm + + + .macro hello + ;; 4:write (1, string, strlen (string)) + ldi r4, 4 + ldi r0, 1 + ldi r1, 1f + ldi r2, 2f-1f-1 + trap 15 + .section .rodata +1: .string "Hello World!\n" +2: .align 2 + .text + .endm + + +;;; Blat our DMAP registers so that they point at on-chip imem + .macro point_dmap_at_imem + .text + ldi r2, MAP_INSN | 0xf + st r2, @(DMAP_REG,r0) + ldi r2, MAP_INSN + st r2, @(IMAP1_REG,r0) + .endm + +;;; Patch VEC so that it jumps back to code that checks PSW +;;; and then exits with success. + .macro check_interrupt vec psw src +;;; Patch the interrupt vector's AE entry with a jmp to success + .text + ldi r4, #1f + ldi r5, \vec + ;; + ld2w r2, @(0,r4) + st2w r2, @(0,r5) + ld2w r2, @(4,r4) + st2w r2, @(4,r5) + ;; + bra 9f + nop +;;; Code that gets patched into the interrupt vector + .data +1: ldi r1, 2f@word + jmp r1 +;;; Successfull trap jumps back to here + .text +;;; Verify the PSW +2: mvfc r2, cr0 + cmpeqi r2, #\psw + brf0t 3f + nop + exit1 +;;; Verify the original addr +3: mvfc r2, bpc + cmpeqi r2, #\src@word + brf0t 4f + exit2 +4: exit0 +;;; continue as normal +9: + .endm + + + PSW_SM = 0x8000 + PSW_01 = 0x4000 + PSW_EA = 0x2000 + PSW_DB = 0x1000 + PSW_DM = 0x0800 + PSW_IE = 0x0400 + PSW_RP = 0x0200 + PSW_MD = 0x0100 + PSW_FX = 0x0080 + PSW_ST = 0x0040 + PSW_10 = 0x0020 + PSW_11 = 0x0010 + PSW_F0 = 0x0008 + PSW_F1 = 0x0004 + PSW_14 = 0x0002 + PSW_C = 0x0001 + + +;;; + + DMAP_MASK = 0x3fff + DMAP_BASE = 0x8000 + DMAP_REG = 0xff04 + + IMAP0_REG = 0xff00 + IMAP1_REG = 0xff02 + + MAP_INSN = 0x1000 + +;;; + + VEC_RI = 0x3ff00 + VEC_BAE = 0x3ff04 + VEC_RIE = 0x3ff08 + VEC_AE = 0x3ff0c + VEC_TRAP = 0x3ff10 + VEC_DBT = 0x3ff50 + VEC_SDBT = 0x3fff4 + VEC_DBI = 0x3ff58 + VEC_EI = 0x3ff5c diff --git a/sim/testsuite/sim/d10v/t-mod-ld-pre.s b/sim/testsuite/sim/d10v/t-mod-ld-pre.s new file mode 100644 index 00000000000..7d75af2b877 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-mod-ld-pre.s @@ -0,0 +1,126 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + mvfc r0, PSW || ldi.s r14, #0 + ldi.l r2, 0x100 ; MOD_E + ldi.l r3, 0x108 ; MOD_S + +test_mod_dec_ld: + mvtc r2, MOD_E || bseti r0, #7 + mvtc r3, MOD_S + mvtc r0, PSW ; modulo mode enable + mv r1,r3 ; r1=0x108 + ld r4, @r1- || nop ; r1=0x106 + ld r4, @r1- || nop ; r1=0x104 + ld r4, @r1- || nop ; r1=0x102 + ld r4, @r1- || nop ; r1=0x100 + ld r4, @r1- || nop ; r1=0x108 + ld r4, @r1- || nop ; r1=0x106 + + cmpeqi r1,#0x106 + brf0f _ERR ; branch to error + +test_mod_inc_ld: + mvtc r2, MOD_S + mvtc r3, MOD_E + mv r1,r2 ; r1=0x100 + ld r4, @r1+ || nop ; r1=0x102 + ld r4, @r1+ || nop ; r1=0x104 + ld r4, @r1+ || nop ; r1=0x106 + ld r4, @r1+ || nop ; r1=0x108 + ld r4, @r1+ || nop ; r1=0x100 + ld r4, @r1+ || nop ; r1=0x102 + + cmpeqi r1,#0x102 + brf0f _ERR + +test_mod_dec_ld2w: + mvtc r2, MOD_E + mvtc r3, MOD_S + mv r1,r3 ; r1=0x108 + ld2W r4, @r1- || nop ; r1=0x104 + ld2W r4, @r1- || nop ; r1=0x100 + ld2W r4, @r1- || nop ; r1=0x108 + ld2W r4, @r1- || nop ; r1=0x104 + + cmpeqi r1,#0x104 + brf0f _ERR ; <= branch to error + +test_mod_inc_ld2w: + mvtc r2, MOD_S + mvtc r3, MOD_E || BCLRI r0, #7 + mv r1,r2 ; r1=0x100 + ld2W r4, @r1+ || nop ; r1=0x104 + ld2W r4, @r1+ || nop ; r1=0x108 + ld2W r4, @r1+ || nop ; r1=0x100 + ld2W r4, @r1+ || nop ; r1=0x104 + + cmpeqi r1,#0x104 + brf0f _ERR + +test_mod_dec_ld_dis: + mvtc r0, PSW ; modulo mode disable + mvtc r2, MOD_E + mvtc r3, MOD_S + mv r1,r3 ; r1=0x108 + ld r4, @r1- || nop ; r1=0x106 + ld r4, @r1- || nop ; r1=0x104 + ld r4, @r1- || nop ; r1=0x102 + ld r4, @r1- || nop ; r1=0x100 + ld r4, @r1- || nop ; r1=0xFE + ld r4, @r1- || nop ; r1=0xFC + + cmpeqi r1,#0xFC + brf0f _ERR + +test_mod_inc_ld_dis: + mvtc r2, MOD_S + mvtc r3, MOD_E + mv r1,r2 ; r1=0x100 + ld r4, @r1+ || nop ; r1=0x102 + ld r4, @r1+ || nop ; r1=0x104 + ld r4, @r1+ || nop ; r1=0x106 + ld r4, @r1+ || nop ; r1=0x108 + ld r4, @r1+ || nop ; r1=0x10A + ld r4, @r1+ || nop ; r1=0x10C + + cmpeqi r1,#0x10C + brf0f _ERR + +test_mod_dec_ld2w_dis: + mvtc r2, MOD_E + mvtc r3, MOD_S + mv r1,r3 ; r1=0x108 + ld2W r4, @r1- || nop ; r1=0x104 + ld2W r4, @r1- || nop ; r1=0x100 + ld2W r4, @r1- || nop ; r1=0xFC + ld2W r4, @r1- || nop ; r1=0xF8 + + cmpeqi r1,#0xF8 + brf0f _ERR + + test_mod_inc_ld2w_dis: + mvtc r2, MOD_S + mvtc r3, MOD_E + mv r1,r2 ; r1=0x100 + ld2W r4, @r1+ || nop ; r1=0x104 + ld2W r4, @r1+ || nop ; r1=0x108 + ld2W r4, @r1+ || nop ; r1=0x10C + ld2W r4, @r1+ || nop ; r1=0x110 + + cmpeqi r1,#0x110 + brf0f _ERR + +_OK: + exit0 + +_ERR: + exit47 + + + diff --git a/sim/testsuite/sim/d10v/t-msbu.s b/sim/testsuite/sim/d10v/t-msbu.s new file mode 100644 index 00000000000..93b65a53979 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-msbu.s @@ -0,0 +1,32 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_msbu1: + MSBU a1, r9, r8 + checkacc2 1 a1 0X7F 0x7FFF 0x8000 + + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_msbu2: + MSBU a1, r9, r8 + checkacc2 2 a1 0X7E 0xFFFF 0x0001 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-mulxu.s b/sim/testsuite/sim/d10v/t-mulxu.s new file mode 100644 index 00000000000..b0c14b6d6da --- /dev/null +++ b/sim/testsuite/sim/d10v/t-mulxu.s @@ -0,0 +1,32 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ;; clear FX + ldi r2, #0x8005 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_mulxu1: + MULXU a1, r9, r8 + checkacc2 1 a1 0x00 0x8000 0x7FFF + + + ;; set FX + ldi r2, #0x8085 + mvtc r2, cr0 + + loadacc2 a1 0x7f 0xffff 0xffff + ldi r8, 0xffff + ldi r9, 0x8001 +test_mulxu2: + MULXU a1, r9, r8 + checkacc2 2 a1 0x01 0x0000 0xFFFE + + exit0 diff --git a/sim/testsuite/sim/d10v/t-mvtac.s b/sim/testsuite/sim/d10v/t-mvtac.s new file mode 100644 index 00000000000..dc73403192d --- /dev/null +++ b/sim/testsuite/sim/d10v/t-mvtac.s @@ -0,0 +1,23 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ldi r8, 0xbeef + mvtaclo r8, a0 + checkacc2 1 a0 0xff 0xffff 0xbeef + + mvtacg r0, a0 + checkacc2 2 a0 0x00 0xffff 0xbeef + + ldi r8, 0xdead + mvtachi r8, a0 + checkacc2 3 a0 0xff 0xdead 0xbeef + + loadacc2 a1 0xfe 0xbeef 0xdead + checkacc2 4 a1 0xfe 0xbeef 0xdead + + exit0 diff --git a/sim/testsuite/sim/d10v/t-mvtc.s b/sim/testsuite/sim/d10v/t-mvtc.s new file mode 100644 index 00000000000..0b463ae935f --- /dev/null +++ b/sim/testsuite/sim/d10v/t-mvtc.s @@ -0,0 +1,134 @@ +# mach: all +# output: +# sim: --environment operating +# as: -W + +.include "t-macros.i" + + start + +;;; Try out each bit in the PSW + + loadpsw2 PSW_SM + checkpsw2 1 PSW_SM + + loadpsw2 PSW_01 + checkpsw2 2 0 ;; PSW_01 + + loadpsw2 PSW_EA + checkpsw2 3 PSW_EA + + loadpsw2 PSW_DB + checkpsw2 4 PSW_DB + + loadpsw2 PSW_DM + checkpsw2 5 0 ;; PSW_DM + + loadpsw2 PSW_IE + checkpsw2 6 PSW_IE + + loadpsw2 PSW_RP + checkpsw2 7 PSW_RP + + loadpsw2 PSW_MD + checkpsw2 8 PSW_MD + + loadpsw2 PSW_FX|PSW_ST + checkpsw2 9 PSW_FX|PSW_ST + + ;; loadpsw2 PSW_ST + ;; checkpsw2 10 + + loadpsw2 PSW_10 + checkpsw2 11 0 ;; PSW_10 + + loadpsw2 PSW_11 + checkpsw2 12 0 ;; PSW_11 + + loadpsw2 PSW_F0 + checkpsw2 13 PSW_F0 + + loadpsw2 PSW_F1 + checkpsw2 14 PSW_F1 + + loadpsw2 PSW_14 + checkpsw2 15 0 ;; PSW_14 + + loadpsw2 PSW_C + checkpsw2 16 PSW_C + + +;;; Check that bit 0 (LSB) of the MOD_E & MOD_S registers are stuck at ZERO. + + ldi r6, #0xdead + mvtc r6, cr10 + ldi r6, #0xbeef + mvtc r6, cr11 + + mvfc r7, cr10 + check 17 r7 0xdeac + mvfc r7, cr11 + check 18 r7 0xbeee + +;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero + +psw_ffff: + ldi r6, 0xffff + mvtc r6, psw + mvfc r7, psw + check 18 r7 0xb7cd + +bpsw_ffff: + ldi r6, 0xffff + mvtc r6, bpsw + mvfc r7, bpsw + check 18 r7 0xb7cd + +dpsw_ffff: + ldi r6, 0xffff + mvtc r6, dpsw + mvfc r7, dpsw + check 18 r7 0xb7cd + +;;; Another check. Very similar + +psw_dfff: + ldi r6, 0xdfff + mvtc r6, psw + mvfc r7, psw + check 18 r7 0x97cd + +bpsw_dfff: + ldi r6, 0xdfff + mvtc r6, bpsw + mvfc r7, bpsw + check 18 r7 0x97cd + +dpsw_dfff: + ldi r6, 0xdfff + mvtc r6, dpsw + mvfc r7, dpsw + check 18 r7 0x97cd + +;;; And again. + +psw_8005: + ldi r6, 0x8005 + mvtc r6, psw + mvfc r7, psw + check 18 r7 0x8005 + +bpsw_8005: + ldi r6, 0x8005 + mvtc r6, bpsw + mvfc r7, bpsw + check 18 r7 0x8005 + +dpsw_8005: + ldi r6, 0x8005 + mvtc r6, dpsw + mvfc r7, dpsw + check 18 r7 0x8005 + + + exit0 diff --git a/sim/testsuite/sim/d10v/t-rac.s b/sim/testsuite/sim/d10v/t-rac.s new file mode 100644 index 00000000000..a452299d581 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-rac.s @@ -0,0 +1,20 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + ;; clear FX + loadpsw2 0x8004 + loadacc2 a0 0x80 0x0000 0x0000 + loadacc2 a1 0x00 0x0000 0x5000 + load r10 0x0123 + load r11 0x4567 +test_rac1: + RAC r10, a0, #-2 + checkpsw2 1 0x8008 + check2w2 2 r10 0x8000 0x0000 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-rachi.s b/sim/testsuite/sim/d10v/t-rachi.s new file mode 100644 index 00000000000..57589b5d96a --- /dev/null +++ b/sim/testsuite/sim/d10v/t-rachi.s @@ -0,0 +1,32 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + loadacc2 a0 0x00 0x7FFF 0x8000 +test_rachi_1: + rachi r4, a0, 0 + check 1 r4 0x7FFF + + + loadacc2 a0 0xFF 0x8000 0x1000 +test_rachi_2: + rachi r4, a0, 0 + check 2 r4 0x8000 + + + loadacc2 a0 0x00 0x1000 0xA000 +test_rachi_3: + rachi r4, a0, 0 + check 3 r4 0x1001 + + + loadacc2 a0 0xFF 0xA000 0x7FFF +test_rachi_4: + rachi r4, a0, 0 + check 4 r4 0xa000 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-rdt.s b/sim/testsuite/sim/d10v/t-rdt.s new file mode 100644 index 00000000000..947da8644d5 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-rdt.s @@ -0,0 +1,23 @@ +# mach: all +# output: +# sim: --environment operating +# as: -W + +.include "t-macros.i" + + start + + PSW_BITS = PSW_C|PSW_F0|PSW_F1 + + ldi r6, #success@word + mvtc r6, dpc + ldi r6, #PSW_BITS + mvtc r6, dpsw + +test_rdt: + RTD + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 diff --git a/sim/testsuite/sim/d10v/t-rep.s b/sim/testsuite/sim/d10v/t-rep.s new file mode 100644 index 00000000000..433aff1e4ef --- /dev/null +++ b/sim/testsuite/sim/d10v/t-rep.s @@ -0,0 +1,49 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + + + ;; Check that the instruction @REP_E is executed when it + ;; is reached using a branch instruction + + ldi r2, 1 +test_rep_1: + rep r2, end_rep_1 + nop || nop + nop || nop + nop || nop + nop || nop + ldi r3, 46 + bra end_rep_1 + ldi r3, 42 +end_rep_1: + addi r3, 1 + + check 1 r3 47 + + + ;; Check that the loop is executed the correct number of times + + ldi r2, 10 + ldi r3, 0 + ldi r4, 0 +test_rep_2: + rep r2, end_rep_2 + nop || nop + nop || nop + nop || nop + nop || nop + nop || nop + addi r3, 1 +end_rep_2: + addi r4, 1 + + check 2 r3 10 + check 3 r4 10 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-rie-xx.s b/sim/testsuite/sim/d10v/t-rie-xx.s new file mode 100644 index 00000000000..fa6b4fc383a --- /dev/null +++ b/sim/testsuite/sim/d10v/t-rie-xx.s @@ -0,0 +1,16 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_RIE&DMAP_MASK)+DMAP_BASE PSW_BITS test_rie_xx + +test_rie_xx: + .short 0xe120, 0x0000 ;; Example of RIE code + nop + exit47 diff --git a/sim/testsuite/sim/d10v/t-rte.s b/sim/testsuite/sim/d10v/t-rte.s new file mode 100644 index 00000000000..392f11812f1 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-rte.s @@ -0,0 +1,22 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = PSW_C|PSW_F0|PSW_F1 + + ldi r6, #success@word + mvtc r6, bpc + ldi r6, #PSW_BITS + mvtc r6, bpsw + +test_rte: + RTE + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 diff --git a/sim/testsuite/sim/d10v/t-sac.s b/sim/testsuite/sim/d10v/t-sac.s new file mode 100644 index 00000000000..84c31d74c3b --- /dev/null +++ b/sim/testsuite/sim/d10v/t-sac.s @@ -0,0 +1,27 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +test_sac_1: + loadacc2 a0 0x00 0xAFFF 0x0000 + sac r4, a0 + check 1 r4 0x7FFF + check 2 r5 0xFFFF + +test_sac_2: + loadacc2 a0 0xFF 0x7000 0x0000 + sac r4, a0 + check 3 r4 0x8000 + check 4 r5 0x0000 + +test_sac_3: + loadacc2 a0 0x00 0x1000 0xA000 + sac r4, a0 + check 5 r4 0x1000 + check 6 r5 0xA000 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-sachi.s b/sim/testsuite/sim/d10v/t-sachi.s new file mode 100644 index 00000000000..b9ed0e71a01 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-sachi.s @@ -0,0 +1,26 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +test_sachi_1: + loadacc2 a0 0x00 0xAFFF 0x0000 + sachi r4, a0 + check 1 r4 0x7FFF + + +test_sachi_2: + loadacc2 a0 0xFF 0x8000 0x1000 + sachi r4, a0 + check 2 r4 0x8000 + + +test_sachi_3: + loadacc2 a0 0x00 0x1000 0xA000 + sachi r4, a0 + check 3 r4 0x1000 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-sadd.s b/sim/testsuite/sim/d10v/t-sadd.s new file mode 100644 index 00000000000..fb463d91737 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-sadd.s @@ -0,0 +1,42 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + PSW_BITS = PSW_FX|PSW_ST|PSW_SM + loadpsw2 PSW_BITS + + ;; Test normal sadd + + loadacc2 a0 0x00 0x7fff 0xffff + loadacc2 a1 0xff 0x8000 0x0000 + sadd a1, a0 + checkacc2 1 a0 0x00 0x7fff 0xffff + checkacc2 2 a1 0xff 0x8000 0x7fff + + ;; Test overflow + + loadacc2 a0 0x00 0x0000 0x0000 + loadacc2 a1 0x01 0x8000 0x0000 + sadd a1, a0 + checkacc2 3 a0 0x00 0x0000 0x0000 + checkacc2 4 a1 0x00 0x7fff 0xffff + + loadacc2 a0 0x00 0xffff 0xffff + loadacc2 a1 0x00 0xffff 0xffff + sadd a1, a0 + checkacc2 5 a1 0x00 0x7fff 0xffff + checkacc2 6 a0 0x00 0xffff 0xffff + + ;; Test underflow + + loadacc2 a0 0x00 0x0000 0x0000 + loadacc2 a1 0x80 0x8000 0x0000 + sadd a1, a0 + checkacc2 7 a0 0x00 0x0000 0x0000 + checkacc2 8 a1 0xff 0x8000 0x0000 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-slae.s b/sim/testsuite/sim/d10v/t-slae.s new file mode 100644 index 00000000000..8236fa2fd77 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-slae.s @@ -0,0 +1,43 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +test_slae_1: + loadpsw2 PSW_ST|PSW_FX + loadacc2 a0 0x00 0x0AFF 0xF000 + ldi r0, 4 + slae a0, r0 + checkacc2 1 a0 0x00 0x7FFF 0xFFFF + +test_slae_2: + loadpsw2 PSW_ST|PSW_FX + loadacc2 a0 0xFF 0xF700 0x1000 + ldi r0, 4 + slae a0, r0 + checkacc2 2 a0 0xFF 0x8000 0x0000 + +test_slae_3: + loadpsw2 PSW_ST|PSW_FX + loadacc2 a0 0x00 0x0010 0xA000 + ldi r0, 4 + slae a0, r0 + checkacc2 3 a0 0x00 0x010A 0x0000 + +test_slae_4: + loadpsw2 0 + loadacc2 a0 0x00 0x0010 0xA000 + ldi r0, 4 + slae a0, r0 + checkacc2 4 a0 0x00 0x010A 0x0000 + +test_slae_5: + loadacc2 a0 0x00 0x0010 0xA000 + ldi r0, -4 + slae a0, r0 + checkacc2 4 a0 0x00 0x0001 0x0A00 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-sp.s b/sim/testsuite/sim/d10v/t-sp.s new file mode 100644 index 00000000000..df443b90487 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-sp.s @@ -0,0 +1,21 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +;;; Read/Write values to SPU/SPI + + loadpsw2 0 + ldi sp, 0xdead + loadpsw2 PSW_SM + ldi sp, 0xbeef + + loadpsw2 0 + check 1 sp 0xdead + loadpsw2 PSW_SM + check 2 sp 0xbeef + + exit0 diff --git a/sim/testsuite/sim/d10v/t-sub.s b/sim/testsuite/sim/d10v/t-sub.s new file mode 100644 index 00000000000..57b99e68efe --- /dev/null +++ b/sim/testsuite/sim/d10v/t-sub.s @@ -0,0 +1,46 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +;; The d10v implements negated addition for subtraction + + .macro check_sub s x y r c + ;; clear carry + ldi r6,#0x8004 + mvtc r6,cr0 + ;; subtract + ldi r10,#\x + ldi r11,#\y + sub r10, r11 + ;; verify result + ldi r12, #\r + cmpeq r10, r12 + brf0t 1f + ldi r6, 1 + ldi r2, #\s + trap 15 +1: + ;; verify carry + mvfc r6, cr0 + and3 r6, r6, #1 + cmpeqi r6, #\c + brf0t 1f + ldi r6, 1 + ldi r2, #\s + trap 15 +1: + .endm + +check_sub 1 0x0000 0x0000 0x0000 1 +check_sub 2 0x0000 0x0001 0xffff 0 +check_sub 3 0x0001 0x0000 0x0001 1 +check_sub 4 0x0001 0x0001 0x0000 1 +check_sub 5 0x0000 0x8000 0x8000 0 +check_sub 6 0x8000 0x0001 0x7fff 1 +check_sub 7 0x7fff 0x7fff 0x0000 1 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-sub2w.s b/sim/testsuite/sim/d10v/t-sub2w.s new file mode 100644 index 00000000000..5e8daee3518 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-sub2w.s @@ -0,0 +1,61 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +;; The d10v implements negated addition for subtraction + + .macro check_sub2w s x y r c v + + ;; clear carry + ldi r6,#0x8004 + mvtc r6,cr0 + + ;; load opnds + ld2w r6, @(1f,r0) + ld2w r8, @(2f,r0) + .data +1: .long \x +2: .long \y + .text + + ;; subtract + SUB2W r6, r8 + + ;; verify result + ld2w r10, @(1f,r0) + .data +1: .long \r + .text + cmpeq r6, r10 + brf0f 2f + cmpeq r7, r11 + brf0t 3f +2: ldi r4, 1 + ldi r0, \s + trap 15 +3: + + ;; verify carry + mvfc r6, cr0 + and3 r6, r6, #1 + cmpeqi r6, #\c + brf0t 1f + ldi r4, 1 + ldi r0, \s + trap 15 +1: + .endm + +check_sub2w 1 0x00000000 0x00000000 0x00000000 1 0 +check_sub2w 2 0x00000000 0x00000001 0xffffffff 0 0 +check_sub2w 3 0x00000001 0x00000000 0x00000001 1 0 +check_sub2w 3 0x00000001 0x00000001 0x00000000 1 0 +check_sub2w 5 0x00000000 0x80000000 0x80000000 0 1 +check_sub2w 6 0x80000000 0x00000001 0x7fffffff 1 1 +check_sub2w 7 0x7fffffff 0x7fffffff 0x00000000 1 0 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-subi.s b/sim/testsuite/sim/d10v/t-subi.s new file mode 100644 index 00000000000..dd4b2be61a5 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-subi.s @@ -0,0 +1,43 @@ +# mach: all +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + +;; The d10v implements negated addition for subtraction + + .macro check_subi s x y r c v + ;; clear carry + ldi r6,#0x8004 + mvtc r6,cr0 + ;; subtract + ldi r10,#\x + SUBI r10,#\y + ;; verify result + ldi r11, #\r + cmpeq r10, r11 + brf0t 1f + ldi r6, 1 + ldi r2, \s + trap 15 +1: + ;; verify carry + mvfc r6, cr0 + and3 r6, r6, #1 + cmpeqi r6, #\c + brf0t 1f + ldi r6, 1 + ldi r2, \s + trap 15 +1: + .endm + + check_subi 1 0000 0x0000 0xfff0 00 ;; 0 - 0x10 + check_subi 2 0x0000 0x0001 0xffff 0 0 + check_subi 3 0x0001 0x0000 0xfff1 0 0 + check_subi 4 0x0001 0x0001 0x0000 1 0 + check_subi 5 0x8000 0x0001 0x7fff 1 1 + + exit0 diff --git a/sim/testsuite/sim/d10v/t-trap.s b/sim/testsuite/sim/d10v/t-trap.s new file mode 100644 index 00000000000..7e5336cbdf6 --- /dev/null +++ b/sim/testsuite/sim/d10v/t-trap.s @@ -0,0 +1,10 @@ +# mach: all +# status: 47 +# output: +# sim: --environment operating + +.include "t-macros.i" + + start + + exit47 |