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* sim: testsuite: flatten treeMike Frysinger2021-01-152858-494321/+0
* sim: d10v: relocate tests & clean up test harnessMike Frysinger2021-01-1550-0/+1810
* sim: frv: clean up redundant test coverageMike Frysinger2021-01-156-0/+236
* sim: m32r: clean up redundant test coverageMike Frysinger2021-01-152-0/+15
* sim: testsuite: allow tests to declare expected exit statusMike Frysinger2021-01-153-2/+14
* sim: replace rindex with strrchrMike Frysinger2021-01-092-2/+6
* sim: sh64: delete portMike Frysinger2021-01-09390-13495/+0
* sim: ChangeLog: move arch-specific entries into the arch dirMike Frysinger2021-01-071-0/+20
* sim: cris: disable test that crashes the linkerMike Frysinger2021-01-072-1/+10
* sim: cris: use -sim with C tests for cris-elf targetsMike Frysinger2021-01-072-0/+8
* fix paths in ChangeLogMike Frysinger2021-01-071-5/+5
* sim: cris: fix C tests with newer toolchainsMike Frysinger2021-01-0711-2/+21
* sim: fr30: delete unused testsuiteMike Frysinger2021-01-05107-7226/+0
* sim: h8300: fix test mach markersMike Frysinger2021-01-0510-9/+15
* sim: h8300: simplify testsuite runnerMike Frysinger2021-01-052-61/+15
* sim: stdlib.h for abs()Mike Frysinger2021-01-042-0/+5
* Update copyright year range in all GDB filesJoel Brobecker2021-01-0155-55/+55
* sim: pru: Add support for LMBD instructionDimitar Dimitrov2020-11-122-0/+65
* bpf: simulator: correct div, mod insn semanticsDavid Faust2020-09-082-17/+40
* MSP430: sim: Fix incorrect simulation of unsigned widening multiplyJozef Lawrynowicz2020-08-052-0/+59
* sim: eBPF simulatorJose E. Marchesi2020-08-0412-0/+842
* MSP430: Fix simulator execution of RRUX instructionJozef Lawrynowicz2020-01-222-0/+18
* Update copyright year range in all GDB files.Joel Brobecker2020-01-0154-54/+54
* Add testsuite for the PRU simulator portDimitar Dimitrov2019-09-2312-0/+575
* sim/testsuite/or1k: Add tests for unordered comparesStafford Horne2019-06-133-0/+202
* sim/testsuite/or1k: Add test case for l.adrp instructionStafford Horne2019-06-132-0/+77
* sim/testsuite/or1k: Add test for 64-bit fpu operationsStafford Horne2019-06-132-0/+176
* Update copyright year range in all GDB files.Joel Brobecker2019-01-0139-39/+39
* or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson2018-10-053-65/+61
* Update copyright year range in all GDB filesJoel Brobecker2018-01-0239-39/+39
* sim: testsuite: add testsuite for or1k simPeter Gavin2017-12-1226-0/+6501
* Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson2017-04-2212-14/+341
* Add support for fcvtl and fcvtl2.Jim Wilson2017-04-082-0/+61
* Support the fcmXX zero instructions.Jim Wilson2017-04-082-0/+81
* Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson2017-03-252-0/+21
* Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson2017-03-033-5/+68
* Add missing smov support, and clean up existing umov support.Jim Wilson2017-02-252-0/+93
* Add missing cnt (popcount) instruction support.Jim Wilson2017-02-252-0/+37
* Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson2017-02-196-19/+126
* Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson2017-02-142-0/+105
* Fix bit/bif instructions.Jim Wilson2017-02-142-0/+93
* Add ldn/stn single support, fix ldnr support.Jim Wilson2017-02-144-0/+404
* Add support for cmtst.Jim Wilson2017-01-232-0/+108
* Fixes for addv and xtn2 instructions.Jim Wilson2017-01-173-0/+134
* Fix problems with the implementation of the uzp1 and uzp2 instructions.Jim Wilson2017-01-092-0/+218
* Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.Jim Wilson2017-01-046-0/+547
* update copyright year range in GDB filesJoel Brobecker2017-01-0114-14/+14
* Fix bugs with float compare and Inf operands.Jim Wilson2016-12-212-0/+150
* Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson2016-12-135-9/+288
* Change copyright owner to FSF in sim/testsuite/sim/mips/hilo-hazard-4.sJoel Brobecker2016-01-062-2/+5