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| author | Daniel Boulby <daniel.boulby@arm.com> | 2022-01-19 11:20:05 +0000 |
|---|---|---|
| committer | Daniel Boulby <daniel.boulby@arm.com> | 2022-01-31 11:27:11 +0000 |
| commit | 97215e0f25014864a4241bb3f992e5946b14dfd3 (patch) | |
| tree | bc6f558127b668c05d60bb701d68f9d794003f93 /bl1 | |
| parent | 50e06da16edc8f7fd6196e8fe4d48835358f3fa1 (diff) | |
| download | arm-trusted-firmware-97215e0f25014864a4241bb3f992e5946b14dfd3.tar.gz | |
refactor(el3-runtime): add prepare_el3_entry func
In the next patch we add an extra step of setting the PSTATE
registers to a known state on el3 entry. In this patch we create
the function prepare_el3_entry to wrap the steps needed for before
el3 entry. For now this is only save_gp_pmcr_pauth_regs.
Change-Id: Ie26dc8d89bfaec308769165d2649e84d41be196c
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_exceptions.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 9dc9e6cd5..c54219fc1 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -224,7 +224,7 @@ smc_handler: * TODO: Revisit to store only SMCCC specified registers. * ----------------------------------------------------- */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* ----------------------------------------------------- |