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| author | Andrew Davis <afd@ti.com> | 2022-09-01 11:02:59 -0500 |
|---|---|---|
| committer | Andrew Davis <afd@ti.com> | 2023-01-12 18:42:57 -0600 |
| commit | 10d5cf1b26f03d61a90cdcff5163965fa48e291c (patch) | |
| tree | 2da1efbb01df31974376b9d916cc4066363b37da /plat/ti | |
| parent | 81858a353f8e45f5cc57ce855188043b1745ea08 (diff) | |
| download | arm-trusted-firmware-10d5cf1b26f03d61a90cdcff5163965fa48e291c.tar.gz | |
feat(ti): disable L2 dataless UniqueClean evictions
Do this early before we enable caching as a workaround for ARM A72
Errata #854172.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic878fdb49e598da0ea6ade012712f8f57023678e
Diffstat (limited to 'plat/ti')
| -rw-r--r-- | plat/ti/k3/common/k3_helpers.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S index 6742e74f1..da94c1644 100644 --- a/plat/ti/k3/common/k3_helpers.S +++ b/plat/ti/k3/common/k3_helpers.S @@ -118,6 +118,12 @@ a72: orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE msr CORTEX_A72_L2CTLR_EL1, x0 + + mrs x0, CORTEX_A72_L2ACTLR_EL1 + /* Enable L2 UniqueClean evictions with data */ + orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN + msr CORTEX_A72_L2ACTLR_EL1, x0 + isb ret endfunc plat_reset_handler |