diff options
| author | Andrew Davis <afd@ti.com> | 2023-01-12 09:32:33 -0600 |
|---|---|---|
| committer | Andrew Davis <afd@ti.com> | 2023-01-12 18:42:57 -0600 |
| commit | 5668db72b724dc256d9b300f6938a08625624a48 (patch) | |
| tree | bbac1f4654f134d58e36ee55a7bb4fd51663babe /plat/ti | |
| parent | 10d5cf1b26f03d61a90cdcff5163965fa48e291c (diff) | |
| download | arm-trusted-firmware-5668db72b724dc256d9b300f6938a08625624a48.tar.gz | |
feat(ti): set snoop-delayed exclusive handling on A72 cores
Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.
TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.
As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9
Diffstat (limited to 'plat/ti')
| -rw-r--r-- | plat/ti/k3/board/j784s4/board.mk | 4 | ||||
| -rw-r--r-- | plat/ti/k3/common/k3_helpers.S | 7 |
2 files changed, 11 insertions, 0 deletions
diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk index c7fcb0016..68ba1b527 100644 --- a/plat/ti/k3/board/j784s4/board.mk +++ b/plat/ti/k3/board/j784s4/board.mk @@ -21,6 +21,10 @@ $(eval $(call add_define,K3_SEC_PROXY_LITE)) K3_DATA_RAM_4_LATENCY := 1 $(eval $(call add_define,K3_DATA_RAM_4_LATENCY)) +# Delay snoop exclusive handling for J784s4 +K3_EXCLUSIVE_SNOOP_DELAY := 1 +$(eval $(call add_define,K3_EXCLUSIVE_SNOOP_DELAY)) + # System coherency is managed in hardware USE_COHERENT_MEM := 1 diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S index da94c1644..f997b4678 100644 --- a/plat/ti/k3/common/k3_helpers.S +++ b/plat/ti/k3/common/k3_helpers.S @@ -124,6 +124,13 @@ a72: orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN msr CORTEX_A72_L2ACTLR_EL1, x0 +#if K3_EXCLUSIVE_SNOOP_DELAY + mrs x0, CORTEX_A72_CPUACTLR_EL1 + /* Set Snoop-delayed exclusive handling */ + orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP + msr CORTEX_A72_CPUACTLR_EL1, x0 +#endif + isb ret endfunc plat_reset_handler |